* [PATCH 3/6] Andes nds32: libgcc of nds32 porting.
@ 2013-07-08 11:01 Chung-Ju Wu
2013-07-10 0:08 ` Joseph S. Myers
0 siblings, 1 reply; 5+ messages in thread
From: Chung-Ju Wu @ 2013-07-08 11:01 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 722 bytes --]
Hi,
This patch consists of libgcc parts for nds32 target.
We support two kinds of libgcc implementation: newlib and mculib,
controlled by --with-nds32-lib=[newlib|mculib] when configure gcc.
In newlib setting, we use default libgcc impelmentation provided
by gcc, and take soft-fp as our software floating point library.
As for mculib setting, many modules have been hand-coded with
assembly codes for code size consideration.
We also have dozens of assembly codes under the directory 'isr-library'
for creating libnds32_isr.a which is used for interrupt support
in nds32 target.
libgcc/
2013-07-08 Chung-Ju Wu <jasonwucj@gmail.com>
Shiva Chen <shiva0217@gmail.com>
* config/nds32 : New directory and files.
[-- Attachment #2: 3-nds32-libgcc.patch --]
[-- Type: application/octet-stream, Size: 273174 bytes --]
diff --git libgcc/config/nds32/crtzero.S libgcc/config/nds32/crtzero.S
new file mode 100644
index 0000000..8d6d2a4
--- /dev/null
+++ libgcc/config/nds32/crtzero.S
@@ -0,0 +1,84 @@
+!*******************************************************************
+!******************** Please DO NOT modify this file****************
+!*******************************************************************
+
+!!==============================================================================
+!!
+!! crtzero.S
+!!
+!! This is JUST A SAMPLE of nds32 startup code !!
+!! You can refer this content and implement
+!! the actual one in newlib/mculib.
+!!
+!!==============================================================================
+
+ .file "crtzero.S"
+
+!!------------------------------------------------------------------------------
+!! Jump to start up code
+!!------------------------------------------------------------------------------
+ .section .nds32_init, "ax"
+ j _start
+
+!!------------------------------------------------------------------------------
+!! Startup code implementation
+!!------------------------------------------------------------------------------
+ .section .text
+ .global _start
+ .weak _SDA_BASE_
+ .weak _FP_BASE_
+ .align 2
+ .func _start
+ .type _start, @function
+_start:
+.L_fp_gp_lp_init:
+ la $fp, _FP_BASE_ ! init $fp
+ la $gp, _SDA_BASE_ ! init $gp for small data access
+ movi $lp, 0 ! init $lp
+
+.L_stack_init:
+ la $sp, _stack ! init $sp
+ movi $r0, -8 ! align $sp to 8-byte (use 0xfffffff8)
+ and $sp, $sp, $r0 ! align $sp to 8-byte (filter out lower 3-bit)
+
+.L_bss_init:
+ ! clear BSS, this process can be 4 time faster if data is 4 byte aligned
+ ! if so, use swi.p instead of sbi.p
+ ! the related stuff are defined in linker script
+ la $r0, _edata ! get the starting addr of bss
+ la $r2, _end ! get ending addr of bss
+ beq $r0, $r2, .L_call_main ! if no bss just do nothing
+ movi $r1, 0 ! should be cleared to 0
+.L_clear_bss:
+ sbi.p $r1, [$r0], 1 ! Set 0 to bss
+ bne $r0, $r2, .L_clear_bss ! Still bytes left to set
+
+!.L_stack_heap_check:
+! la $r0, _end ! init heap_end
+! s.w $r0, heap_end ! save it
+
+
+!.L_init_argc_argv:
+! ! argc/argv initialization if necessary; default implementation is in crt1.o
+! la $r9, _arg_init ! load address of _arg_init?
+! beqz $r9, .L4 ! has _arg_init? no, go check main()
+! addi $sp, $sp, -512 ! allocate space for command line + arguments
+! move $r6, $sp ! r6 = buffer addr of cmd line
+! move $r0, $r6 ! r0 = buffer addr of cmd line
+! syscall 6002 ! get cmd line
+! move $r0, $r6 ! r0 = buffer addr of cmd line
+! addi $r1, $r6, 256 ! r1 = argv
+! jral $r9 ! init argc/argv
+! addi $r1, $r6, 256 ! r1 = argv
+
+.L_call_main:
+ ! call main() if main() is provided
+ la $r15, main ! load address of main
+ jral $r15 ! call main
+
+.L_terminate_program:
+ syscall 0x1 ! use syscall 0x1 to terminate program
+ .size _start, .-_start
+ .end
+
+!! ------------------------------------------------------------------------
diff --git libgcc/config/nds32/initfini.c libgcc/config/nds32/initfini.c
new file mode 100644
index 0000000..7235148
--- /dev/null
+++ libgcc/config/nds32/initfini.c
@@ -0,0 +1,159 @@
+/* .init/.fini section handling + C++ global constructor/destructor
+ handling of Andes NDS32 cpu for GNU compiler.
+ This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
+ Copyright (C) 2012-2013 Free Software Foundation, Inc.
+ Contributed by Andes Technology Corporation.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+/* Declare a pointer to void function type. */
+typedef void (*func_ptr) (void);
+
+#ifdef CRT_BEGIN
+
+/* NOTE: In order to be able to support SVR4 shared libraries, we arrange
+ to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__,
+ __DTOR_END__ } per root executable and also one set of these symbols
+ per shared library. So in any given whole process image, we may have
+ multiple definitions of each of these symbols. In order to prevent
+ these definitions from conflicting with one another, and in order to
+ ensure that the proper lists are used for the initialization/finalization
+ of each individual shared library (respectively), we give these symbols
+ only internal (i.e. `static') linkage, and we also make it a point to
+ refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
+ symbol in crtinit.o, where they are defined. */
+
+static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
+ = { (func_ptr) (-1) };
+
+static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
+ = { (func_ptr) (-1) };
+
+/* Run all the global destructors on exit from the program. */
+
+/* Some systems place the number of pointers in the first word of the
+ table. On SVR4 however, that word is -1. In all cases, the table is
+ null-terminated. On SVR4, we start from the beginning of the list and
+ invoke each per-compilation-unit destructor routine in order
+ until we find that null.
+
+ Note that this function MUST be static. There will be one of these
+ functions in each root executable and one in each shared library, but
+ although they all have the same code, each one is unique in that it
+ refers to one particular associated `__DTOR_LIST__' which belongs to the
+ same particular root executable or shared library file. */
+
+static void __do_global_dtors (void)
+asm ("__do_global_dtors") __attribute__ ((section (".text")));
+
+static void
+__do_global_dtors (void)
+{
+ func_ptr *p;
+ for (p = __DTOR_LIST__ + 1; *p; p++)
+ (*p) ();
+}
+
+/* .init section start.
+ This must appear at the start of the .init section. */
+
+asm ("\n\
+ .section .init\n\
+ .global _init\n\
+ .type _init, @function\n\
+_init:\n\
+ ! 1. store $fp\n\
+ ! 2. adjust $fp by $sp\n\
+ ! 3. adjust $sp\n\
+");
+
+/* .fini section start.
+ This must appear at the start of the .fini section. */
+
+asm ("\n\
+ .section .fini\n\
+ .global _fini\n\
+ .type _fini, @function\n\
+_fini:\n\
+ ! 1. store $fp\n\
+ ! 2. adjust $fp by $sp\n\
+ ! 3. adjust $sp\n\
+ ! 4. call __do_global_dtors\n\
+ j __do_global_dtors\n\
+");
+
+#endif /* CRT_BEGIN */
+
+#ifdef CRT_END
+
+/* Define __dso_handle which would be needed for C++ library.
+ Since our elf-toolchain only builds programs with static link,
+ we can directly define 'void *__dso_handle = 0'. */
+void *__dso_handle = 0;
+
+/* Put a word containing zero at the end of each of our two lists of function
+ addresses. Note that the words defined here go into the .ctors and .dtors
+ sections of the crtend.o file, and since that file is always linked in
+ last, these words naturally end up at the very ends of the two lists
+ contained in these two sections. */
+
+static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
+ = { (func_ptr) 0 };
+
+static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
+ = { (func_ptr) 0 };
+
+/* Run all global constructors for the program.
+ Note that they are run in reverse order. */
+
+static void __do_global_ctors (void)
+asm ("__do_global_ctors") __attribute__ ((section (".text")));
+
+static void
+__do_global_ctors (void)
+{
+ func_ptr *p;
+ for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
+ (*p) ();
+}
+
+/* .init section end.
+ This must live at the end of the .init section. */
+
+asm ("\n\
+ .section .init\n\
+ ! 1. call __do_global_ctors\n\
+ ! 2. adjust back $sp\n\
+ ! 3. restore $fp\n\
+ j __do_global_ctors\n\
+");
+
+/* .fini section end.
+ This must live at the end of the .fini section. */
+
+asm ("\n\
+ .section .fini\n\
+ ! 1. adjust back $sp\n\
+ ! 2. restore $fp\n\
+");
+
+#endif /* CRT_END */
diff --git libgcc/config/nds32/isr-library/adj_intr_lvl.inc libgcc/config/nds32/isr-library/adj_intr_lvl.inc
new file mode 100644
index 0000000..fbe1f6c
--- /dev/null
+++ libgcc/config/nds32/isr-library/adj_intr_lvl.inc
@@ -0,0 +1,13 @@
+.macro ADJ_INTR_LVL
+#if defined(NDS32_NESTED) /* Nested handler. */
+ mfsr $r3, $PSW
+ addi $r3, $r3, #-0x1
+ mtsr $r3, $PSW
+#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */
+ /* Save ipc and ipsw and lower INT level. */
+ mfsr $r3, $PSW
+ addi $r3, $r3, #-0x2
+ mtsr $r3, $PSW
+#else /* Not nested handler. */
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/excp_isr.S libgcc/config/nds32/isr-library/excp_isr.S
new file mode 100644
index 0000000..0706a4a
--- /dev/null
+++ libgcc/config/nds32/isr-library/excp_isr.S
@@ -0,0 +1,107 @@
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
+ .align 1
+/*
+ First Level Handlers
+ 1. First Level Handlers are invokded in vector section via jump instruction
+ with specific names for different configurations.
+ 2. Naming Format: _nds32_e_SR_NT for exception handlers.
+ _nds32_i_SR_NT for interrupt handlers.
+ 2.1 All upper case letters are replaced with specific lower case letters encodings.
+ 2.2 SR: Saved Registers
+ sa: Save All regs (context)
+ ps: Partial Save (all caller-saved regs)
+ 2.3 NT: Nested Type
+ ns: nested
+ nn: not nested
+ nr: nested ready
+*/
+
+/*
+ This is original 16-byte vector size version.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .globl _nds32_e_sa_ns
+ .type _nds32_e_sa_ns, @function
+_nds32_e_sa_ns:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_e_sa_nr
+ .type _nds32_e_sa_nr, @function
+_nds32_e_sa_nr:
+#else /* Not nested handler. */
+ .globl _nds32_e_sa_nn
+ .type _nds32_e_sa_nn, @function
+_nds32_e_sa_nn:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .globl _nds32_e_ps_ns
+ .type _nds32_e_ps_ns, @function
+_nds32_e_ps_ns:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_e_ps_nr
+ .type _nds32_e_ps_nr, @function
+_nds32_e_ps_nr:
+#else /* Not nested handler. */
+ .globl _nds32_e_ps_nn
+ .type _nds32_e_ps_nn, @function
+_nds32_e_ps_nn:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+ This is 16-byte vector size version.
+ The vector id was restored into $r0 in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+ SAVE_ALL
+#else
+ SAVE_PARTIAL
+#endif
+ /* Prepare to call 2nd level handler. */
+ la $r2, _nds32_jmptbl_00
+ lw $r2, [$r2 + $r0 << #2]
+ ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
+ jral $r2
+ /* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+ RESTORE_ALL
+#else
+ RESTORE_PARTIAL
+#endif
+ iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .size _nds32_e_sa_ns, .-_nds32_e_sa_ns
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_e_sa_nr, .-_nds32_e_sa_nr
+#else /* Not nested handler. */
+ .size _nds32_e_sa_nn, .-_nds32_e_sa_nn
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .size _nds32_e_ps_ns, .-_nds32_e_ps_ns
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_e_ps_nr, .-_nds32_e_ps_nr
+#else /* Not nested handler. */
+ .size _nds32_e_ps_nn, .-_nds32_e_ps_nn
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git libgcc/config/nds32/isr-library/excp_isr_4b.S libgcc/config/nds32/isr-library/excp_isr_4b.S
new file mode 100644
index 0000000..266b20e
--- /dev/null
+++ libgcc/config/nds32/isr-library/excp_isr_4b.S
@@ -0,0 +1,108 @@
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
+ .align 1
+/*
+ First Level Handlers
+ 1. First Level Handlers are invokded in vector section via jump instruction
+ with specific names for different configurations.
+ 2. Naming Format: _nds32_e_SR_NT for exception handlers.
+ _nds32_i_SR_NT for interrupt handlers.
+ 2.1 All upper case letters are replaced with specific lower case letters encodings.
+ 2.2 SR: Saved Registers
+ sa: Save All regs (context)
+ ps: Partial Save (all caller-saved regs)
+ 2.3 NT: Nested Type
+ ns: nested
+ nn: not nested
+ nr: nested ready
+*/
+
+/*
+ This is 4-byte vector size version.
+ The "_4b" postfix was added for 4-byte version symbol.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .globl _nds32_e_sa_ns_4b
+ .type _nds32_e_sa_ns_4b, @function
+_nds32_e_sa_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_e_sa_nr_4b
+ .type _nds32_e_sa_nr_4b, @function
+_nds32_e_sa_nr_4b:
+#else /* Not nested handler. */
+ .globl _nds32_e_sa_nn_4b
+ .type _nds32_e_sa_nn_4b, @function
+_nds32_e_sa_nn_4b:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .globl _nds32_e_ps_ns_4b
+ .type _nds32_e_ps_ns_4b, @function
+_nds32_e_ps_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_e_ps_nr_4b
+ .type _nds32_e_ps_nr_4b, @function
+_nds32_e_ps_nr_4b:
+#else /* Not nested handler. */
+ .globl _nds32_e_ps_nn_4b
+ .type _nds32_e_ps_nn_4b, @function
+_nds32_e_ps_nn_4b:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+ This is 4-byte vector size version.
+ The vector id was restored into $lp in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+ SAVE_ALL_4B
+#else
+ SAVE_PARTIAL_4B
+#endif
+ /* Prepare to call 2nd level handler. */
+ la $r2, _nds32_jmptbl_00
+ lw $r2, [$r2 + $r0 << #2]
+ ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
+ jral $r2
+ /* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+ RESTORE_ALL
+#else
+ RESTORE_PARTIAL
+#endif
+ iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .size _nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b
+#else /* Not nested handler. */
+ .size _nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .size _nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b
+#else /* Not nested handler. */
+ .size _nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git libgcc/config/nds32/isr-library/intr_isr.S libgcc/config/nds32/isr-library/intr_isr.S
new file mode 100644
index 0000000..f9e8cd2
--- /dev/null
+++ libgcc/config/nds32/isr-library/intr_isr.S
@@ -0,0 +1,107 @@
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
+ .align 1
+/*
+ First Level Handlers
+ 1. First Level Handlers are invokded in vector section via jump instruction
+ with specific names for different configurations.
+ 2. Naming Format: _nds32_e_SR_NT for exception handlers.
+ _nds32_i_SR_NT for interrupt handlers.
+ 2.1 All upper case letters are replaced with specific lower case letters encodings.
+ 2.2 SR: Saved Registers
+ sa: Save All regs (context)
+ ps: Partial Save (all caller-saved regs)
+ 2.3 NT: Nested Type
+ ns: nested
+ nn: not nested
+ nr: nested ready
+*/
+
+/*
+ This is original 16-byte vector size version.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .globl _nds32_i_sa_ns
+ .type _nds32_i_sa_ns, @function
+_nds32_i_sa_ns:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_i_sa_nr
+ .type _nds32_i_sa_nr, @function
+_nds32_i_sa_nr:
+#else /* Not nested handler. */
+ .globl _nds32_i_sa_nn
+ .type _nds32_i_sa_nn, @function
+_nds32_i_sa_nn:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .globl _nds32_i_ps_ns
+ .type _nds32_i_ps_ns, @function
+_nds32_i_ps_ns:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_i_ps_nr
+ .type _nds32_i_ps_nr, @function
+_nds32_i_ps_nr:
+#else /* Not nested handler. */
+ .globl _nds32_i_ps_nn
+ .type _nds32_i_ps_nn, @function
+_nds32_i_ps_nn:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+ This is 16-byte vector size version.
+ The vector id was restored into $r0 in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+ SAVE_ALL
+#else
+ SAVE_PARTIAL
+#endif
+ /* Prepare to call 2nd level handler. */
+ la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */
+ lw $r2, [$r2 + $r0 << #2]
+ ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
+ jral $r2
+ /* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+ RESTORE_ALL
+#else
+ RESTORE_PARTIAL
+#endif
+ iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .size _nds32_i_sa_ns, .-_nds32_i_sa_ns
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_i_sa_nr, .-_nds32_i_sa_nr
+#else /* Not nested handler. */
+ .size _nds32_i_sa_nn, .-_nds32_i_sa_nn
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .size _nds32_i_ps_ns, .-_nds32_i_ps_ns
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_i_ps_nr, .-_nds32_i_ps_nr
+#else /* Not nested handler. */
+ .size _nds32_i_ps_nn, .-_nds32_i_ps_nn
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git libgcc/config/nds32/isr-library/intr_isr_4b.S libgcc/config/nds32/isr-library/intr_isr_4b.S
new file mode 100644
index 0000000..6b255dc
--- /dev/null
+++ libgcc/config/nds32/isr-library/intr_isr_4b.S
@@ -0,0 +1,109 @@
+#include "save_mac_regs.inc"
+#include "save_fpu_regs.inc"
+#include "save_fpu_regs_00.inc"
+#include "save_fpu_regs_01.inc"
+#include "save_fpu_regs_02.inc"
+#include "save_fpu_regs_03.inc"
+#include "save_all.inc"
+#include "save_partial.inc"
+#include "adj_intr_lvl.inc"
+#include "restore_mac_regs.inc"
+#include "restore_fpu_regs_00.inc"
+#include "restore_fpu_regs_01.inc"
+#include "restore_fpu_regs_02.inc"
+#include "restore_fpu_regs_03.inc"
+#include "restore_fpu_regs.inc"
+#include "restore_all.inc"
+#include "restore_partial.inc"
+ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
+ .align 1
+/*
+ First Level Handlers
+ 1. First Level Handlers are invokded in vector section via jump instruction
+ with specific names for different configurations.
+ 2. Naming Format: _nds32_e_SR_NT for exception handlers.
+ _nds32_i_SR_NT for interrupt handlers.
+ 2.1 All upper case letters are replaced with specific lower case letters encodings.
+ 2.2 SR: Saved Registers
+ sa: Save All regs (context)
+ ps: Partial Save (all caller-saved regs)
+ 2.3 NT: Nested Type
+ ns: nested
+ nn: not nested
+ nr: nested ready
+*/
+
+/*
+ This is 4-byte vector size version.
+ The "_4b" postfix was added for 4-byte version symbol.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .globl _nds32_i_sa_ns_4b
+ .type _nds32_i_sa_ns_4b, @function
+_nds32_i_sa_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_i_sa_nr_4b
+ .type _nds32_i_sa_nr_4b, @function
+_nds32_i_sa_nr_4b:
+#else /* Not nested handler. */
+ .globl _nds32_i_sa_nn_4b
+ .type _nds32_i_sa_nn_4b, @function
+_nds32_i_sa_nn_4b:
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .globl _nds32_i_ps_ns_4b
+ .type _nds32_i_ps_ns_4b, @function
+_nds32_i_ps_ns_4b:
+#elif defined(NDS32_NESTED_READY)
+ .globl _nds32_i_ps_nr_4b
+ .type _nds32_i_ps_nr_4b, @function
+_nds32_i_ps_nr_4b:
+#else /* Not nested handler. */
+ .globl _nds32_i_ps_nn_4b
+ .type _nds32_i_ps_nn_4b, @function
+_nds32_i_ps_nn_4b:
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
+
+/*
+ This is 4-byte vector size version.
+ The vector id was restored into $lp in vector by compiler.
+*/
+#ifdef NDS32_SAVE_ALL_REGS
+ SAVE_ALL_4B
+#else
+ SAVE_PARTIAL_4B
+#endif
+ /* Prepare to call 2nd level handler. */
+ la $r2, _nds32_jmptbl_00
+ lw $r2, [$r2 + $r0 << #2]
+ addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */
+ ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
+ jral $r2
+ /* Restore used registers. */
+#ifdef NDS32_SAVE_ALL_REGS
+ RESTORE_ALL
+#else
+ RESTORE_PARTIAL
+#endif
+ iret
+
+#ifdef NDS32_SAVE_ALL_REGS
+#if defined(NDS32_NESTED)
+ .size _nds32_i_sa_ns_4b, .-_nds32_i_sa_ns_4b
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_i_sa_nr_4b, .-_nds32_i_sa_nr_4b
+#else /* Not nested handler. */
+ .size _nds32_i_sa_nn_4b, .-_nds32_i_sa_nn_4b
+#endif /* endif for Nest Type */
+#else /* not NDS32_SAVE_ALL_REGS */
+#if defined(NDS32_NESTED)
+ .size _nds32_i_ps_ns_4b, .-_nds32_i_ps_ns_4b
+#elif defined(NDS32_NESTED_READY)
+ .size _nds32_i_ps_nr_4b, .-_nds32_i_ps_nr_4b
+#else /* Not nested handler. */
+ .size _nds32_i_ps_nn_4b, .-_nds32_i_ps_nn_4b
+#endif /* endif for Nest Type */
+#endif /* not NDS32_SAVE_ALL_REGS */
diff --git libgcc/config/nds32/isr-library/jmptbl_vid00.S libgcc/config/nds32/isr-library/jmptbl_vid00.S
new file mode 100644
index 0000000..95817a3
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid00.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.00, "a"
+ .align 2
+ .weak _nds32_jmptbl_00
+ .type _nds32_jmptbl_00, @object
+_nds32_jmptbl_00:
+ .word 0
+ .size _nds32_jmptbl_00, .-_nds32_jmptbl_00
diff --git libgcc/config/nds32/isr-library/jmptbl_vid01.S libgcc/config/nds32/isr-library/jmptbl_vid01.S
new file mode 100644
index 0000000..0ad98dd
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid01.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.01, "a"
+ .align 2
+ .weak _nds32_jmptbl_01
+ .type _nds32_jmptbl_01, @object
+_nds32_jmptbl_01:
+ .word 0
+ .size _nds32_jmptbl_01, .-_nds32_jmptbl_01
diff --git libgcc/config/nds32/isr-library/jmptbl_vid02.S libgcc/config/nds32/isr-library/jmptbl_vid02.S
new file mode 100644
index 0000000..18566ac
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid02.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.02, "a"
+ .align 2
+ .weak _nds32_jmptbl_02
+ .type _nds32_jmptbl_02, @object
+_nds32_jmptbl_02:
+ .word 0
+ .size _nds32_jmptbl_02, .-_nds32_jmptbl_02
diff --git libgcc/config/nds32/isr-library/jmptbl_vid03.S libgcc/config/nds32/isr-library/jmptbl_vid03.S
new file mode 100644
index 0000000..2b11d1f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid03.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.03, "a"
+ .align 2
+ .weak _nds32_jmptbl_03
+ .type _nds32_jmptbl_03, @object
+_nds32_jmptbl_03:
+ .word 0
+ .size _nds32_jmptbl_03, .-_nds32_jmptbl_03
diff --git libgcc/config/nds32/isr-library/jmptbl_vid04.S libgcc/config/nds32/isr-library/jmptbl_vid04.S
new file mode 100644
index 0000000..7a2a972
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid04.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.04, "a"
+ .align 2
+ .weak _nds32_jmptbl_04
+ .type _nds32_jmptbl_04, @object
+_nds32_jmptbl_04:
+ .word 0
+ .size _nds32_jmptbl_04, .-_nds32_jmptbl_04
diff --git libgcc/config/nds32/isr-library/jmptbl_vid05.S libgcc/config/nds32/isr-library/jmptbl_vid05.S
new file mode 100644
index 0000000..bde0219
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid05.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.05, "a"
+ .align 2
+ .weak _nds32_jmptbl_05
+ .type _nds32_jmptbl_05, @object
+_nds32_jmptbl_05:
+ .word 0
+ .size _nds32_jmptbl_05, .-_nds32_jmptbl_05
diff --git libgcc/config/nds32/isr-library/jmptbl_vid06.S libgcc/config/nds32/isr-library/jmptbl_vid06.S
new file mode 100644
index 0000000..dc973b0
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid06.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.06, "a"
+ .align 2
+ .weak _nds32_jmptbl_06
+ .type _nds32_jmptbl_06, @object
+_nds32_jmptbl_06:
+ .word 0
+ .size _nds32_jmptbl_06, .-_nds32_jmptbl_06
diff --git libgcc/config/nds32/isr-library/jmptbl_vid07.S libgcc/config/nds32/isr-library/jmptbl_vid07.S
new file mode 100644
index 0000000..ba15125
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid07.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.07, "a"
+ .align 2
+ .weak _nds32_jmptbl_07
+ .type _nds32_jmptbl_07, @object
+_nds32_jmptbl_07:
+ .word 0
+ .size _nds32_jmptbl_07, .-_nds32_jmptbl_07
diff --git libgcc/config/nds32/isr-library/jmptbl_vid08.S libgcc/config/nds32/isr-library/jmptbl_vid08.S
new file mode 100644
index 0000000..7a9b84e
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid08.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.08, "a"
+ .align 2
+ .weak _nds32_jmptbl_08
+ .type _nds32_jmptbl_08, @object
+_nds32_jmptbl_08:
+ .word 0
+ .size _nds32_jmptbl_08, .-_nds32_jmptbl_08
diff --git libgcc/config/nds32/isr-library/jmptbl_vid09.S libgcc/config/nds32/isr-library/jmptbl_vid09.S
new file mode 100644
index 0000000..463de5f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid09.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.09, "a"
+ .align 2
+ .weak _nds32_jmptbl_09
+ .type _nds32_jmptbl_09, @object
+_nds32_jmptbl_09:
+ .word 0
+ .size _nds32_jmptbl_09, .-_nds32_jmptbl_09
diff --git libgcc/config/nds32/isr-library/jmptbl_vid10.S libgcc/config/nds32/isr-library/jmptbl_vid10.S
new file mode 100644
index 0000000..8aff575
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid10.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.10, "a"
+ .align 2
+ .weak _nds32_jmptbl_10
+ .type _nds32_jmptbl_10, @object
+_nds32_jmptbl_10:
+ .word 0
+ .size _nds32_jmptbl_10, .-_nds32_jmptbl_10
diff --git libgcc/config/nds32/isr-library/jmptbl_vid11.S libgcc/config/nds32/isr-library/jmptbl_vid11.S
new file mode 100644
index 0000000..ee6c863
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid11.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.11, "a"
+ .align 2
+ .weak _nds32_jmptbl_11
+ .type _nds32_jmptbl_11, @object
+_nds32_jmptbl_11:
+ .word 0
+ .size _nds32_jmptbl_11, .-_nds32_jmptbl_11
diff --git libgcc/config/nds32/isr-library/jmptbl_vid12.S libgcc/config/nds32/isr-library/jmptbl_vid12.S
new file mode 100644
index 0000000..58bc5de
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid12.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.12, "a"
+ .align 2
+ .weak _nds32_jmptbl_12
+ .type _nds32_jmptbl_12, @object
+_nds32_jmptbl_12:
+ .word 0
+ .size _nds32_jmptbl_12, .-_nds32_jmptbl_12
diff --git libgcc/config/nds32/isr-library/jmptbl_vid13.S libgcc/config/nds32/isr-library/jmptbl_vid13.S
new file mode 100644
index 0000000..559b223
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid13.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.13, "a"
+ .align 2
+ .weak _nds32_jmptbl_13
+ .type _nds32_jmptbl_13, @object
+_nds32_jmptbl_13:
+ .word 0
+ .size _nds32_jmptbl_13, .-_nds32_jmptbl_13
diff --git libgcc/config/nds32/isr-library/jmptbl_vid14.S libgcc/config/nds32/isr-library/jmptbl_vid14.S
new file mode 100644
index 0000000..acd620f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid14.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.14, "a"
+ .align 2
+ .weak _nds32_jmptbl_14
+ .type _nds32_jmptbl_14, @object
+_nds32_jmptbl_14:
+ .word 0
+ .size _nds32_jmptbl_14, .-_nds32_jmptbl_14
diff --git libgcc/config/nds32/isr-library/jmptbl_vid15.S libgcc/config/nds32/isr-library/jmptbl_vid15.S
new file mode 100644
index 0000000..5fc8ed0
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid15.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.15, "a"
+ .align 2
+ .weak _nds32_jmptbl_15
+ .type _nds32_jmptbl_15, @object
+_nds32_jmptbl_15:
+ .word 0
+ .size _nds32_jmptbl_15, .-_nds32_jmptbl_15
diff --git libgcc/config/nds32/isr-library/jmptbl_vid16.S libgcc/config/nds32/isr-library/jmptbl_vid16.S
new file mode 100644
index 0000000..b1c01a0
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid16.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.16, "a"
+ .align 2
+ .weak _nds32_jmptbl_16
+ .type _nds32_jmptbl_16, @object
+_nds32_jmptbl_16:
+ .word 0
+ .size _nds32_jmptbl_16, .-_nds32_jmptbl_16
diff --git libgcc/config/nds32/isr-library/jmptbl_vid17.S libgcc/config/nds32/isr-library/jmptbl_vid17.S
new file mode 100644
index 0000000..626b027
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid17.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.17, "a"
+ .align 2
+ .weak _nds32_jmptbl_17
+ .type _nds32_jmptbl_17, @object
+_nds32_jmptbl_17:
+ .word 0
+ .size _nds32_jmptbl_17, .-_nds32_jmptbl_17
diff --git libgcc/config/nds32/isr-library/jmptbl_vid18.S libgcc/config/nds32/isr-library/jmptbl_vid18.S
new file mode 100644
index 0000000..6a5bd1b
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid18.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.18, "a"
+ .align 2
+ .weak _nds32_jmptbl_18
+ .type _nds32_jmptbl_18, @object
+_nds32_jmptbl_18:
+ .word 0
+ .size _nds32_jmptbl_18, .-_nds32_jmptbl_18
diff --git libgcc/config/nds32/isr-library/jmptbl_vid19.S libgcc/config/nds32/isr-library/jmptbl_vid19.S
new file mode 100644
index 0000000..77e5176
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid19.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.19, "a"
+ .align 2
+ .weak _nds32_jmptbl_19
+ .type _nds32_jmptbl_19, @object
+_nds32_jmptbl_19:
+ .word 0
+ .size _nds32_jmptbl_19, .-_nds32_jmptbl_19
diff --git libgcc/config/nds32/isr-library/jmptbl_vid20.S libgcc/config/nds32/isr-library/jmptbl_vid20.S
new file mode 100644
index 0000000..268d9c9
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid20.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.20, "a"
+ .align 2
+ .weak _nds32_jmptbl_20
+ .type _nds32_jmptbl_20, @object
+_nds32_jmptbl_20:
+ .word 0
+ .size _nds32_jmptbl_20, .-_nds32_jmptbl_20
diff --git libgcc/config/nds32/isr-library/jmptbl_vid21.S libgcc/config/nds32/isr-library/jmptbl_vid21.S
new file mode 100644
index 0000000..ac3412f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid21.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.21, "a"
+ .align 2
+ .weak _nds32_jmptbl_21
+ .type _nds32_jmptbl_21, @object
+_nds32_jmptbl_21:
+ .word 0
+ .size _nds32_jmptbl_21, .-_nds32_jmptbl_21
diff --git libgcc/config/nds32/isr-library/jmptbl_vid22.S libgcc/config/nds32/isr-library/jmptbl_vid22.S
new file mode 100644
index 0000000..15bcd05
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid22.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.22, "a"
+ .align 2
+ .weak _nds32_jmptbl_22
+ .type _nds32_jmptbl_22, @object
+_nds32_jmptbl_22:
+ .word 0
+ .size _nds32_jmptbl_22, .-_nds32_jmptbl_22
diff --git libgcc/config/nds32/isr-library/jmptbl_vid23.S libgcc/config/nds32/isr-library/jmptbl_vid23.S
new file mode 100644
index 0000000..64c4f09
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid23.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.23, "a"
+ .align 2
+ .weak _nds32_jmptbl_23
+ .type _nds32_jmptbl_23, @object
+_nds32_jmptbl_23:
+ .word 0
+ .size _nds32_jmptbl_23, .-_nds32_jmptbl_23
diff --git libgcc/config/nds32/isr-library/jmptbl_vid24.S libgcc/config/nds32/isr-library/jmptbl_vid24.S
new file mode 100644
index 0000000..3304cea
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid24.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.24, "a"
+ .align 2
+ .weak _nds32_jmptbl_24
+ .type _nds32_jmptbl_24, @object
+_nds32_jmptbl_24:
+ .word 0
+ .size _nds32_jmptbl_24, .-_nds32_jmptbl_24
diff --git libgcc/config/nds32/isr-library/jmptbl_vid25.S libgcc/config/nds32/isr-library/jmptbl_vid25.S
new file mode 100644
index 0000000..813d906
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid25.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.25, "a"
+ .align 2
+ .weak _nds32_jmptbl_25
+ .type _nds32_jmptbl_25, @object
+_nds32_jmptbl_25:
+ .word 0
+ .size _nds32_jmptbl_25, .-_nds32_jmptbl_25
diff --git libgcc/config/nds32/isr-library/jmptbl_vid26.S libgcc/config/nds32/isr-library/jmptbl_vid26.S
new file mode 100644
index 0000000..d19f236
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid26.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.26, "a"
+ .align 2
+ .weak _nds32_jmptbl_26
+ .type _nds32_jmptbl_26, @object
+_nds32_jmptbl_26:
+ .word 0
+ .size _nds32_jmptbl_26, .-_nds32_jmptbl_26
diff --git libgcc/config/nds32/isr-library/jmptbl_vid27.S libgcc/config/nds32/isr-library/jmptbl_vid27.S
new file mode 100644
index 0000000..7ce8878
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid27.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.27, "a"
+ .align 2
+ .weak _nds32_jmptbl_27
+ .type _nds32_jmptbl_27, @object
+_nds32_jmptbl_27:
+ .word 0
+ .size _nds32_jmptbl_27, .-_nds32_jmptbl_27
diff --git libgcc/config/nds32/isr-library/jmptbl_vid28.S libgcc/config/nds32/isr-library/jmptbl_vid28.S
new file mode 100644
index 0000000..26f832c
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid28.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.28, "a"
+ .align 2
+ .weak _nds32_jmptbl_28
+ .type _nds32_jmptbl_28, @object
+_nds32_jmptbl_28:
+ .word 0
+ .size _nds32_jmptbl_28, .-_nds32_jmptbl_28
diff --git libgcc/config/nds32/isr-library/jmptbl_vid29.S libgcc/config/nds32/isr-library/jmptbl_vid29.S
new file mode 100644
index 0000000..e45d5ab
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid29.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.29, "a"
+ .align 2
+ .weak _nds32_jmptbl_29
+ .type _nds32_jmptbl_29, @object
+_nds32_jmptbl_29:
+ .word 0
+ .size _nds32_jmptbl_29, .-_nds32_jmptbl_29
diff --git libgcc/config/nds32/isr-library/jmptbl_vid30.S libgcc/config/nds32/isr-library/jmptbl_vid30.S
new file mode 100644
index 0000000..944a71f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid30.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.30, "a"
+ .align 2
+ .weak _nds32_jmptbl_30
+ .type _nds32_jmptbl_30, @object
+_nds32_jmptbl_30:
+ .word 0
+ .size _nds32_jmptbl_30, .-_nds32_jmptbl_30
diff --git libgcc/config/nds32/isr-library/jmptbl_vid31.S libgcc/config/nds32/isr-library/jmptbl_vid31.S
new file mode 100644
index 0000000..a3403de
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid31.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.31, "a"
+ .align 2
+ .weak _nds32_jmptbl_31
+ .type _nds32_jmptbl_31, @object
+_nds32_jmptbl_31:
+ .word 0
+ .size _nds32_jmptbl_31, .-_nds32_jmptbl_31
diff --git libgcc/config/nds32/isr-library/jmptbl_vid32.S libgcc/config/nds32/isr-library/jmptbl_vid32.S
new file mode 100644
index 0000000..22e230d
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid32.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.32, "a"
+ .align 2
+ .weak _nds32_jmptbl_32
+ .type _nds32_jmptbl_32, @object
+_nds32_jmptbl_32:
+ .word 0
+ .size _nds32_jmptbl_32, .-_nds32_jmptbl_32
diff --git libgcc/config/nds32/isr-library/jmptbl_vid33.S libgcc/config/nds32/isr-library/jmptbl_vid33.S
new file mode 100644
index 0000000..8cc7ea6
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid33.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.33, "a"
+ .align 2
+ .weak _nds32_jmptbl_33
+ .type _nds32_jmptbl_33, @object
+_nds32_jmptbl_33:
+ .word 0
+ .size _nds32_jmptbl_33, .-_nds32_jmptbl_33
diff --git libgcc/config/nds32/isr-library/jmptbl_vid34.S libgcc/config/nds32/isr-library/jmptbl_vid34.S
new file mode 100644
index 0000000..20ab733
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid34.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.34, "a"
+ .align 2
+ .weak _nds32_jmptbl_34
+ .type _nds32_jmptbl_34, @object
+_nds32_jmptbl_34:
+ .word 0
+ .size _nds32_jmptbl_34, .-_nds32_jmptbl_34
diff --git libgcc/config/nds32/isr-library/jmptbl_vid35.S libgcc/config/nds32/isr-library/jmptbl_vid35.S
new file mode 100644
index 0000000..3da488e
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid35.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.35, "a"
+ .align 2
+ .weak _nds32_jmptbl_35
+ .type _nds32_jmptbl_35, @object
+_nds32_jmptbl_35:
+ .word 0
+ .size _nds32_jmptbl_35, .-_nds32_jmptbl_35
diff --git libgcc/config/nds32/isr-library/jmptbl_vid36.S libgcc/config/nds32/isr-library/jmptbl_vid36.S
new file mode 100644
index 0000000..eee872f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid36.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.36, "a"
+ .align 2
+ .weak _nds32_jmptbl_36
+ .type _nds32_jmptbl_36, @object
+_nds32_jmptbl_36:
+ .word 0
+ .size _nds32_jmptbl_36, .-_nds32_jmptbl_36
diff --git libgcc/config/nds32/isr-library/jmptbl_vid37.S libgcc/config/nds32/isr-library/jmptbl_vid37.S
new file mode 100644
index 0000000..b7c7598
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid37.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.37, "a"
+ .align 2
+ .weak _nds32_jmptbl_37
+ .type _nds32_jmptbl_37, @object
+_nds32_jmptbl_37:
+ .word 0
+ .size _nds32_jmptbl_37, .-_nds32_jmptbl_37
diff --git libgcc/config/nds32/isr-library/jmptbl_vid38.S libgcc/config/nds32/isr-library/jmptbl_vid38.S
new file mode 100644
index 0000000..21d6fc3
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid38.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.38, "a"
+ .align 2
+ .weak _nds32_jmptbl_38
+ .type _nds32_jmptbl_38, @object
+_nds32_jmptbl_38:
+ .word 0
+ .size _nds32_jmptbl_38, .-_nds32_jmptbl_38
diff --git libgcc/config/nds32/isr-library/jmptbl_vid39.S libgcc/config/nds32/isr-library/jmptbl_vid39.S
new file mode 100644
index 0000000..85ad442
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid39.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.39, "a"
+ .align 2
+ .weak _nds32_jmptbl_39
+ .type _nds32_jmptbl_39, @object
+_nds32_jmptbl_39:
+ .word 0
+ .size _nds32_jmptbl_39, .-_nds32_jmptbl_39
diff --git libgcc/config/nds32/isr-library/jmptbl_vid40.S libgcc/config/nds32/isr-library/jmptbl_vid40.S
new file mode 100644
index 0000000..8023d9a
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid40.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.40, "a"
+ .align 2
+ .weak _nds32_jmptbl_40
+ .type _nds32_jmptbl_40, @object
+_nds32_jmptbl_40:
+ .word 0
+ .size _nds32_jmptbl_40, .-_nds32_jmptbl_40
diff --git libgcc/config/nds32/isr-library/jmptbl_vid41.S libgcc/config/nds32/isr-library/jmptbl_vid41.S
new file mode 100644
index 0000000..1efd2c6
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid41.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.41, "a"
+ .align 2
+ .weak _nds32_jmptbl_41
+ .type _nds32_jmptbl_41, @object
+_nds32_jmptbl_41:
+ .word 0
+ .size _nds32_jmptbl_41, .-_nds32_jmptbl_41
diff --git libgcc/config/nds32/isr-library/jmptbl_vid42.S libgcc/config/nds32/isr-library/jmptbl_vid42.S
new file mode 100644
index 0000000..55bb9d8
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid42.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.42, "a"
+ .align 2
+ .weak _nds32_jmptbl_42
+ .type _nds32_jmptbl_42, @object
+_nds32_jmptbl_42:
+ .word 0
+ .size _nds32_jmptbl_42, .-_nds32_jmptbl_42
diff --git libgcc/config/nds32/isr-library/jmptbl_vid43.S libgcc/config/nds32/isr-library/jmptbl_vid43.S
new file mode 100644
index 0000000..ed34ccc
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid43.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.43, "a"
+ .align 2
+ .weak _nds32_jmptbl_43
+ .type _nds32_jmptbl_43, @object
+_nds32_jmptbl_43:
+ .word 0
+ .size _nds32_jmptbl_43, .-_nds32_jmptbl_43
diff --git libgcc/config/nds32/isr-library/jmptbl_vid44.S libgcc/config/nds32/isr-library/jmptbl_vid44.S
new file mode 100644
index 0000000..7308f41
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid44.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.44, "a"
+ .align 2
+ .weak _nds32_jmptbl_44
+ .type _nds32_jmptbl_44, @object
+_nds32_jmptbl_44:
+ .word 0
+ .size _nds32_jmptbl_44, .-_nds32_jmptbl_44
diff --git libgcc/config/nds32/isr-library/jmptbl_vid45.S libgcc/config/nds32/isr-library/jmptbl_vid45.S
new file mode 100644
index 0000000..9ea67bd
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid45.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.45, "a"
+ .align 2
+ .weak _nds32_jmptbl_45
+ .type _nds32_jmptbl_45, @object
+_nds32_jmptbl_45:
+ .word 0
+ .size _nds32_jmptbl_45, .-_nds32_jmptbl_45
diff --git libgcc/config/nds32/isr-library/jmptbl_vid46.S libgcc/config/nds32/isr-library/jmptbl_vid46.S
new file mode 100644
index 0000000..98d14a0
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid46.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.46, "a"
+ .align 2
+ .weak _nds32_jmptbl_46
+ .type _nds32_jmptbl_46, @object
+_nds32_jmptbl_46:
+ .word 0
+ .size _nds32_jmptbl_46, .-_nds32_jmptbl_46
diff --git libgcc/config/nds32/isr-library/jmptbl_vid47.S libgcc/config/nds32/isr-library/jmptbl_vid47.S
new file mode 100644
index 0000000..3adfab9
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid47.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.47, "a"
+ .align 2
+ .weak _nds32_jmptbl_47
+ .type _nds32_jmptbl_47, @object
+_nds32_jmptbl_47:
+ .word 0
+ .size _nds32_jmptbl_47, .-_nds32_jmptbl_47
diff --git libgcc/config/nds32/isr-library/jmptbl_vid48.S libgcc/config/nds32/isr-library/jmptbl_vid48.S
new file mode 100644
index 0000000..3ceb6c2
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid48.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.48, "a"
+ .align 2
+ .weak _nds32_jmptbl_48
+ .type _nds32_jmptbl_48, @object
+_nds32_jmptbl_48:
+ .word 0
+ .size _nds32_jmptbl_48, .-_nds32_jmptbl_48
diff --git libgcc/config/nds32/isr-library/jmptbl_vid49.S libgcc/config/nds32/isr-library/jmptbl_vid49.S
new file mode 100644
index 0000000..b94b738
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid49.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.49, "a"
+ .align 2
+ .weak _nds32_jmptbl_49
+ .type _nds32_jmptbl_49, @object
+_nds32_jmptbl_49:
+ .word 0
+ .size _nds32_jmptbl_49, .-_nds32_jmptbl_49
diff --git libgcc/config/nds32/isr-library/jmptbl_vid50.S libgcc/config/nds32/isr-library/jmptbl_vid50.S
new file mode 100644
index 0000000..3cafb74
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid50.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.50, "a"
+ .align 2
+ .weak _nds32_jmptbl_50
+ .type _nds32_jmptbl_50, @object
+_nds32_jmptbl_50:
+ .word 0
+ .size _nds32_jmptbl_50, .-_nds32_jmptbl_50
diff --git libgcc/config/nds32/isr-library/jmptbl_vid51.S libgcc/config/nds32/isr-library/jmptbl_vid51.S
new file mode 100644
index 0000000..cf82177
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid51.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.51, "a"
+ .align 2
+ .weak _nds32_jmptbl_51
+ .type _nds32_jmptbl_51, @object
+_nds32_jmptbl_51:
+ .word 0
+ .size _nds32_jmptbl_51, .-_nds32_jmptbl_51
diff --git libgcc/config/nds32/isr-library/jmptbl_vid52.S libgcc/config/nds32/isr-library/jmptbl_vid52.S
new file mode 100644
index 0000000..3295d75
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid52.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.52, "a"
+ .align 2
+ .weak _nds32_jmptbl_52
+ .type _nds32_jmptbl_52, @object
+_nds32_jmptbl_52:
+ .word 0
+ .size _nds32_jmptbl_52, .-_nds32_jmptbl_52
diff --git libgcc/config/nds32/isr-library/jmptbl_vid53.S libgcc/config/nds32/isr-library/jmptbl_vid53.S
new file mode 100644
index 0000000..5ab384f
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid53.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.53, "a"
+ .align 2
+ .weak _nds32_jmptbl_53
+ .type _nds32_jmptbl_53, @object
+_nds32_jmptbl_53:
+ .word 0
+ .size _nds32_jmptbl_53, .-_nds32_jmptbl_53
diff --git libgcc/config/nds32/isr-library/jmptbl_vid54.S libgcc/config/nds32/isr-library/jmptbl_vid54.S
new file mode 100644
index 0000000..ebbc224
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid54.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.54, "a"
+ .align 2
+ .weak _nds32_jmptbl_54
+ .type _nds32_jmptbl_54, @object
+_nds32_jmptbl_54:
+ .word 0
+ .size _nds32_jmptbl_54, .-_nds32_jmptbl_54
diff --git libgcc/config/nds32/isr-library/jmptbl_vid55.S libgcc/config/nds32/isr-library/jmptbl_vid55.S
new file mode 100644
index 0000000..d965bba
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid55.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.55, "a"
+ .align 2
+ .weak _nds32_jmptbl_55
+ .type _nds32_jmptbl_55, @object
+_nds32_jmptbl_55:
+ .word 0
+ .size _nds32_jmptbl_55, .-_nds32_jmptbl_55
diff --git libgcc/config/nds32/isr-library/jmptbl_vid56.S libgcc/config/nds32/isr-library/jmptbl_vid56.S
new file mode 100644
index 0000000..189ea31
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid56.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.56, "a"
+ .align 2
+ .weak _nds32_jmptbl_56
+ .type _nds32_jmptbl_56, @object
+_nds32_jmptbl_56:
+ .word 0
+ .size _nds32_jmptbl_56, .-_nds32_jmptbl_56
diff --git libgcc/config/nds32/isr-library/jmptbl_vid57.S libgcc/config/nds32/isr-library/jmptbl_vid57.S
new file mode 100644
index 0000000..04f3fae
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid57.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.57, "a"
+ .align 2
+ .weak _nds32_jmptbl_57
+ .type _nds32_jmptbl_57, @object
+_nds32_jmptbl_57:
+ .word 0
+ .size _nds32_jmptbl_57, .-_nds32_jmptbl_57
diff --git libgcc/config/nds32/isr-library/jmptbl_vid58.S libgcc/config/nds32/isr-library/jmptbl_vid58.S
new file mode 100644
index 0000000..d824588
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid58.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.58, "a"
+ .align 2
+ .weak _nds32_jmptbl_58
+ .type _nds32_jmptbl_58, @object
+_nds32_jmptbl_58:
+ .word 0
+ .size _nds32_jmptbl_58, .-_nds32_jmptbl_58
diff --git libgcc/config/nds32/isr-library/jmptbl_vid59.S libgcc/config/nds32/isr-library/jmptbl_vid59.S
new file mode 100644
index 0000000..ae867ee
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid59.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.59, "a"
+ .align 2
+ .weak _nds32_jmptbl_59
+ .type _nds32_jmptbl_59, @object
+_nds32_jmptbl_59:
+ .word 0
+ .size _nds32_jmptbl_59, .-_nds32_jmptbl_59
diff --git libgcc/config/nds32/isr-library/jmptbl_vid60.S libgcc/config/nds32/isr-library/jmptbl_vid60.S
new file mode 100644
index 0000000..3d6abc3
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid60.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.60, "a"
+ .align 2
+ .weak _nds32_jmptbl_60
+ .type _nds32_jmptbl_60, @object
+_nds32_jmptbl_60:
+ .word 0
+ .size _nds32_jmptbl_60, .-_nds32_jmptbl_60
diff --git libgcc/config/nds32/isr-library/jmptbl_vid61.S libgcc/config/nds32/isr-library/jmptbl_vid61.S
new file mode 100644
index 0000000..04af492
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid61.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.61, "a"
+ .align 2
+ .weak _nds32_jmptbl_61
+ .type _nds32_jmptbl_61, @object
+_nds32_jmptbl_61:
+ .word 0
+ .size _nds32_jmptbl_61, .-_nds32_jmptbl_61
diff --git libgcc/config/nds32/isr-library/jmptbl_vid62.S libgcc/config/nds32/isr-library/jmptbl_vid62.S
new file mode 100644
index 0000000..b3115ce
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid62.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.62, "a"
+ .align 2
+ .weak _nds32_jmptbl_62
+ .type _nds32_jmptbl_62, @object
+_nds32_jmptbl_62:
+ .word 0
+ .size _nds32_jmptbl_62, .-_nds32_jmptbl_62
diff --git libgcc/config/nds32/isr-library/jmptbl_vid63.S libgcc/config/nds32/isr-library/jmptbl_vid63.S
new file mode 100644
index 0000000..cfe22fb
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid63.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.63, "a"
+ .align 2
+ .weak _nds32_jmptbl_63
+ .type _nds32_jmptbl_63, @object
+_nds32_jmptbl_63:
+ .word 0
+ .size _nds32_jmptbl_63, .-_nds32_jmptbl_63
diff --git libgcc/config/nds32/isr-library/jmptbl_vid64.S libgcc/config/nds32/isr-library/jmptbl_vid64.S
new file mode 100644
index 0000000..51f1a22
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid64.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.64, "a"
+ .align 2
+ .weak _nds32_jmptbl_64
+ .type _nds32_jmptbl_64, @object
+_nds32_jmptbl_64:
+ .word 0
+ .size _nds32_jmptbl_64, .-_nds32_jmptbl_64
diff --git libgcc/config/nds32/isr-library/jmptbl_vid65.S libgcc/config/nds32/isr-library/jmptbl_vid65.S
new file mode 100644
index 0000000..caec841
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid65.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.65, "a"
+ .align 2
+ .weak _nds32_jmptbl_65
+ .type _nds32_jmptbl_65, @object
+_nds32_jmptbl_65:
+ .word 0
+ .size _nds32_jmptbl_65, .-_nds32_jmptbl_65
diff --git libgcc/config/nds32/isr-library/jmptbl_vid66.S libgcc/config/nds32/isr-library/jmptbl_vid66.S
new file mode 100644
index 0000000..acdb37b
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid66.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.66, "a"
+ .align 2
+ .weak _nds32_jmptbl_66
+ .type _nds32_jmptbl_66, @object
+_nds32_jmptbl_66:
+ .word 0
+ .size _nds32_jmptbl_66, .-_nds32_jmptbl_66
diff --git libgcc/config/nds32/isr-library/jmptbl_vid67.S libgcc/config/nds32/isr-library/jmptbl_vid67.S
new file mode 100644
index 0000000..ea29410
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid67.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.67, "a"
+ .align 2
+ .weak _nds32_jmptbl_67
+ .type _nds32_jmptbl_67, @object
+_nds32_jmptbl_67:
+ .word 0
+ .size _nds32_jmptbl_67, .-_nds32_jmptbl_67
diff --git libgcc/config/nds32/isr-library/jmptbl_vid68.S libgcc/config/nds32/isr-library/jmptbl_vid68.S
new file mode 100644
index 0000000..2be477b
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid68.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.68, "a"
+ .align 2
+ .weak _nds32_jmptbl_68
+ .type _nds32_jmptbl_68, @object
+_nds32_jmptbl_68:
+ .word 0
+ .size _nds32_jmptbl_68, .-_nds32_jmptbl_68
diff --git libgcc/config/nds32/isr-library/jmptbl_vid69.S libgcc/config/nds32/isr-library/jmptbl_vid69.S
new file mode 100644
index 0000000..8ada9ce
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid69.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.69, "a"
+ .align 2
+ .weak _nds32_jmptbl_69
+ .type _nds32_jmptbl_69, @object
+_nds32_jmptbl_69:
+ .word 0
+ .size _nds32_jmptbl_69, .-_nds32_jmptbl_69
diff --git libgcc/config/nds32/isr-library/jmptbl_vid70.S libgcc/config/nds32/isr-library/jmptbl_vid70.S
new file mode 100644
index 0000000..ee9b494
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid70.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.70, "a"
+ .align 2
+ .weak _nds32_jmptbl_70
+ .type _nds32_jmptbl_70, @object
+_nds32_jmptbl_70:
+ .word 0
+ .size _nds32_jmptbl_70, .-_nds32_jmptbl_70
diff --git libgcc/config/nds32/isr-library/jmptbl_vid71.S libgcc/config/nds32/isr-library/jmptbl_vid71.S
new file mode 100644
index 0000000..c83d53e
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid71.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.71, "a"
+ .align 2
+ .weak _nds32_jmptbl_71
+ .type _nds32_jmptbl_71, @object
+_nds32_jmptbl_71:
+ .word 0
+ .size _nds32_jmptbl_71, .-_nds32_jmptbl_71
diff --git libgcc/config/nds32/isr-library/jmptbl_vid72.S libgcc/config/nds32/isr-library/jmptbl_vid72.S
new file mode 100644
index 0000000..ea4a199
--- /dev/null
+++ libgcc/config/nds32/isr-library/jmptbl_vid72.S
@@ -0,0 +1,7 @@
+ .section .nds32_jmptbl.72, "a"
+ .align 2
+ .weak _nds32_jmptbl_72
+ .type _nds32_jmptbl_72, @object
+_nds32_jmptbl_72:
+ .word 0
+ .size _nds32_jmptbl_72, .-_nds32_jmptbl_72
diff --git libgcc/config/nds32/isr-library/nmih.S libgcc/config/nds32/isr-library/nmih.S
new file mode 100644
index 0000000..1d6a68a
--- /dev/null
+++ libgcc/config/nds32/isr-library/nmih.S
@@ -0,0 +1,7 @@
+ .section .nds32_nmih, "a"
+ .align 2
+ .weak _nds32_nmih
+ .type _nds32_nmih, @object
+_nds32_nmih:
+ .word 0
+ .size _nds32_nmih, .-_nds32_nmih
diff --git libgcc/config/nds32/isr-library/reset.S libgcc/config/nds32/isr-library/reset.S
new file mode 100644
index 0000000..4350e64
--- /dev/null
+++ libgcc/config/nds32/isr-library/reset.S
@@ -0,0 +1,105 @@
+ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
+ .align 1
+ .weak _SDA_BASE_ /* For reset handler only. */
+ .weak _FP_BASE_ /* For reset handler only. */
+ .weak _nds32_init_mem /* User defined memory initialization function. */
+ .globl _start
+ .globl _nds32_reset
+ .type _nds32_reset, @function
+_nds32_reset:
+_start:
+#ifdef NDS32_EXT_EX9
+ .no_ex9_begin
+#endif
+ /* Handle NMI and warm boot if any of them exists. */
+ beqz $sp, 1f /* Reset, NMI or warm boot? */
+ /* Either NMI or warm boot; save all regs. */
+
+ /* Preserve registers for context-switching. */
+#ifdef __NDS32_REDUCED_REGS__
+ /* For 16-reg mode. */
+ smw.adm $r0, [$sp], $r10, #0x0
+ smw.adm $r15, [$sp], $r15, #0xf
+#else
+ /* For 32-reg mode. */
+ smw.adm $r0, [$sp], $r27, #0xf
+#endif
+#ifdef NDS32_EXT_IFC
+ mfusr $r1, $IFC_LP
+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
+ stack 8-byte alignment. */
+#endif
+
+ la $gp, _SDA_BASE_ /* Init GP for small data access. */
+ move $r0, $sp /* Init parameter. */
+ mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */
+ andi $r1, $r1, #0xf
+ addi $r1, $r1, #-1
+ beqz $r1, 2f /* Warm boot if true. */
+ l.w $r15, _nds32_nmih /* Load NMI handler. */
+ j 3f
+2:
+ l.w $r15, _nds32_wrh /* Load warm boot handler. */
+3:
+ beqz $r15, 1f /* If no handler, do cold boot. */
+ jral $r15 /* Call handler. */
+ bnez $r0, 1f /* If fail to resume, do cold boot. */
+
+ /* Restore registers for context-switching. */
+#ifdef NDS32_EXT_IFC
+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
+ stack 8-byte alignment. */
+ mtusr $r1, $IFC_LP
+#endif
+#ifdef __NDS32_REDUCED_REGS__
+ /* For 16-reg mode. */
+ lmw.bim $r15, [$sp], $r15, #0xf
+ lmw.bim $r0, [$sp], $r10, #0x0
+#else
+ /* For 32-reg mode. */
+ lmw.bim $r0, [$sp], $r27, #0xf
+#endif
+ iret /* Resume operation. */
+
+
+1: /* Cold boot. */
+ /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */
+ mfsr $r0, $IVB
+ li $r1, #0xffff3fff
+ and $r0, $r0, $r1
+ ori $r0, $r0, #0x4000
+ mtsr $r0, $IVB
+ dsb
+
+ la $gp, _SDA_BASE_ /* Init $gp. */
+ la $fp, _FP_BASE_ /* Init $fp. */
+ la $sp, _stack /* Init $sp. */
+#ifdef NDS32_EXT_EX9
+/*
+ * Initialize the table base of EX9 instruction
+ * ex9 generation needs to disable before the ITB is set
+ */
+ mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
+ srli $r0, $r0, 24
+ andi $r0, $r0, 0x1
+ beqz $r0, 4f /* Zero means HW does not support EX9. */
+ la $r0, _ITB_BASE_ /* Init $ITB. */
+ mtusr $r0, $ITB
+ .no_ex9_end
+4:
+#endif
+ la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
+ may written by C language. */
+ beqz $r15, 6f
+ jral $r15
+6:
+ l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
+ jral $r15
+/* Reset handler() should never return in a RTOS or non-OS system.
+ In case it does return, an exception will be generated.
+ This exception will be caught either by default break handler or by EDM.
+ Default break handle may just do an infinite loop.
+ EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
+5:
+ break #0x7fff
+ .size _nds32_reset, .-_nds32_reset
diff --git libgcc/config/nds32/isr-library/reset_4b.S libgcc/config/nds32/isr-library/reset_4b.S
new file mode 100644
index 0000000..c857d9c
--- /dev/null
+++ libgcc/config/nds32/isr-library/reset_4b.S
@@ -0,0 +1,106 @@
+ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
+ .align 1
+ .weak _SDA_BASE_ /* For reset handler only. */
+ .weak _FP_BASE_ /* For reset handler only. */
+ .weak _nds32_init_mem /* User defined memory initialization function. */
+ .globl _start
+ .globl _nds32_reset_4b
+ .type _nds32_reset_4b, @function
+_nds32_reset_4b:
+_start:
+#ifdef NDS32_EXT_EX9
+ .no_ex9_begin
+#endif
+ /* Handle NMI and warm boot if any of them exists. */
+ beqz $sp, 1f /* Reset, NMI or warm boot? */
+ /* Either NMI or warm boot; save all regs. */
+
+ /* Preserve registers for context-switching. */
+#ifdef __NDS32_REDUCED_REGS__
+ /* For 16-reg mode. */
+ smw.adm $r0, [$sp], $r10, #0x0
+ smw.adm $r15, [$sp], $r15, #0xf
+#else
+ /* For 32-reg mode. */
+ smw.adm $r0, [$sp], $r27, #0xf
+#endif
+#ifdef NDS32_EXT_IFC
+ mfusr $r1, $IFC_LP
+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
+ stack 8-byte alignment. */
+#endif
+
+ la $gp, _SDA_BASE_ /* Init GP for small data access. */
+ move $r0, $sp /* Init parameter. */
+ mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */
+ andi $r1, $r1, #0xf
+ addi $r1, $r1, #-1
+ beqz $r1, 2f /* Warm boot if true. */
+ l.w $r15, _nds32_nmih /* Load NMI handler. */
+ j 3f
+2:
+ l.w $r15, _nds32_wrh /* Load warm boot handler. */
+3:
+ beqz $r15, 1f /* If no handler, do cold boot. */
+ jral $r15 /* Call handler. */
+ bnez $r0, 1f /* If fail to resume, do cold boot. */
+
+ /* Restore registers for context-switching. */
+#ifdef NDS32_EXT_IFC
+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
+ stack 8-byte alignment. */
+ mtusr $r1, $IFC_LP
+#endif
+#ifdef __NDS32_REDUCED_REGS__
+ /* For 16-reg mode. */
+ lmw.bim $r15, [$sp], $r15, #0xf
+ lmw.bim $r0, [$sp], $r10, #0x0
+#else
+ /* For 32-reg mode. */
+ lmw.bim $r0, [$sp], $r27, #0xf
+#endif
+ iret /* Resume operation. */
+
+
+1: /* Cold boot. */
+ /* With vector ID feature, set default vector size to 4B. */
+ /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */
+ mfsr $r0, $IVB
+ li $r1, #0xc000
+ or $r0, $r0, $r1
+ xor $r0, $r0, $r1
+ mtsr $r0, $IVB
+ dsb
+
+ la $gp, _SDA_BASE_ /* Init $gp. */
+ la $fp, _FP_BASE_ /* Init $fp. */
+ la $sp, _stack /* Init $sp. */
+#ifdef NDS32_EXT_EX9
+/*
+ * Initialize the table base of EX9 instruction
+ * ex9 generation needs to disable before the ITB is set
+ */
+ mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */
+ srli $r0, $r0, 24
+ andi $r0, $r0, 0x1
+ beqz $r0, 4f /* Zero means HW does not support EX9. */
+ la $r0, _ITB_BASE_ /* Init $ITB. */
+ mtusr $r0, $ITB
+ .no_ex9_end
+4:
+#endif
+ la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem
+ may written by C language. */
+ beqz $r15, 6f
+ jral $r15
+6:
+ l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */
+ jral $r15
+/* Reset handler() should never return in a RTOS or non-OS system.
+ In case it does return, an exception will be generated.
+ This exception will be caught either by default break handler or by EDM.
+ Default break handle may just do an infinite loop.
+ EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */
+5:
+ break #0x7fff
+ .size _nds32_reset_4b, .-_nds32_reset_4b
diff --git libgcc/config/nds32/isr-library/restore_all.inc libgcc/config/nds32/isr-library/restore_all.inc
new file mode 100644
index 0000000..6b1635e
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_all.inc
@@ -0,0 +1,20 @@
+.macro RESTORE_ALL
+ setgie.d
+ dsb
+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore IPC, IPSW. */
+ mtsr $r1, $IPC
+ mtsr $r2, $IPSW
+ RESTORE_FPU_REGS
+ RESTORE_MAC_REGS
+#ifdef NDS32_EXT_IFC
+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
+ stack 8-byte alignment. */
+ mtusr $r1, $IFC_LP
+#endif
+#ifdef __NDS32_REDUCED_REGS__
+ lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */
+ lmw.bim $r15, [$sp], $r15, #0xf
+#else /* not __NDS32_REDUCED_REGS__ */
+ lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/restore_fpu_regs.inc libgcc/config/nds32/isr-library/restore_fpu_regs.inc
new file mode 100644
index 0000000..ec220e0
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_fpu_regs.inc
@@ -0,0 +1,11 @@
+.macro RESTORE_FPU_REGS
+#if defined(NDS32_EXT_FPU_CONFIG_0)
+ RESTORE_FPU_REGS_00
+#elif defined(NDS32_EXT_FPU_CONFIG_1)
+ RESTORE_FPU_REGS_01
+#elif defined(NDS32_EXT_FPU_CONFIG_2)
+ RESTORE_FPU_REGS_02
+#elif defined(NDS32_EXT_FPU_CONFIG_3)
+ RESTORE_FPU_REGS_03
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc
new file mode 100644
index 0000000..b1d0946
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc
@@ -0,0 +1,6 @@
+.macro RESTORE_FPU_REGS_00
+ fldi.bi $fd0, [$sp], #8
+ fldi.bi $fd1, [$sp], #8
+ fldi.bi $fd2, [$sp], #8
+ fldi.bi $fd3, [$sp], #8
+.endm
diff --git libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc
new file mode 100644
index 0000000..f72e19a
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc
@@ -0,0 +1,10 @@
+.macro RESTORE_FPU_REGS_01
+ fldi.bi $fd0, [$sp], #8
+ fldi.bi $fd1, [$sp], #8
+ fldi.bi $fd2, [$sp], #8
+ fldi.bi $fd3, [$sp], #8
+ fldi.bi $fd4, [$sp], #8
+ fldi.bi $fd5, [$sp], #8
+ fldi.bi $fd6, [$sp], #8
+ fldi.bi $fd7, [$sp], #8
+.endm
diff --git libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc
new file mode 100644
index 0000000..b6e74f9
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc
@@ -0,0 +1,18 @@
+.macro RESTORE_FPU_REGS_02
+ fldi.bi $fd0, [$sp], 8
+ fldi.bi $fd1, [$sp], 8
+ fldi.bi $fd2, [$sp], 8
+ fldi.bi $fd3, [$sp], 8
+ fldi.bi $fd4, [$sp], 8
+ fldi.bi $fd5, [$sp], 8
+ fldi.bi $fd6, [$sp], 8
+ fldi.bi $fd7, [$sp], 8
+ fldi.bi $fd8, [$sp], 8
+ fldi.bi $fd9, [$sp], 8
+ fldi.bi $fd10, [$sp], 8
+ fldi.bi $fd11, [$sp], 8
+ fldi.bi $fd12, [$sp], 8
+ fldi.bi $fd13, [$sp], 8
+ fldi.bi $fd14, [$sp], 8
+ fldi.bi $fd15, [$sp], 8
+.endm
diff --git libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc
new file mode 100644
index 0000000..ca4bd58
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc
@@ -0,0 +1,34 @@
+.macro RESTORE_FPU_REGS_03
+ fldi.bi $fd0, [$sp], #8
+ fldi.bi $fd1, [$sp], #8
+ fldi.bi $fd2, [$sp], #8
+ fldi.bi $fd3, [$sp], #8
+ fldi.bi $fd4, [$sp], #8
+ fldi.bi $fd5, [$sp], #8
+ fldi.bi $fd6, [$sp], #8
+ fldi.bi $fd7, [$sp], #8
+ fldi.bi $fd8, [$sp], #8
+ fldi.bi $fd9, [$sp], #8
+ fldi.bi $fd10, [$sp], #8
+ fldi.bi $fd11, [$sp], #8
+ fldi.bi $fd12, [$sp], #8
+ fldi.bi $fd13, [$sp], #8
+ fldi.bi $fd14, [$sp], #8
+ fldi.bi $fd15, [$sp], #8
+ fldi.bi $fd16, [$sp], #8
+ fldi.bi $fd17, [$sp], #8
+ fldi.bi $fd18, [$sp], #8
+ fldi.bi $fd19, [$sp], #8
+ fldi.bi $fd20, [$sp], #8
+ fldi.bi $fd21, [$sp], #8
+ fldi.bi $fd22, [$sp], #8
+ fldi.bi $fd23, [$sp], #8
+ fldi.bi $fd24, [$sp], #8
+ fldi.bi $fd25, [$sp], #8
+ fldi.bi $fd26, [$sp], #8
+ fldi.bi $fd27, [$sp], #8
+ fldi.bi $fd28, [$sp], #8
+ fldi.bi $fd29, [$sp], #8
+ fldi.bi $fd30, [$sp], #8
+ fldi.bi $fd31, [$sp], #8
+.endm
diff --git libgcc/config/nds32/isr-library/restore_mac_regs.inc libgcc/config/nds32/isr-library/restore_mac_regs.inc
new file mode 100644
index 0000000..2cbda59
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_mac_regs.inc
@@ -0,0 +1,9 @@
+.macro RESTORE_MAC_REGS
+#ifdef NDS32_DX_REGS
+ lmw.bim $r1, [$sp], $r4, #0x0
+ mtusr $r1, $d0.lo
+ mtusr $r2, $d0.hi
+ mtusr $r3, $d1.lo
+ mtusr $r4, $d1.hi
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/restore_partial.inc libgcc/config/nds32/isr-library/restore_partial.inc
new file mode 100644
index 0000000..4433aca
--- /dev/null
+++ libgcc/config/nds32/isr-library/restore_partial.inc
@@ -0,0 +1,22 @@
+.macro RESTORE_PARTIAL
+#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
+ setgie.d
+ dsb
+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore IPC, IPSW. */
+ mtsr $r1, $IPC /* Set IPC. */
+ mtsr $r2, $IPSW /* Set IPSW. */
+#endif
+ RESTORE_FPU_REGS
+ RESTORE_MAC_REGS
+#ifdef NDS32_EXT_IFC
+ lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep
+ stack 8-byte alignment. */
+ mtusr $r1, $IFC_LP
+#endif
+ lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */
+#ifdef __NDS32_REDUCED_REGS__
+ lmw.bim $r15, [$sp], $r15, #0x2
+#else
+ lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/save_all.inc libgcc/config/nds32/isr-library/save_all.inc
new file mode 100644
index 0000000..06d1670
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_all.inc
@@ -0,0 +1,38 @@
+.macro SAVE_ALL_4B
+#ifdef __NDS32_REDUCED_REGS__
+ smw.adm $r15, [$sp], $r15, #0xf
+ smw.adm $r0, [$sp], $r10, #0x0
+#else /* not __NDS32_REDUCED_REGS__ */
+ smw.adm $r0, [$sp], $r27, #0xf
+#endif /* not __NDS32_REDUCED_REGS__ */
+#ifdef NDS32_EXT_IFC
+ mfusr $r1, $IFC_LP
+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
+ stack 8-byte alignment. */
+#endif
+ SAVE_MAC_REGS
+ SAVE_FPU_REGS
+ mfsr $r1, $IPC /* Get IPC. */
+ mfsr $r2, $IPSW /* Get IPSW. */
+ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
+ move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
+ mfsr $r0, $ITYPE /* Get VID to $r0. */
+ srli $r0, $r0, #5
+ fexti33 $r0, #6
+.endm
+
+.macro SAVE_ALL
+/* SAVE_REG_TBL code has been moved to
+ vector table generated by compiler. */
+#ifdef NDS32_EXT_IFC
+ mfusr $r1, $IFC_LP
+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
+ stack 8-byte alignment. */
+#endif
+ SAVE_MAC_REGS
+ SAVE_FPU_REGS
+ mfsr $r1, $IPC /* Get IPC. */
+ mfsr $r2, $IPSW /* Get IPSW. */
+ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
+ move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */
+.endm
diff --git libgcc/config/nds32/isr-library/save_fpu_regs.inc libgcc/config/nds32/isr-library/save_fpu_regs.inc
new file mode 100644
index 0000000..71e6bb4
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_fpu_regs.inc
@@ -0,0 +1,11 @@
+.macro SAVE_FPU_REGS
+#if defined(NDS32_EXT_FPU_CONFIG_0)
+ SAVE_FPU_REGS_00
+#elif defined(NDS32_EXT_FPU_CONFIG_1)
+ SAVE_FPU_REGS_01
+#elif defined(NDS32_EXT_FPU_CONFIG_2)
+ SAVE_FPU_REGS_02
+#elif defined(NDS32_EXT_FPU_CONFIG_3)
+ SAVE_FPU_REGS_03
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/save_fpu_regs_00.inc libgcc/config/nds32/isr-library/save_fpu_regs_00.inc
new file mode 100644
index 0000000..56a4974
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_fpu_regs_00.inc
@@ -0,0 +1,8 @@
+.macro SAVE_FPU_REGS_00
+ addi $sp, $sp, #-8
+ fsdi.bi $fd3, [$sp], #-8
+ fsdi.bi $fd2, [$sp], #-8
+ fsdi.bi $fd1, [$sp], #-8
+ fsdi.bi $fd0, [$sp], #-8
+ addi $sp, $sp, #8
+.endm
diff --git libgcc/config/nds32/isr-library/save_fpu_regs_01.inc libgcc/config/nds32/isr-library/save_fpu_regs_01.inc
new file mode 100644
index 0000000..14db951
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_fpu_regs_01.inc
@@ -0,0 +1,12 @@
+.macro SAVE_FPU_REGS_01
+ addi $sp, $sp, #-8
+ fsdi.bi $fd7, [$sp], #-8
+ fsdi.bi $fd6, [$sp], #-8
+ fsdi.bi $fd5, [$sp], #-8
+ fsdi.bi $fd4, [$sp], #-8
+ fsdi.bi $fd3, [$sp], #-8
+ fsdi.bi $fd2, [$sp], #-8
+ fsdi.bi $fd1, [$sp], #-8
+ fsdi.bi $fd0, [$sp], #-8
+ addi $sp, $sp, #8
+.endm
diff --git libgcc/config/nds32/isr-library/save_fpu_regs_02.inc libgcc/config/nds32/isr-library/save_fpu_regs_02.inc
new file mode 100644
index 0000000..7fdd00e
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_fpu_regs_02.inc
@@ -0,0 +1,20 @@
+.macro SAVE_FPU_REGS_02
+ addi $sp, $sp, #-8
+ fsdi.bi $fd15, [$sp], #-8
+ fsdi.bi $fd14, [$sp], #-8
+ fsdi.bi $fd13, [$sp], #-8
+ fsdi.bi $fd12, [$sp], #-8
+ fsdi.bi $fd11, [$sp], #-8
+ fsdi.bi $fd10, [$sp], #-8
+ fsdi.bi $fd9, [$sp], #-8
+ fsdi.bi $fd8, [$sp], #-8
+ fsdi.bi $fd7, [$sp], #-8
+ fsdi.bi $fd6, [$sp], #-8
+ fsdi.bi $fd5, [$sp], #-8
+ fsdi.bi $fd4, [$sp], #-8
+ fsdi.bi $fd3, [$sp], #-8
+ fsdi.bi $fd2, [$sp], #-8
+ fsdi.bi $fd1, [$sp], #-8
+ fsdi.bi $fd0, [$sp], #-8
+ addi $sp, $sp, #8
+.endm
diff --git libgcc/config/nds32/isr-library/save_fpu_regs_03.inc libgcc/config/nds32/isr-library/save_fpu_regs_03.inc
new file mode 100644
index 0000000..a2356a3
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_fpu_regs_03.inc
@@ -0,0 +1,36 @@
+.macro SAVE_FPU_REGS_03
+ addi $sp, $sp, #-8
+ fsdi.bi $fd31, [$sp], #-8
+ fsdi.bi $fd30, [$sp], #-8
+ fsdi.bi $fd29, [$sp], #-8
+ fsdi.bi $fd28, [$sp], #-8
+ fsdi.bi $fd27, [$sp], #-8
+ fsdi.bi $fd26, [$sp], #-8
+ fsdi.bi $fd25, [$sp], #-8
+ fsdi.bi $fd24, [$sp], #-8
+ fsdi.bi $fd23, [$sp], #-8
+ fsdi.bi $fd22, [$sp], #-8
+ fsdi.bi $fd21, [$sp], #-8
+ fsdi.bi $fd20, [$sp], #-8
+ fsdi.bi $fd19, [$sp], #-8
+ fsdi.bi $fd18, [$sp], #-8
+ fsdi.bi $fd17, [$sp], #-8
+ fsdi.bi $fd16, [$sp], #-8
+ fsdi.bi $fd15, [$sp], #-8
+ fsdi.bi $fd14, [$sp], #-8
+ fsdi.bi $fd13, [$sp], #-8
+ fsdi.bi $fd12, [$sp], #-8
+ fsdi.bi $fd11, [$sp], #-8
+ fsdi.bi $fd10, [$sp], #-8
+ fsdi.bi $fd9, [$sp], #-8
+ fsdi.bi $fd8, [$sp], #-8
+ fsdi.bi $fd7, [$sp], #-8
+ fsdi.bi $fd6, [$sp], #-8
+ fsdi.bi $fd5, [$sp], #-8
+ fsdi.bi $fd4, [$sp], #-8
+ fsdi.bi $fd3, [$sp], #-8
+ fsdi.bi $fd2, [$sp], #-8
+ fsdi.bi $fd1, [$sp], #-8
+ fsdi.bi $fd0, [$sp], #-8
+ addi $sp, $sp, #8
+.endm
diff --git libgcc/config/nds32/isr-library/save_mac_regs.inc libgcc/config/nds32/isr-library/save_mac_regs.inc
new file mode 100644
index 0000000..f435fac
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_mac_regs.inc
@@ -0,0 +1,9 @@
+.macro SAVE_MAC_REGS
+#ifdef NDS32_DX_REGS
+ mfusr $r1, $d0.lo
+ mfusr $r2, $d0.hi
+ mfusr $r3, $d1.lo
+ mfusr $r4, $d1.hi
+ smw.adm $r1, [$sp], $r4, #0x0
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/save_partial.inc libgcc/config/nds32/isr-library/save_partial.inc
new file mode 100644
index 0000000..9ab8a80
--- /dev/null
+++ libgcc/config/nds32/isr-library/save_partial.inc
@@ -0,0 +1,40 @@
+.macro SAVE_PARTIAL_4B
+#ifdef __NDS32_REDUCED_REGS__
+ smw.adm $r15, [$sp], $r15, #0x2
+#else /* not __NDS32_REDUCED_REGS__ */
+ smw.adm $r15, [$sp], $r27, #0x2
+#endif /* not __NDS32_REDUCED_REGS__ */
+ smw.adm $r0, [$sp], $r5, #0x0
+#ifdef NDS32_EXT_IFC
+ mfusr $r1, $IFC_LP
+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
+ stack 8-byte alignment. */
+#endif
+ SAVE_MAC_REGS
+ SAVE_FPU_REGS
+#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
+ mfsr $r1, $IPC /* Get IPC. */
+ mfsr $r2, $IPSW /* Get IPSW. */
+ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
+#endif
+ mfsr $r0, $ITYPE /* Get VID to $r0. */
+ srli $r0, $r0, #5
+ fexti33 $r0, #6
+.endm
+
+.macro SAVE_PARTIAL
+/* SAVE_CALLER_REGS code has been moved to
+ vector table generated by compiler. */
+#ifdef NDS32_EXT_IFC
+ mfusr $r1, $IFC_LP
+ smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep
+ stack 8-byte alignment. */
+#endif
+ SAVE_MAC_REGS
+ SAVE_FPU_REGS
+#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
+ mfsr $r1, $IPC /* Get IPC. */
+ mfsr $r2, $IPSW /* Get IPSW. */
+ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */
+#endif
+.endm
diff --git libgcc/config/nds32/isr-library/vec_vid00.S libgcc/config/nds32/isr-library/vec_vid00.S
new file mode 100644
index 0000000..49861eb
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid00.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.00, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_00
+ .type _nds32_vector_00, @function
+_nds32_vector_00:
+1:
+ j 1b
+ .size _nds32_vector_00, .-_nds32_vector_00
diff --git libgcc/config/nds32/isr-library/vec_vid00_4b.S libgcc/config/nds32/isr-library/vec_vid00_4b.S
new file mode 100644
index 0000000..1e12cf3
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid00_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.00, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_00_4b
+ .type _nds32_vector_00_4b, @function
+_nds32_vector_00_4b:
+1:
+ j 1b
+ .size _nds32_vector_00_4b, .-_nds32_vector_00_4b
diff --git libgcc/config/nds32/isr-library/vec_vid01.S libgcc/config/nds32/isr-library/vec_vid01.S
new file mode 100644
index 0000000..c4daa80
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid01.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.01, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_01
+ .type _nds32_vector_01, @function
+_nds32_vector_01:
+1:
+ j 1b
+ .size _nds32_vector_01, .-_nds32_vector_01
diff --git libgcc/config/nds32/isr-library/vec_vid01_4b.S libgcc/config/nds32/isr-library/vec_vid01_4b.S
new file mode 100644
index 0000000..8403491
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid01_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.01, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_01_4b
+ .type _nds32_vector_01_4b, @function
+_nds32_vector_01_4b:
+1:
+ j 1b
+ .size _nds32_vector_01_4b, .-_nds32_vector_01_4b
diff --git libgcc/config/nds32/isr-library/vec_vid02.S libgcc/config/nds32/isr-library/vec_vid02.S
new file mode 100644
index 0000000..7615451
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid02.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.02, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_02
+ .type _nds32_vector_02, @function
+_nds32_vector_02:
+1:
+ j 1b
+ .size _nds32_vector_02, .-_nds32_vector_02
diff --git libgcc/config/nds32/isr-library/vec_vid02_4b.S libgcc/config/nds32/isr-library/vec_vid02_4b.S
new file mode 100644
index 0000000..f203588
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid02_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.02, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_02_4b
+ .type _nds32_vector_02_4b, @function
+_nds32_vector_02_4b:
+1:
+ j 1b
+ .size _nds32_vector_02_4b, .-_nds32_vector_02_4b
diff --git libgcc/config/nds32/isr-library/vec_vid03.S libgcc/config/nds32/isr-library/vec_vid03.S
new file mode 100644
index 0000000..b59b4e7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid03.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.03, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_03
+ .type _nds32_vector_03, @function
+_nds32_vector_03:
+1:
+ j 1b
+ .size _nds32_vector_03, .-_nds32_vector_03
diff --git libgcc/config/nds32/isr-library/vec_vid03_4b.S libgcc/config/nds32/isr-library/vec_vid03_4b.S
new file mode 100644
index 0000000..8747844
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid03_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.03, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_03_4b
+ .type _nds32_vector_03_4b, @function
+_nds32_vector_03_4b:
+1:
+ j 1b
+ .size _nds32_vector_03_4b, .-_nds32_vector_03_4b
diff --git libgcc/config/nds32/isr-library/vec_vid04.S libgcc/config/nds32/isr-library/vec_vid04.S
new file mode 100644
index 0000000..3f9d787
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid04.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.04, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_04
+ .type _nds32_vector_04, @function
+_nds32_vector_04:
+1:
+ j 1b
+ .size _nds32_vector_04, .-_nds32_vector_04
diff --git libgcc/config/nds32/isr-library/vec_vid04_4b.S libgcc/config/nds32/isr-library/vec_vid04_4b.S
new file mode 100644
index 0000000..9e43e23
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid04_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.04, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_04_4b
+ .type _nds32_vector_04_4b, @function
+_nds32_vector_04_4b:
+1:
+ j 1b
+ .size _nds32_vector_04_4b, .-_nds32_vector_04_4b
diff --git libgcc/config/nds32/isr-library/vec_vid05.S libgcc/config/nds32/isr-library/vec_vid05.S
new file mode 100644
index 0000000..f507d54
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid05.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.05, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_05
+ .type _nds32_vector_05, @function
+_nds32_vector_05:
+1:
+ j 1b
+ .size _nds32_vector_05, .-_nds32_vector_05
diff --git libgcc/config/nds32/isr-library/vec_vid05_4b.S libgcc/config/nds32/isr-library/vec_vid05_4b.S
new file mode 100644
index 0000000..fb16b47
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid05_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.05, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_05_4b
+ .type _nds32_vector_05_4b, @function
+_nds32_vector_05_4b:
+1:
+ j 1b
+ .size _nds32_vector_05_4b, .-_nds32_vector_05_4b
diff --git libgcc/config/nds32/isr-library/vec_vid06.S libgcc/config/nds32/isr-library/vec_vid06.S
new file mode 100644
index 0000000..30c95f5
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid06.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.06, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_06
+ .type _nds32_vector_06, @function
+_nds32_vector_06:
+1:
+ j 1b
+ .size _nds32_vector_06, .-_nds32_vector_06
diff --git libgcc/config/nds32/isr-library/vec_vid06_4b.S libgcc/config/nds32/isr-library/vec_vid06_4b.S
new file mode 100644
index 0000000..9bde924
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid06_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.06, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_06_4b
+ .type _nds32_vector_06_4b, @function
+_nds32_vector_06_4b:
+1:
+ j 1b
+ .size _nds32_vector_06_4b, .-_nds32_vector_06_4b
diff --git libgcc/config/nds32/isr-library/vec_vid07.S libgcc/config/nds32/isr-library/vec_vid07.S
new file mode 100644
index 0000000..d702f4d
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid07.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.07, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_07
+ .type _nds32_vector_07, @function
+_nds32_vector_07:
+1:
+ j 1b
+ .size _nds32_vector_07, .-_nds32_vector_07
diff --git libgcc/config/nds32/isr-library/vec_vid07_4b.S libgcc/config/nds32/isr-library/vec_vid07_4b.S
new file mode 100644
index 0000000..8b3c17e
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid07_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.07, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_07_4b
+ .type _nds32_vector_07_4b, @function
+_nds32_vector_07_4b:
+1:
+ j 1b
+ .size _nds32_vector_07_4b, .-_nds32_vector_07_4b
diff --git libgcc/config/nds32/isr-library/vec_vid08.S libgcc/config/nds32/isr-library/vec_vid08.S
new file mode 100644
index 0000000..c22f6df
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid08.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.08, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_08
+ .type _nds32_vector_08, @function
+_nds32_vector_08:
+1:
+ j 1b
+ .size _nds32_vector_08, .-_nds32_vector_08
diff --git libgcc/config/nds32/isr-library/vec_vid08_4b.S libgcc/config/nds32/isr-library/vec_vid08_4b.S
new file mode 100644
index 0000000..3f3eeb0
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid08_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.08, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_08_4b
+ .type _nds32_vector_08_4b, @function
+_nds32_vector_08_4b:
+1:
+ j 1b
+ .size _nds32_vector_08_4b, .-_nds32_vector_08_4b
diff --git libgcc/config/nds32/isr-library/vec_vid09.S libgcc/config/nds32/isr-library/vec_vid09.S
new file mode 100644
index 0000000..3230a49
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid09.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.09, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_09
+ .type _nds32_vector_09, @function
+_nds32_vector_09:
+1:
+ j 1b
+ .size _nds32_vector_09, .-_nds32_vector_09
diff --git libgcc/config/nds32/isr-library/vec_vid09_4b.S libgcc/config/nds32/isr-library/vec_vid09_4b.S
new file mode 100644
index 0000000..56151fc
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid09_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.09, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_09_4b
+ .type _nds32_vector_09_4b, @function
+_nds32_vector_09_4b:
+1:
+ j 1b
+ .size _nds32_vector_09_4b, .-_nds32_vector_09_4b
diff --git libgcc/config/nds32/isr-library/vec_vid10.S libgcc/config/nds32/isr-library/vec_vid10.S
new file mode 100644
index 0000000..ff7e9aa
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid10.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.10, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_10
+ .type _nds32_vector_10, @function
+_nds32_vector_10:
+1:
+ j 1b
+ .size _nds32_vector_10, .-_nds32_vector_10
diff --git libgcc/config/nds32/isr-library/vec_vid10_4b.S libgcc/config/nds32/isr-library/vec_vid10_4b.S
new file mode 100644
index 0000000..a63de72
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid10_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.10, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_10_4b
+ .type _nds32_vector_10_4b, @function
+_nds32_vector_10_4b:
+1:
+ j 1b
+ .size _nds32_vector_10_4b, .-_nds32_vector_10_4b
diff --git libgcc/config/nds32/isr-library/vec_vid11.S libgcc/config/nds32/isr-library/vec_vid11.S
new file mode 100644
index 0000000..e5323d4
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid11.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.11, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_11
+ .type _nds32_vector_11, @function
+_nds32_vector_11:
+1:
+ j 1b
+ .size _nds32_vector_11, .-_nds32_vector_11
diff --git libgcc/config/nds32/isr-library/vec_vid11_4b.S libgcc/config/nds32/isr-library/vec_vid11_4b.S
new file mode 100644
index 0000000..6a5bef3
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid11_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.11, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_11_4b
+ .type _nds32_vector_11_4b, @function
+_nds32_vector_11_4b:
+1:
+ j 1b
+ .size _nds32_vector_11_4b, .-_nds32_vector_11_4b
diff --git libgcc/config/nds32/isr-library/vec_vid12.S libgcc/config/nds32/isr-library/vec_vid12.S
new file mode 100644
index 0000000..f8f206e
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid12.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.12, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_12
+ .type _nds32_vector_12, @function
+_nds32_vector_12:
+1:
+ j 1b
+ .size _nds32_vector_12, .-_nds32_vector_12
diff --git libgcc/config/nds32/isr-library/vec_vid12_4b.S libgcc/config/nds32/isr-library/vec_vid12_4b.S
new file mode 100644
index 0000000..6c4f8da
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid12_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.12, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_12_4b
+ .type _nds32_vector_12_4b, @function
+_nds32_vector_12_4b:
+1:
+ j 1b
+ .size _nds32_vector_12_4b, .-_nds32_vector_12_4b
diff --git libgcc/config/nds32/isr-library/vec_vid13.S libgcc/config/nds32/isr-library/vec_vid13.S
new file mode 100644
index 0000000..a701255
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid13.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.13, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_13
+ .type _nds32_vector_13, @function
+_nds32_vector_13:
+1:
+ j 1b
+ .size _nds32_vector_13, .-_nds32_vector_13
diff --git libgcc/config/nds32/isr-library/vec_vid13_4b.S libgcc/config/nds32/isr-library/vec_vid13_4b.S
new file mode 100644
index 0000000..b1414ee
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid13_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.13, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_13_4b
+ .type _nds32_vector_13_4b, @function
+_nds32_vector_13_4b:
+1:
+ j 1b
+ .size _nds32_vector_13_4b, .-_nds32_vector_13_4b
diff --git libgcc/config/nds32/isr-library/vec_vid14.S libgcc/config/nds32/isr-library/vec_vid14.S
new file mode 100644
index 0000000..6b48111
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid14.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.14, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_14
+ .type _nds32_vector_14, @function
+_nds32_vector_14:
+1:
+ j 1b
+ .size _nds32_vector_14, .-_nds32_vector_14
diff --git libgcc/config/nds32/isr-library/vec_vid14_4b.S libgcc/config/nds32/isr-library/vec_vid14_4b.S
new file mode 100644
index 0000000..addc809
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid14_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.14, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_14_4b
+ .type _nds32_vector_14_4b, @function
+_nds32_vector_14_4b:
+1:
+ j 1b
+ .size _nds32_vector_14_4b, .-_nds32_vector_14_4b
diff --git libgcc/config/nds32/isr-library/vec_vid15.S libgcc/config/nds32/isr-library/vec_vid15.S
new file mode 100644
index 0000000..f7e15e7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid15.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.15, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_15
+ .type _nds32_vector_15, @function
+_nds32_vector_15:
+1:
+ j 1b
+ .size _nds32_vector_15, .-_nds32_vector_15
diff --git libgcc/config/nds32/isr-library/vec_vid15_4b.S libgcc/config/nds32/isr-library/vec_vid15_4b.S
new file mode 100644
index 0000000..1e1ee15
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid15_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.15, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_15_4b
+ .type _nds32_vector_15_4b, @function
+_nds32_vector_15_4b:
+1:
+ j 1b
+ .size _nds32_vector_15_4b, .-_nds32_vector_15_4b
diff --git libgcc/config/nds32/isr-library/vec_vid16.S libgcc/config/nds32/isr-library/vec_vid16.S
new file mode 100644
index 0000000..2049897
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid16.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.16, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_16
+ .type _nds32_vector_16, @function
+_nds32_vector_16:
+1:
+ j 1b
+ .size _nds32_vector_16, .-_nds32_vector_16
diff --git libgcc/config/nds32/isr-library/vec_vid16_4b.S libgcc/config/nds32/isr-library/vec_vid16_4b.S
new file mode 100644
index 0000000..f160797
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid16_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.16, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_16_4b
+ .type _nds32_vector_16_4b, @function
+_nds32_vector_16_4b:
+1:
+ j 1b
+ .size _nds32_vector_16_4b, .-_nds32_vector_16_4b
diff --git libgcc/config/nds32/isr-library/vec_vid17.S libgcc/config/nds32/isr-library/vec_vid17.S
new file mode 100644
index 0000000..e7db716
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid17.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.17, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_17
+ .type _nds32_vector_17, @function
+_nds32_vector_17:
+1:
+ j 1b
+ .size _nds32_vector_17, .-_nds32_vector_17
diff --git libgcc/config/nds32/isr-library/vec_vid17_4b.S libgcc/config/nds32/isr-library/vec_vid17_4b.S
new file mode 100644
index 0000000..065696f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid17_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.17, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_17_4b
+ .type _nds32_vector_17_4b, @function
+_nds32_vector_17_4b:
+1:
+ j 1b
+ .size _nds32_vector_17_4b, .-_nds32_vector_17_4b
diff --git libgcc/config/nds32/isr-library/vec_vid18.S libgcc/config/nds32/isr-library/vec_vid18.S
new file mode 100644
index 0000000..39cf052
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid18.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.18, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_18
+ .type _nds32_vector_18, @function
+_nds32_vector_18:
+1:
+ j 1b
+ .size _nds32_vector_18, .-_nds32_vector_18
diff --git libgcc/config/nds32/isr-library/vec_vid18_4b.S libgcc/config/nds32/isr-library/vec_vid18_4b.S
new file mode 100644
index 0000000..ef41e4b
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid18_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.18, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_18_4b
+ .type _nds32_vector_18_4b, @function
+_nds32_vector_18_4b:
+1:
+ j 1b
+ .size _nds32_vector_18_4b, .-_nds32_vector_18_4b
diff --git libgcc/config/nds32/isr-library/vec_vid19.S libgcc/config/nds32/isr-library/vec_vid19.S
new file mode 100644
index 0000000..be05931
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid19.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.19, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_19
+ .type _nds32_vector_19, @function
+_nds32_vector_19:
+1:
+ j 1b
+ .size _nds32_vector_19, .-_nds32_vector_19
diff --git libgcc/config/nds32/isr-library/vec_vid19_4b.S libgcc/config/nds32/isr-library/vec_vid19_4b.S
new file mode 100644
index 0000000..94b4134
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid19_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.19, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_19_4b
+ .type _nds32_vector_19_4b, @function
+_nds32_vector_19_4b:
+1:
+ j 1b
+ .size _nds32_vector_19_4b, .-_nds32_vector_19_4b
diff --git libgcc/config/nds32/isr-library/vec_vid20.S libgcc/config/nds32/isr-library/vec_vid20.S
new file mode 100644
index 0000000..4f27687
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid20.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.20, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_20
+ .type _nds32_vector_20, @function
+_nds32_vector_20:
+1:
+ j 1b
+ .size _nds32_vector_20, .-_nds32_vector_20
diff --git libgcc/config/nds32/isr-library/vec_vid20_4b.S libgcc/config/nds32/isr-library/vec_vid20_4b.S
new file mode 100644
index 0000000..42aae42
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid20_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.20, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_20_4b
+ .type _nds32_vector_20_4b, @function
+_nds32_vector_20_4b:
+1:
+ j 1b
+ .size _nds32_vector_20_4b, .-_nds32_vector_20_4b
diff --git libgcc/config/nds32/isr-library/vec_vid21.S libgcc/config/nds32/isr-library/vec_vid21.S
new file mode 100644
index 0000000..11aab70
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid21.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.21, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_21
+ .type _nds32_vector_21, @function
+_nds32_vector_21:
+1:
+ j 1b
+ .size _nds32_vector_21, .-_nds32_vector_21
diff --git libgcc/config/nds32/isr-library/vec_vid21_4b.S libgcc/config/nds32/isr-library/vec_vid21_4b.S
new file mode 100644
index 0000000..283d2b7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid21_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.21, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_21_4b
+ .type _nds32_vector_21_4b, @function
+_nds32_vector_21_4b:
+1:
+ j 1b
+ .size _nds32_vector_21_4b, .-_nds32_vector_21_4b
diff --git libgcc/config/nds32/isr-library/vec_vid22.S libgcc/config/nds32/isr-library/vec_vid22.S
new file mode 100644
index 0000000..7821e33
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid22.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.22, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_22
+ .type _nds32_vector_22, @function
+_nds32_vector_22:
+1:
+ j 1b
+ .size _nds32_vector_22, .-_nds32_vector_22
diff --git libgcc/config/nds32/isr-library/vec_vid22_4b.S libgcc/config/nds32/isr-library/vec_vid22_4b.S
new file mode 100644
index 0000000..8ad7a7f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid22_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.22, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_22_4b
+ .type _nds32_vector_22_4b, @function
+_nds32_vector_22_4b:
+1:
+ j 1b
+ .size _nds32_vector_22_4b, .-_nds32_vector_22_4b
diff --git libgcc/config/nds32/isr-library/vec_vid23.S libgcc/config/nds32/isr-library/vec_vid23.S
new file mode 100644
index 0000000..72918e8c4
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid23.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.23, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_23
+ .type _nds32_vector_23, @function
+_nds32_vector_23:
+1:
+ j 1b
+ .size _nds32_vector_23, .-_nds32_vector_23
diff --git libgcc/config/nds32/isr-library/vec_vid23_4b.S libgcc/config/nds32/isr-library/vec_vid23_4b.S
new file mode 100644
index 0000000..fb35443
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid23_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.23, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_23_4b
+ .type _nds32_vector_23_4b, @function
+_nds32_vector_23_4b:
+1:
+ j 1b
+ .size _nds32_vector_23_4b, .-_nds32_vector_23_4b
diff --git libgcc/config/nds32/isr-library/vec_vid24.S libgcc/config/nds32/isr-library/vec_vid24.S
new file mode 100644
index 0000000..2714be8
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid24.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.24, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_24
+ .type _nds32_vector_24, @function
+_nds32_vector_24:
+1:
+ j 1b
+ .size _nds32_vector_24, .-_nds32_vector_24
diff --git libgcc/config/nds32/isr-library/vec_vid24_4b.S libgcc/config/nds32/isr-library/vec_vid24_4b.S
new file mode 100644
index 0000000..535deb9
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid24_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.24, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_24_4b
+ .type _nds32_vector_24_4b, @function
+_nds32_vector_24_4b:
+1:
+ j 1b
+ .size _nds32_vector_24_4b, .-_nds32_vector_24_4b
diff --git libgcc/config/nds32/isr-library/vec_vid25.S libgcc/config/nds32/isr-library/vec_vid25.S
new file mode 100644
index 0000000..2dde0a2
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid25.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.25, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_25
+ .type _nds32_vector_25, @function
+_nds32_vector_25:
+1:
+ j 1b
+ .size _nds32_vector_25, .-_nds32_vector_25
diff --git libgcc/config/nds32/isr-library/vec_vid25_4b.S libgcc/config/nds32/isr-library/vec_vid25_4b.S
new file mode 100644
index 0000000..0ddd4d2
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid25_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.25, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_25_4b
+ .type _nds32_vector_25_4b, @function
+_nds32_vector_25_4b:
+1:
+ j 1b
+ .size _nds32_vector_25_4b, .-_nds32_vector_25_4b
diff --git libgcc/config/nds32/isr-library/vec_vid26.S libgcc/config/nds32/isr-library/vec_vid26.S
new file mode 100644
index 0000000..598ce9a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid26.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.26, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_26
+ .type _nds32_vector_26, @function
+_nds32_vector_26:
+1:
+ j 1b
+ .size _nds32_vector_26, .-_nds32_vector_26
diff --git libgcc/config/nds32/isr-library/vec_vid26_4b.S libgcc/config/nds32/isr-library/vec_vid26_4b.S
new file mode 100644
index 0000000..385ea04
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid26_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.26, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_26_4b
+ .type _nds32_vector_26_4b, @function
+_nds32_vector_26_4b:
+1:
+ j 1b
+ .size _nds32_vector_26_4b, .-_nds32_vector_26_4b
diff --git libgcc/config/nds32/isr-library/vec_vid27.S libgcc/config/nds32/isr-library/vec_vid27.S
new file mode 100644
index 0000000..6835bdc
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid27.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.27, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_27
+ .type _nds32_vector_27, @function
+_nds32_vector_27:
+1:
+ j 1b
+ .size _nds32_vector_27, .-_nds32_vector_27
diff --git libgcc/config/nds32/isr-library/vec_vid27_4b.S libgcc/config/nds32/isr-library/vec_vid27_4b.S
new file mode 100644
index 0000000..a373683
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid27_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.27, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_27_4b
+ .type _nds32_vector_27_4b, @function
+_nds32_vector_27_4b:
+1:
+ j 1b
+ .size _nds32_vector_27_4b, .-_nds32_vector_27_4b
diff --git libgcc/config/nds32/isr-library/vec_vid28.S libgcc/config/nds32/isr-library/vec_vid28.S
new file mode 100644
index 0000000..1db9ee7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid28.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.28, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_28
+ .type _nds32_vector_28, @function
+_nds32_vector_28:
+1:
+ j 1b
+ .size _nds32_vector_28, .-_nds32_vector_28
diff --git libgcc/config/nds32/isr-library/vec_vid28_4b.S libgcc/config/nds32/isr-library/vec_vid28_4b.S
new file mode 100644
index 0000000..3492f6e
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid28_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.28, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_28_4b
+ .type _nds32_vector_28_4b, @function
+_nds32_vector_28_4b:
+1:
+ j 1b
+ .size _nds32_vector_28_4b, .-_nds32_vector_28_4b
diff --git libgcc/config/nds32/isr-library/vec_vid29.S libgcc/config/nds32/isr-library/vec_vid29.S
new file mode 100644
index 0000000..4a4ac01
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid29.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.29, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_29
+ .type _nds32_vector_29, @function
+_nds32_vector_29:
+1:
+ j 1b
+ .size _nds32_vector_29, .-_nds32_vector_29
diff --git libgcc/config/nds32/isr-library/vec_vid29_4b.S libgcc/config/nds32/isr-library/vec_vid29_4b.S
new file mode 100644
index 0000000..e91a6c9
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid29_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.29, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_29_4b
+ .type _nds32_vector_29_4b, @function
+_nds32_vector_29_4b:
+1:
+ j 1b
+ .size _nds32_vector_29_4b, .-_nds32_vector_29_4b
diff --git libgcc/config/nds32/isr-library/vec_vid30.S libgcc/config/nds32/isr-library/vec_vid30.S
new file mode 100644
index 0000000..7822219
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid30.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.30, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_30
+ .type _nds32_vector_30, @function
+_nds32_vector_30:
+1:
+ j 1b
+ .size _nds32_vector_30, .-_nds32_vector_30
diff --git libgcc/config/nds32/isr-library/vec_vid30_4b.S libgcc/config/nds32/isr-library/vec_vid30_4b.S
new file mode 100644
index 0000000..3161536
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid30_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.30, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_30_4b
+ .type _nds32_vector_30_4b, @function
+_nds32_vector_30_4b:
+1:
+ j 1b
+ .size _nds32_vector_30_4b, .-_nds32_vector_30_4b
diff --git libgcc/config/nds32/isr-library/vec_vid31.S libgcc/config/nds32/isr-library/vec_vid31.S
new file mode 100644
index 0000000..42d634a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid31.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.31, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_31
+ .type _nds32_vector_31, @function
+_nds32_vector_31:
+1:
+ j 1b
+ .size _nds32_vector_31, .-_nds32_vector_31
diff --git libgcc/config/nds32/isr-library/vec_vid31_4b.S libgcc/config/nds32/isr-library/vec_vid31_4b.S
new file mode 100644
index 0000000..fb8af23
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid31_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.31, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_31_4b
+ .type _nds32_vector_31_4b, @function
+_nds32_vector_31_4b:
+1:
+ j 1b
+ .size _nds32_vector_31_4b, .-_nds32_vector_31_4b
diff --git libgcc/config/nds32/isr-library/vec_vid32.S libgcc/config/nds32/isr-library/vec_vid32.S
new file mode 100644
index 0000000..5eacff1
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid32.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.32, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_32
+ .type _nds32_vector_32, @function
+_nds32_vector_32:
+1:
+ j 1b
+ .size _nds32_vector_32, .-_nds32_vector_32
diff --git libgcc/config/nds32/isr-library/vec_vid32_4b.S libgcc/config/nds32/isr-library/vec_vid32_4b.S
new file mode 100644
index 0000000..5c0ff91
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid32_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.32, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_32_4b
+ .type _nds32_vector_32_4b, @function
+_nds32_vector_32_4b:
+1:
+ j 1b
+ .size _nds32_vector_32_4b, .-_nds32_vector_32_4b
diff --git libgcc/config/nds32/isr-library/vec_vid33.S libgcc/config/nds32/isr-library/vec_vid33.S
new file mode 100644
index 0000000..8c541ed
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid33.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.33, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_33
+ .type _nds32_vector_33, @function
+_nds32_vector_33:
+1:
+ j 1b
+ .size _nds32_vector_33, .-_nds32_vector_33
diff --git libgcc/config/nds32/isr-library/vec_vid33_4b.S libgcc/config/nds32/isr-library/vec_vid33_4b.S
new file mode 100644
index 0000000..a292f0f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid33_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.33, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_33_4b
+ .type _nds32_vector_33_4b, @function
+_nds32_vector_33_4b:
+1:
+ j 1b
+ .size _nds32_vector_33_4b, .-_nds32_vector_33_4b
diff --git libgcc/config/nds32/isr-library/vec_vid34.S libgcc/config/nds32/isr-library/vec_vid34.S
new file mode 100644
index 0000000..52d9aae
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid34.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.34, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_34
+ .type _nds32_vector_34, @function
+_nds32_vector_34:
+1:
+ j 1b
+ .size _nds32_vector_34, .-_nds32_vector_34
diff --git libgcc/config/nds32/isr-library/vec_vid34_4b.S libgcc/config/nds32/isr-library/vec_vid34_4b.S
new file mode 100644
index 0000000..465af48
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid34_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.34, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_34_4b
+ .type _nds32_vector_34_4b, @function
+_nds32_vector_34_4b:
+1:
+ j 1b
+ .size _nds32_vector_34_4b, .-_nds32_vector_34_4b
diff --git libgcc/config/nds32/isr-library/vec_vid35.S libgcc/config/nds32/isr-library/vec_vid35.S
new file mode 100644
index 0000000..eef4b2a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid35.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.35, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_35
+ .type _nds32_vector_35, @function
+_nds32_vector_35:
+1:
+ j 1b
+ .size _nds32_vector_35, .-_nds32_vector_35
diff --git libgcc/config/nds32/isr-library/vec_vid35_4b.S libgcc/config/nds32/isr-library/vec_vid35_4b.S
new file mode 100644
index 0000000..2328e58
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid35_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.35, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_35_4b
+ .type _nds32_vector_35_4b, @function
+_nds32_vector_35_4b:
+1:
+ j 1b
+ .size _nds32_vector_35_4b, .-_nds32_vector_35_4b
diff --git libgcc/config/nds32/isr-library/vec_vid36.S libgcc/config/nds32/isr-library/vec_vid36.S
new file mode 100644
index 0000000..0a130fc
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid36.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.36, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_36
+ .type _nds32_vector_36, @function
+_nds32_vector_36:
+1:
+ j 1b
+ .size _nds32_vector_36, .-_nds32_vector_36
diff --git libgcc/config/nds32/isr-library/vec_vid36_4b.S libgcc/config/nds32/isr-library/vec_vid36_4b.S
new file mode 100644
index 0000000..d1ecee2
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid36_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.36, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_36_4b
+ .type _nds32_vector_36_4b, @function
+_nds32_vector_36_4b:
+1:
+ j 1b
+ .size _nds32_vector_36_4b, .-_nds32_vector_36_4b
diff --git libgcc/config/nds32/isr-library/vec_vid37.S libgcc/config/nds32/isr-library/vec_vid37.S
new file mode 100644
index 0000000..4ee8f6b
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid37.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.37, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_37
+ .type _nds32_vector_37, @function
+_nds32_vector_37:
+1:
+ j 1b
+ .size _nds32_vector_37, .-_nds32_vector_37
diff --git libgcc/config/nds32/isr-library/vec_vid37_4b.S libgcc/config/nds32/isr-library/vec_vid37_4b.S
new file mode 100644
index 0000000..5d74d27
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid37_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.37, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_37_4b
+ .type _nds32_vector_37_4b, @function
+_nds32_vector_37_4b:
+1:
+ j 1b
+ .size _nds32_vector_37_4b, .-_nds32_vector_37_4b
diff --git libgcc/config/nds32/isr-library/vec_vid38.S libgcc/config/nds32/isr-library/vec_vid38.S
new file mode 100644
index 0000000..add73d7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid38.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.38, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_38
+ .type _nds32_vector_38, @function
+_nds32_vector_38:
+1:
+ j 1b
+ .size _nds32_vector_38, .-_nds32_vector_38
diff --git libgcc/config/nds32/isr-library/vec_vid38_4b.S libgcc/config/nds32/isr-library/vec_vid38_4b.S
new file mode 100644
index 0000000..435466d
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid38_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.38, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_38_4b
+ .type _nds32_vector_38_4b, @function
+_nds32_vector_38_4b:
+1:
+ j 1b
+ .size _nds32_vector_38_4b, .-_nds32_vector_38_4b
diff --git libgcc/config/nds32/isr-library/vec_vid39.S libgcc/config/nds32/isr-library/vec_vid39.S
new file mode 100644
index 0000000..a4ac940
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid39.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.39, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_39
+ .type _nds32_vector_39, @function
+_nds32_vector_39:
+1:
+ j 1b
+ .size _nds32_vector_39, .-_nds32_vector_39
diff --git libgcc/config/nds32/isr-library/vec_vid39_4b.S libgcc/config/nds32/isr-library/vec_vid39_4b.S
new file mode 100644
index 0000000..24762c3
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid39_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.39, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_39_4b
+ .type _nds32_vector_39_4b, @function
+_nds32_vector_39_4b:
+1:
+ j 1b
+ .size _nds32_vector_39_4b, .-_nds32_vector_39_4b
diff --git libgcc/config/nds32/isr-library/vec_vid40.S libgcc/config/nds32/isr-library/vec_vid40.S
new file mode 100644
index 0000000..b3e4f4a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid40.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.40, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_40
+ .type _nds32_vector_40, @function
+_nds32_vector_40:
+1:
+ j 1b
+ .size _nds32_vector_40, .-_nds32_vector_40
diff --git libgcc/config/nds32/isr-library/vec_vid40_4b.S libgcc/config/nds32/isr-library/vec_vid40_4b.S
new file mode 100644
index 0000000..d726854
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid40_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.40, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_40_4b
+ .type _nds32_vector_40_4b, @function
+_nds32_vector_40_4b:
+1:
+ j 1b
+ .size _nds32_vector_40_4b, .-_nds32_vector_40_4b
diff --git libgcc/config/nds32/isr-library/vec_vid41.S libgcc/config/nds32/isr-library/vec_vid41.S
new file mode 100644
index 0000000..931c05c
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid41.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.41, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_41
+ .type _nds32_vector_41, @function
+_nds32_vector_41:
+1:
+ j 1b
+ .size _nds32_vector_41, .-_nds32_vector_41
diff --git libgcc/config/nds32/isr-library/vec_vid41_4b.S libgcc/config/nds32/isr-library/vec_vid41_4b.S
new file mode 100644
index 0000000..dbb2737
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid41_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.41, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_41_4b
+ .type _nds32_vector_41_4b, @function
+_nds32_vector_41_4b:
+1:
+ j 1b
+ .size _nds32_vector_41_4b, .-_nds32_vector_41_4b
diff --git libgcc/config/nds32/isr-library/vec_vid42.S libgcc/config/nds32/isr-library/vec_vid42.S
new file mode 100644
index 0000000..ee1fc1d
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid42.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.42, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_42
+ .type _nds32_vector_42, @function
+_nds32_vector_42:
+1:
+ j 1b
+ .size _nds32_vector_42, .-_nds32_vector_42
diff --git libgcc/config/nds32/isr-library/vec_vid42_4b.S libgcc/config/nds32/isr-library/vec_vid42_4b.S
new file mode 100644
index 0000000..28a2e57
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid42_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.42, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_42_4b
+ .type _nds32_vector_42_4b, @function
+_nds32_vector_42_4b:
+1:
+ j 1b
+ .size _nds32_vector_42_4b, .-_nds32_vector_42_4b
diff --git libgcc/config/nds32/isr-library/vec_vid43.S libgcc/config/nds32/isr-library/vec_vid43.S
new file mode 100644
index 0000000..a46cf5d
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid43.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.43, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_43
+ .type _nds32_vector_43, @function
+_nds32_vector_43:
+1:
+ j 1b
+ .size _nds32_vector_43, .-_nds32_vector_43
diff --git libgcc/config/nds32/isr-library/vec_vid43_4b.S libgcc/config/nds32/isr-library/vec_vid43_4b.S
new file mode 100644
index 0000000..b92b359
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid43_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.43, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_43_4b
+ .type _nds32_vector_43_4b, @function
+_nds32_vector_43_4b:
+1:
+ j 1b
+ .size _nds32_vector_43_4b, .-_nds32_vector_43_4b
diff --git libgcc/config/nds32/isr-library/vec_vid44.S libgcc/config/nds32/isr-library/vec_vid44.S
new file mode 100644
index 0000000..e838efe
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid44.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.44, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_44
+ .type _nds32_vector_44, @function
+_nds32_vector_44:
+1:
+ j 1b
+ .size _nds32_vector_44, .-_nds32_vector_44
diff --git libgcc/config/nds32/isr-library/vec_vid44_4b.S libgcc/config/nds32/isr-library/vec_vid44_4b.S
new file mode 100644
index 0000000..c29788a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid44_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.44, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_44_4b
+ .type _nds32_vector_44_4b, @function
+_nds32_vector_44_4b:
+1:
+ j 1b
+ .size _nds32_vector_44_4b, .-_nds32_vector_44_4b
diff --git libgcc/config/nds32/isr-library/vec_vid45.S libgcc/config/nds32/isr-library/vec_vid45.S
new file mode 100644
index 0000000..0a4450f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid45.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.45, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_45
+ .type _nds32_vector_45, @function
+_nds32_vector_45:
+1:
+ j 1b
+ .size _nds32_vector_45, .-_nds32_vector_45
diff --git libgcc/config/nds32/isr-library/vec_vid45_4b.S libgcc/config/nds32/isr-library/vec_vid45_4b.S
new file mode 100644
index 0000000..895933c
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid45_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.45, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_45_4b
+ .type _nds32_vector_45_4b, @function
+_nds32_vector_45_4b:
+1:
+ j 1b
+ .size _nds32_vector_45_4b, .-_nds32_vector_45_4b
diff --git libgcc/config/nds32/isr-library/vec_vid46.S libgcc/config/nds32/isr-library/vec_vid46.S
new file mode 100644
index 0000000..aa97ff7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid46.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.46, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_46
+ .type _nds32_vector_46, @function
+_nds32_vector_46:
+1:
+ j 1b
+ .size _nds32_vector_46, .-_nds32_vector_46
diff --git libgcc/config/nds32/isr-library/vec_vid46_4b.S libgcc/config/nds32/isr-library/vec_vid46_4b.S
new file mode 100644
index 0000000..07a54f5
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid46_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.46, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_46_4b
+ .type _nds32_vector_46_4b, @function
+_nds32_vector_46_4b:
+1:
+ j 1b
+ .size _nds32_vector_46_4b, .-_nds32_vector_46_4b
diff --git libgcc/config/nds32/isr-library/vec_vid47.S libgcc/config/nds32/isr-library/vec_vid47.S
new file mode 100644
index 0000000..687737a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid47.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.47, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_47
+ .type _nds32_vector_47, @function
+_nds32_vector_47:
+1:
+ j 1b
+ .size _nds32_vector_47, .-_nds32_vector_47
diff --git libgcc/config/nds32/isr-library/vec_vid47_4b.S libgcc/config/nds32/isr-library/vec_vid47_4b.S
new file mode 100644
index 0000000..654fec5
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid47_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.47, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_47_4b
+ .type _nds32_vector_47_4b, @function
+_nds32_vector_47_4b:
+1:
+ j 1b
+ .size _nds32_vector_47_4b, .-_nds32_vector_47_4b
diff --git libgcc/config/nds32/isr-library/vec_vid48.S libgcc/config/nds32/isr-library/vec_vid48.S
new file mode 100644
index 0000000..b8311f4
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid48.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.48, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_48
+ .type _nds32_vector_48, @function
+_nds32_vector_48:
+1:
+ j 1b
+ .size _nds32_vector_48, .-_nds32_vector_48
diff --git libgcc/config/nds32/isr-library/vec_vid48_4b.S libgcc/config/nds32/isr-library/vec_vid48_4b.S
new file mode 100644
index 0000000..1d1213f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid48_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.48, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_48_4b
+ .type _nds32_vector_48_4b, @function
+_nds32_vector_48_4b:
+1:
+ j 1b
+ .size _nds32_vector_48_4b, .-_nds32_vector_48_4b
diff --git libgcc/config/nds32/isr-library/vec_vid49.S libgcc/config/nds32/isr-library/vec_vid49.S
new file mode 100644
index 0000000..e9f0fa3
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid49.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.49, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_49
+ .type _nds32_vector_49, @function
+_nds32_vector_49:
+1:
+ j 1b
+ .size _nds32_vector_49, .-_nds32_vector_49
diff --git libgcc/config/nds32/isr-library/vec_vid49_4b.S libgcc/config/nds32/isr-library/vec_vid49_4b.S
new file mode 100644
index 0000000..f5dd1c1
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid49_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.49, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_49_4b
+ .type _nds32_vector_49_4b, @function
+_nds32_vector_49_4b:
+1:
+ j 1b
+ .size _nds32_vector_49_4b, .-_nds32_vector_49_4b
diff --git libgcc/config/nds32/isr-library/vec_vid50.S libgcc/config/nds32/isr-library/vec_vid50.S
new file mode 100644
index 0000000..5144608
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid50.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.50, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_50
+ .type _nds32_vector_50, @function
+_nds32_vector_50:
+1:
+ j 1b
+ .size _nds32_vector_50, .-_nds32_vector_50
diff --git libgcc/config/nds32/isr-library/vec_vid50_4b.S libgcc/config/nds32/isr-library/vec_vid50_4b.S
new file mode 100644
index 0000000..3f6ffe3
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid50_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.50, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_50_4b
+ .type _nds32_vector_50_4b, @function
+_nds32_vector_50_4b:
+1:
+ j 1b
+ .size _nds32_vector_50_4b, .-_nds32_vector_50_4b
diff --git libgcc/config/nds32/isr-library/vec_vid51.S libgcc/config/nds32/isr-library/vec_vid51.S
new file mode 100644
index 0000000..f80417e
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid51.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.51, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_51
+ .type _nds32_vector_51, @function
+_nds32_vector_51:
+1:
+ j 1b
+ .size _nds32_vector_51, .-_nds32_vector_51
diff --git libgcc/config/nds32/isr-library/vec_vid51_4b.S libgcc/config/nds32/isr-library/vec_vid51_4b.S
new file mode 100644
index 0000000..db7cc63
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid51_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.51, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_51_4b
+ .type _nds32_vector_51_4b, @function
+_nds32_vector_51_4b:
+1:
+ j 1b
+ .size _nds32_vector_51_4b, .-_nds32_vector_51_4b
diff --git libgcc/config/nds32/isr-library/vec_vid52.S libgcc/config/nds32/isr-library/vec_vid52.S
new file mode 100644
index 0000000..6e24f88
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid52.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.52, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_52
+ .type _nds32_vector_52, @function
+_nds32_vector_52:
+1:
+ j 1b
+ .size _nds32_vector_52, .-_nds32_vector_52
diff --git libgcc/config/nds32/isr-library/vec_vid52_4b.S libgcc/config/nds32/isr-library/vec_vid52_4b.S
new file mode 100644
index 0000000..dce3393
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid52_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.52, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_52_4b
+ .type _nds32_vector_52_4b, @function
+_nds32_vector_52_4b:
+1:
+ j 1b
+ .size _nds32_vector_52_4b, .-_nds32_vector_52_4b
diff --git libgcc/config/nds32/isr-library/vec_vid53.S libgcc/config/nds32/isr-library/vec_vid53.S
new file mode 100644
index 0000000..9a630e7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid53.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.53, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_53
+ .type _nds32_vector_53, @function
+_nds32_vector_53:
+1:
+ j 1b
+ .size _nds32_vector_53, .-_nds32_vector_53
diff --git libgcc/config/nds32/isr-library/vec_vid53_4b.S libgcc/config/nds32/isr-library/vec_vid53_4b.S
new file mode 100644
index 0000000..e8ac32f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid53_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.53, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_53_4b
+ .type _nds32_vector_53_4b, @function
+_nds32_vector_53_4b:
+1:
+ j 1b
+ .size _nds32_vector_53_4b, .-_nds32_vector_53_4b
diff --git libgcc/config/nds32/isr-library/vec_vid54.S libgcc/config/nds32/isr-library/vec_vid54.S
new file mode 100644
index 0000000..56b4abc
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid54.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.54, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_54
+ .type _nds32_vector_54, @function
+_nds32_vector_54:
+1:
+ j 1b
+ .size _nds32_vector_54, .-_nds32_vector_54
diff --git libgcc/config/nds32/isr-library/vec_vid54_4b.S libgcc/config/nds32/isr-library/vec_vid54_4b.S
new file mode 100644
index 0000000..87f8e24
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid54_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.54, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_54_4b
+ .type _nds32_vector_54_4b, @function
+_nds32_vector_54_4b:
+1:
+ j 1b
+ .size _nds32_vector_54_4b, .-_nds32_vector_54_4b
diff --git libgcc/config/nds32/isr-library/vec_vid55.S libgcc/config/nds32/isr-library/vec_vid55.S
new file mode 100644
index 0000000..9ac33f5
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid55.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.55, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_55
+ .type _nds32_vector_55, @function
+_nds32_vector_55:
+1:
+ j 1b
+ .size _nds32_vector_55, .-_nds32_vector_55
diff --git libgcc/config/nds32/isr-library/vec_vid55_4b.S libgcc/config/nds32/isr-library/vec_vid55_4b.S
new file mode 100644
index 0000000..01632ee
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid55_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.55, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_55_4b
+ .type _nds32_vector_55_4b, @function
+_nds32_vector_55_4b:
+1:
+ j 1b
+ .size _nds32_vector_55_4b, .-_nds32_vector_55_4b
diff --git libgcc/config/nds32/isr-library/vec_vid56.S libgcc/config/nds32/isr-library/vec_vid56.S
new file mode 100644
index 0000000..896a7e2
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid56.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.56, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_56
+ .type _nds32_vector_56, @function
+_nds32_vector_56:
+1:
+ j 1b
+ .size _nds32_vector_56, .-_nds32_vector_56
diff --git libgcc/config/nds32/isr-library/vec_vid56_4b.S libgcc/config/nds32/isr-library/vec_vid56_4b.S
new file mode 100644
index 0000000..f5b1ee5
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid56_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.56, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_56_4b
+ .type _nds32_vector_56_4b, @function
+_nds32_vector_56_4b:
+1:
+ j 1b
+ .size _nds32_vector_56_4b, .-_nds32_vector_56_4b
diff --git libgcc/config/nds32/isr-library/vec_vid57.S libgcc/config/nds32/isr-library/vec_vid57.S
new file mode 100644
index 0000000..14d9497
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid57.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.57, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_57
+ .type _nds32_vector_57, @function
+_nds32_vector_57:
+1:
+ j 1b
+ .size _nds32_vector_57, .-_nds32_vector_57
diff --git libgcc/config/nds32/isr-library/vec_vid57_4b.S libgcc/config/nds32/isr-library/vec_vid57_4b.S
new file mode 100644
index 0000000..ed6cea6
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid57_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.57, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_57_4b
+ .type _nds32_vector_57_4b, @function
+_nds32_vector_57_4b:
+1:
+ j 1b
+ .size _nds32_vector_57_4b, .-_nds32_vector_57_4b
diff --git libgcc/config/nds32/isr-library/vec_vid58.S libgcc/config/nds32/isr-library/vec_vid58.S
new file mode 100644
index 0000000..efa1ef7
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid58.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.58, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_58
+ .type _nds32_vector_58, @function
+_nds32_vector_58:
+1:
+ j 1b
+ .size _nds32_vector_58, .-_nds32_vector_58
diff --git libgcc/config/nds32/isr-library/vec_vid58_4b.S libgcc/config/nds32/isr-library/vec_vid58_4b.S
new file mode 100644
index 0000000..f2d333a
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid58_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.58, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_58_4b
+ .type _nds32_vector_58_4b, @function
+_nds32_vector_58_4b:
+1:
+ j 1b
+ .size _nds32_vector_58_4b, .-_nds32_vector_58_4b
diff --git libgcc/config/nds32/isr-library/vec_vid59.S libgcc/config/nds32/isr-library/vec_vid59.S
new file mode 100644
index 0000000..8b11445
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid59.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.59, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_59
+ .type _nds32_vector_59, @function
+_nds32_vector_59:
+1:
+ j 1b
+ .size _nds32_vector_59, .-_nds32_vector_59
diff --git libgcc/config/nds32/isr-library/vec_vid59_4b.S libgcc/config/nds32/isr-library/vec_vid59_4b.S
new file mode 100644
index 0000000..c859d23
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid59_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.59, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_59_4b
+ .type _nds32_vector_59_4b, @function
+_nds32_vector_59_4b:
+1:
+ j 1b
+ .size _nds32_vector_59_4b, .-_nds32_vector_59_4b
diff --git libgcc/config/nds32/isr-library/vec_vid60.S libgcc/config/nds32/isr-library/vec_vid60.S
new file mode 100644
index 0000000..3b4d2b0
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid60.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.60, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_60
+ .type _nds32_vector_60, @function
+_nds32_vector_60:
+1:
+ j 1b
+ .size _nds32_vector_60, .-_nds32_vector_60
diff --git libgcc/config/nds32/isr-library/vec_vid60_4b.S libgcc/config/nds32/isr-library/vec_vid60_4b.S
new file mode 100644
index 0000000..2486091
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid60_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.60, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_60_4b
+ .type _nds32_vector_60_4b, @function
+_nds32_vector_60_4b:
+1:
+ j 1b
+ .size _nds32_vector_60_4b, .-_nds32_vector_60_4b
diff --git libgcc/config/nds32/isr-library/vec_vid61.S libgcc/config/nds32/isr-library/vec_vid61.S
new file mode 100644
index 0000000..0aa643b
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid61.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.61, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_61
+ .type _nds32_vector_61, @function
+_nds32_vector_61:
+1:
+ j 1b
+ .size _nds32_vector_61, .-_nds32_vector_61
diff --git libgcc/config/nds32/isr-library/vec_vid61_4b.S libgcc/config/nds32/isr-library/vec_vid61_4b.S
new file mode 100644
index 0000000..59b679c
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid61_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.61, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_61_4b
+ .type _nds32_vector_61_4b, @function
+_nds32_vector_61_4b:
+1:
+ j 1b
+ .size _nds32_vector_61_4b, .-_nds32_vector_61_4b
diff --git libgcc/config/nds32/isr-library/vec_vid62.S libgcc/config/nds32/isr-library/vec_vid62.S
new file mode 100644
index 0000000..3558421
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid62.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.62, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_62
+ .type _nds32_vector_62, @function
+_nds32_vector_62:
+1:
+ j 1b
+ .size _nds32_vector_62, .-_nds32_vector_62
diff --git libgcc/config/nds32/isr-library/vec_vid62_4b.S libgcc/config/nds32/isr-library/vec_vid62_4b.S
new file mode 100644
index 0000000..b265d02
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid62_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.62, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_62_4b
+ .type _nds32_vector_62_4b, @function
+_nds32_vector_62_4b:
+1:
+ j 1b
+ .size _nds32_vector_62_4b, .-_nds32_vector_62_4b
diff --git libgcc/config/nds32/isr-library/vec_vid63.S libgcc/config/nds32/isr-library/vec_vid63.S
new file mode 100644
index 0000000..5ea4cc8
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid63.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.63, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_63
+ .type _nds32_vector_63, @function
+_nds32_vector_63:
+1:
+ j 1b
+ .size _nds32_vector_63, .-_nds32_vector_63
diff --git libgcc/config/nds32/isr-library/vec_vid63_4b.S libgcc/config/nds32/isr-library/vec_vid63_4b.S
new file mode 100644
index 0000000..481346c
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid63_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.63, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_63_4b
+ .type _nds32_vector_63_4b, @function
+_nds32_vector_63_4b:
+1:
+ j 1b
+ .size _nds32_vector_63_4b, .-_nds32_vector_63_4b
diff --git libgcc/config/nds32/isr-library/vec_vid64.S libgcc/config/nds32/isr-library/vec_vid64.S
new file mode 100644
index 0000000..4ed1f0e
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid64.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.64, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_64
+ .type _nds32_vector_64, @function
+_nds32_vector_64:
+1:
+ j 1b
+ .size _nds32_vector_64, .-_nds32_vector_64
diff --git libgcc/config/nds32/isr-library/vec_vid64_4b.S libgcc/config/nds32/isr-library/vec_vid64_4b.S
new file mode 100644
index 0000000..fdfcbfd
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid64_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.64, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_64_4b
+ .type _nds32_vector_64_4b, @function
+_nds32_vector_64_4b:
+1:
+ j 1b
+ .size _nds32_vector_64_4b, .-_nds32_vector_64_4b
diff --git libgcc/config/nds32/isr-library/vec_vid65.S libgcc/config/nds32/isr-library/vec_vid65.S
new file mode 100644
index 0000000..a8b18f9
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid65.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.65, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_65
+ .type _nds32_vector_65, @function
+_nds32_vector_65:
+1:
+ j 1b
+ .size _nds32_vector_65, .-_nds32_vector_65
diff --git libgcc/config/nds32/isr-library/vec_vid65_4b.S libgcc/config/nds32/isr-library/vec_vid65_4b.S
new file mode 100644
index 0000000..5298dee
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid65_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.65, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_65_4b
+ .type _nds32_vector_65_4b, @function
+_nds32_vector_65_4b:
+1:
+ j 1b
+ .size _nds32_vector_65_4b, .-_nds32_vector_65_4b
diff --git libgcc/config/nds32/isr-library/vec_vid66.S libgcc/config/nds32/isr-library/vec_vid66.S
new file mode 100644
index 0000000..e0963dc
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid66.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.66, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_66
+ .type _nds32_vector_66, @function
+_nds32_vector_66:
+1:
+ j 1b
+ .size _nds32_vector_66, .-_nds32_vector_66
diff --git libgcc/config/nds32/isr-library/vec_vid66_4b.S libgcc/config/nds32/isr-library/vec_vid66_4b.S
new file mode 100644
index 0000000..9b47330
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid66_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.66, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_66_4b
+ .type _nds32_vector_66_4b, @function
+_nds32_vector_66_4b:
+1:
+ j 1b
+ .size _nds32_vector_66_4b, .-_nds32_vector_66_4b
diff --git libgcc/config/nds32/isr-library/vec_vid67.S libgcc/config/nds32/isr-library/vec_vid67.S
new file mode 100644
index 0000000..8113b70
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid67.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.67, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_67
+ .type _nds32_vector_67, @function
+_nds32_vector_67:
+1:
+ j 1b
+ .size _nds32_vector_67, .-_nds32_vector_67
diff --git libgcc/config/nds32/isr-library/vec_vid67_4b.S libgcc/config/nds32/isr-library/vec_vid67_4b.S
new file mode 100644
index 0000000..c03bbbe
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid67_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.67, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_67_4b
+ .type _nds32_vector_67_4b, @function
+_nds32_vector_67_4b:
+1:
+ j 1b
+ .size _nds32_vector_67_4b, .-_nds32_vector_67_4b
diff --git libgcc/config/nds32/isr-library/vec_vid68.S libgcc/config/nds32/isr-library/vec_vid68.S
new file mode 100644
index 0000000..c5414bf
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid68.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.68, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_68
+ .type _nds32_vector_68, @function
+_nds32_vector_68:
+1:
+ j 1b
+ .size _nds32_vector_68, .-_nds32_vector_68
diff --git libgcc/config/nds32/isr-library/vec_vid68_4b.S libgcc/config/nds32/isr-library/vec_vid68_4b.S
new file mode 100644
index 0000000..f383624
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid68_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.68, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_68_4b
+ .type _nds32_vector_68_4b, @function
+_nds32_vector_68_4b:
+1:
+ j 1b
+ .size _nds32_vector_68_4b, .-_nds32_vector_68_4b
diff --git libgcc/config/nds32/isr-library/vec_vid69.S libgcc/config/nds32/isr-library/vec_vid69.S
new file mode 100644
index 0000000..856a0ae
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid69.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.69, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_69
+ .type _nds32_vector_69, @function
+_nds32_vector_69:
+1:
+ j 1b
+ .size _nds32_vector_69, .-_nds32_vector_69
diff --git libgcc/config/nds32/isr-library/vec_vid69_4b.S libgcc/config/nds32/isr-library/vec_vid69_4b.S
new file mode 100644
index 0000000..8a73a38
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid69_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.69, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_69_4b
+ .type _nds32_vector_69_4b, @function
+_nds32_vector_69_4b:
+1:
+ j 1b
+ .size _nds32_vector_69_4b, .-_nds32_vector_69_4b
diff --git libgcc/config/nds32/isr-library/vec_vid70.S libgcc/config/nds32/isr-library/vec_vid70.S
new file mode 100644
index 0000000..d22bb5f
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid70.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.70, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_70
+ .type _nds32_vector_70, @function
+_nds32_vector_70:
+1:
+ j 1b
+ .size _nds32_vector_70, .-_nds32_vector_70
diff --git libgcc/config/nds32/isr-library/vec_vid70_4b.S libgcc/config/nds32/isr-library/vec_vid70_4b.S
new file mode 100644
index 0000000..520715c
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid70_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.70, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_70_4b
+ .type _nds32_vector_70_4b, @function
+_nds32_vector_70_4b:
+1:
+ j 1b
+ .size _nds32_vector_70_4b, .-_nds32_vector_70_4b
diff --git libgcc/config/nds32/isr-library/vec_vid71.S libgcc/config/nds32/isr-library/vec_vid71.S
new file mode 100644
index 0000000..1310d85
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid71.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.71, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_71
+ .type _nds32_vector_71, @function
+_nds32_vector_71:
+1:
+ j 1b
+ .size _nds32_vector_71, .-_nds32_vector_71
diff --git libgcc/config/nds32/isr-library/vec_vid71_4b.S libgcc/config/nds32/isr-library/vec_vid71_4b.S
new file mode 100644
index 0000000..0d09b59
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid71_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.71, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_71_4b
+ .type _nds32_vector_71_4b, @function
+_nds32_vector_71_4b:
+1:
+ j 1b
+ .size _nds32_vector_71_4b, .-_nds32_vector_71_4b
diff --git libgcc/config/nds32/isr-library/vec_vid72.S libgcc/config/nds32/isr-library/vec_vid72.S
new file mode 100644
index 0000000..2d4f563
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid72.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.72, "ax"
+ .vec_size 16
+ .align 4
+ .weak _nds32_vector_72
+ .type _nds32_vector_72, @function
+_nds32_vector_72:
+1:
+ j 1b
+ .size _nds32_vector_72, .-_nds32_vector_72
diff --git libgcc/config/nds32/isr-library/vec_vid72_4b.S libgcc/config/nds32/isr-library/vec_vid72_4b.S
new file mode 100644
index 0000000..88689fa
--- /dev/null
+++ libgcc/config/nds32/isr-library/vec_vid72_4b.S
@@ -0,0 +1,9 @@
+ .section .nds32_vector.72, "ax"
+ .vec_size 4
+ .align 2
+ .weak _nds32_vector_72_4b
+ .type _nds32_vector_72_4b, @function
+_nds32_vector_72_4b:
+1:
+ j 1b
+ .size _nds32_vector_72_4b, .-_nds32_vector_72_4b
diff --git libgcc/config/nds32/isr-library/wrh.S libgcc/config/nds32/isr-library/wrh.S
new file mode 100644
index 0000000..7cc8a9a
--- /dev/null
+++ libgcc/config/nds32/isr-library/wrh.S
@@ -0,0 +1,7 @@
+ .section .nds32_wrh, "a"
+ .align 2
+ .weak _nds32_wrh
+ .type _nds32_wrh, @object
+_nds32_wrh:
+ .word 0
+ .size _nds32_wrh, .-_nds32_wrh
diff --git libgcc/config/nds32/lib1asmsrc-mculib.S libgcc/config/nds32/lib1asmsrc-mculib.S
new file mode 100644
index 0000000..49ad26c
--- /dev/null
+++ libgcc/config/nds32/lib1asmsrc-mculib.S
@@ -0,0 +1,5223 @@
+/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
+ Copyright (C) 2012-2013 Free Software Foundation, Inc.
+ Contributed by Andes Technology Corporation.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+ .section .mdebug.abi_nds32
+ .previous
+
+
+/* ------------------------------------------- */
+/* FPBIT floating point operations for libgcc */
+/* ------------------------------------------- */
+
+#ifdef L_addsub_sf
+
+ .text
+ .align 1
+ .global __subsf3
+ .type __subsf3, @function
+__subsf3:
+ push $lp
+ pushm $r6, $r9
+
+ move $r2, #0x80000000
+ xor $r1, $r1, $r2
+
+ j .Lsfpadd
+
+ .global __addsf3
+ .type __addsf3, @function
+__addsf3:
+ push $lp
+ pushm $r6, $r9
+.Lsfpadd:
+ srli $r5, $r0, #23
+ andi $r5, $r5, #0xff
+ srli $r7, $r1, #23
+ andi $r7, $r7, #0xff
+ move $r3, #0x80000000
+ slli $r4, $r0, #8
+ or $r4, $r4, $r3
+ slli $r6, $r1, #8
+ or $r6, $r6, $r3
+
+ addi $r9, $r5, #-1
+ slti $r15, $r9, #0xfe
+ beqzs8 .LEspecA
+
+.LElab1:
+ addi $r9, $r7, #-1
+ slti $r15, $r9, #0xfe
+ beqzs8 .LEspecB
+
+.LElab2:
+ sub $r8, $r5, $r7
+ sltsi $r15, $r8, #0
+ bnezs8 .Li1
+ sltsi $r15, $r8, #0x20
+ bnezs8 .Li2
+ move $r6, #2
+ j .Le1
+.Li2:
+ move $r2, $r6
+ srl $r6, $r6, $r8
+ sll $r9, $r6, $r8
+ beq $r9, $r2, .Le1
+ ori $r6, $r6, #2
+ j .Le1
+.Li1:
+ move $r5, $r7
+ subri $r8, $r8, #0
+ sltsi $r15, $r8, #0x20
+ bnezs8 .Li4
+ move $r4, #2
+ j .Le1
+.Li4:
+ move $r2, $r4
+ srl $r4, $r4, $r8
+ sll $r9, $r4, $r8
+ beq $r9, $r2, .Le1
+ ori $r4, $r4, #2
+
+.Le1:
+ and $r8, $r0, $r3
+ xor $r9, $r8, $r1
+ sltsi $r15, $r9, #0
+ bnezs8 .LEsub1
+
+ #ADD($r4, $r6)
+ add $r4, $r4, $r6
+ slt $r15, $r4, $r6
+ beqzs8 .LEres
+ andi $r9, $r4, #1
+ beqz $r9, .Li7
+ ori $r4, $r4, #2
+.Li7:
+ srli $r4, $r4, #1
+ addi $r5, $r5, #1
+ subri $r15, $r5, #0xff
+ bnezs8 .LEres
+ move $r4, #0
+ j .LEres
+
+.LEsub1:
+ #SUB($r4, $r6)
+ move $r15, $r4
+ sub $r4, $r4, $r6
+ slt $r15, $r15, $r4
+ beqzs8 .Li9
+ subri $r4, $r4, #0
+ xor $r8, $r8, $r3
+ j .Le9
+.Li9:
+ beqz $r4, .LEzer
+.Le9:
+#ifdef __NDS32_PERF_EXT__
+ clz $r2, $r4
+#else
+ pushm $r0, $r1
+ pushm $r3, $r5
+ move $r0, $r4
+ bal __clzsi2
+ move $r2, $r0
+ popm $r3, $r5
+ popm $r0, $r1
+#endif
+ sub $r5, $r5, $r2
+ sll $r4, $r4, $r2
+
+.LEres:
+ blez $r5, .LEund
+
+.LElab12:
+ #ADD($r4, $0x80)
+ move $r15, #0x80
+ add $r4, $r4, $r15
+ slt $r15, $r4, $r15
+
+ #ADDC($r5, $0x0)
+ add $r5, $r5, $r15
+ srli $r9, $r4, #8
+ andi $r9, $r9, #1
+ sub $r4, $r4, $r9
+ slli $r4, $r4, #1
+ srli $r4, $r4, #9
+ slli $r9, $r5, #23
+ or $r4, $r4, $r9
+ or $r0, $r4, $r8
+
+.LE999:
+ popm $r6, $r9
+ pop $lp
+ ret5 $lp
+
+.LEund:
+ subri $r2, $r5, #1
+ slti $r15, $r2, #0x20
+ beqzs8 .LEzer
+ move $r9, #0x80000000
+ or $r4, $r4, $r9
+ subri $r9, $r2, #0x20
+ sll $r5, $r4, $r9
+ srl $r4, $r4, $r2
+ beqz $r5, .Li10
+ ori $r4, $r4, #1
+.Li10:
+ move $r5, #0
+ addi $r9, $r4, #0x80
+ sltsi $r15, $r9, #0
+ beqzs8 .LElab12
+ move $r5, #1
+ j .LElab12
+
+.LEspecA:
+ bnez $r5, .Li12
+ add $r4, $r4, $r4
+ beqz $r4, .Li13
+#ifdef __NDS32_PERF_EXT__
+ clz $r8, $r4
+#else
+ pushm $r0, $r5
+ move $r0, $r4
+ bal __clzsi2
+ move $r8, $r0
+ popm $r0, $r5
+#endif
+ sub $r5, $r5, $r8
+ sll $r4, $r4, $r8
+ j .LElab1
+.Li13:
+ subri $r15, $r7, #0xff
+ beqzs8 .LEspecB
+ move $r9, #0x80000000
+ bne $r1, $r9, .LEretB
+.Li12:
+ add $r9, $r4, $r4
+ bnez $r9, .LEnan
+ subri $r15, $r7, #0xff
+ bnezs8 .LEretA
+ xor $r9, $r0, $r1
+ sltsi $r15, $r9, #0
+ bnezs8 .LEnan
+ j .LEretB
+
+.LEspecB:
+ bnez $r7, .Li15
+ add $r6, $r6, $r6
+ beqz $r6, .LEretA
+#ifdef __NDS32_PERF_EXT__
+ clz $r8, $r6
+#else
+ pushm $r0, $r5
+ move $r0, $r6
+ bal __clzsi2
+ move $r8, $r0
+ popm $r0, $r5
+#endif
+ sub $r7, $r7, $r8
+ sll $r6, $r6, $r8
+ j .LElab2
+.Li15:
+ add $r9, $r6, $r6
+ bnez $r9, .LEnan
+
+.LEretB:
+ move $r0, $r1
+ j .LE999
+
+.LEretA:
+ j .LE999
+
+.LEzer:
+ move $r0, #0
+ j .LE999
+
+.LEnan:
+ move $r0, #0xffc00000
+ j .LE999
+ .size __subsf3, .-__subsf3
+ .size __addsf3, .-__addsf3
+#endif /* L_addsub_sf */
+
+
+
+#ifdef L_sf_to_si
+
+ .text
+ .align 1
+ .global __fixsfsi
+ .type __fixsfsi, @function
+__fixsfsi:
+ push $lp
+
+ slli $r1, $r0, #8
+ move $r3, #0x80000000
+ or $r1, $r1, $r3
+ srli $r3, $r0, #23
+ andi $r3, $r3, #0xff
+ subri $r2, $r3, #0x9e
+ blez $r2, .LJspec
+ sltsi $r15, $r2, #0x20
+ bnezs8 .Li42
+ move $r0, #0
+ j .LJ999
+.Li42:
+ srl $r1, $r1, $r2
+ sltsi $r15, $r0, #0
+ beqzs8 .Li43
+ subri $r1, $r1, #0
+.Li43:
+ move $r0, $r1
+
+.LJ999:
+ pop $lp
+ ret5 $lp
+
+.LJspec:
+ move $r3, #0x7f800000
+ slt $r15, $r3, $r0
+ beqzs8 .Li44
+ move $r0, #0x80000000
+ j .LJ999
+.Li44:
+ move $r0, #0x7fffffff
+ j .LJ999
+ .size __fixsfsi, .-__fixsfsi
+#endif /* L_sf_to_si */
+
+
+
+#ifdef L_divsi3
+
+ .text
+ .align 2
+ .globl __divsi3
+ .type __divsi3, @function
+__divsi3:
+ ! ---------------------------------------------------------------------
+ ! neg = 0;
+ ! if (a < 0)
+ ! { a = -a;
+ ! neg = !neg;
+ ! }
+ ! ---------------------------------------------------------------------
+ sltsi $r5, $r0, 0 ! $r5 <- neg = (a < 0) ? 1 : 0
+ subri $r4, $r0, 0 ! $r4 <- a = -a
+ cmovn $r0, $r4, $r5 ! $r0 <- a = neg ? -a : a
+.L2:
+ ! ---------------------------------------------------------------------
+ ! if (b < 0)
+ ! ---------------------------------------------------------------------
+ bgez $r1, .L3 ! if b >= 0, skip
+ ! ---------------------------------------------------------------------
+ ! { b=-b;
+ ! neg=!neg;
+ ! }
+ ! ---------------------------------------------------------------------
+ subri $r1, $r1, 0 ! $r1 <- b = -b
+ subri $r5, $r5, 1 ! $r5 <- neg = !neg
+.L3:
+ ! ---------------------------------------------------------------------
+ !!res = udivmodsi4 (a, b, 1);
+ ! res = 0;
+ ! if (den != 0)
+ ! ---------------------------------------------------------------------
+ movi $r2, 0 ! $r2 <- res = 0
+ beqz $r1, .L1 ! if den == 0, skip
+ ! ---------------------------------------------------------------------
+ ! bit = 1;
+ ! ---------------------------------------------------------------------
+ movi $r4, 1 ! $r4 <- bit = 1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+ ! ---------------------------------------------------------------------
+ ! while (den < num && bit && !(den & (1L << 31)))
+ ! ---------------------------------------------------------------------
+ slt $ta, $r1, $r0 ! $ta <- den < num ?
+ beqz $ta, .L5 ! if no, skip
+ ! ---------------------------------------------------------------------
+ ! { den << = 1;
+ ! bit << = 1;
+ ! }
+ ! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && !defined (__NDS32_ISA_V3M__)
+ clz $r3, $r1 ! $r3 <- leading zero count for den
+ clz $ta, $r0 ! $ta <- leading zero count for num
+ sub $r3, $r3, $ta ! $r3 <- number of bits to shift
+ sll $r1, $r1, $r3 ! $r1 <- den
+ sll $r4, $r4, $r3 ! $r2 <- bit
+#else
+ slli $r1, $r1, 1 ! $r1 <- den << = 1
+ slli $r4, $r4, 1 ! $r4 <- bit << = 1
+ b .L6 ! continue loop
+#endif
+.L5:
+ ! ---------------------------------------------------------------------
+ ! while (bit)
+ ! { if (num >= den)
+ ! ---------------------------------------------------------------------
+ slt $ta, $r0, $r1 ! $ta <- num < den ?
+ bnez $ta, .L9 ! if yes, skip
+ ! ---------------------------------------------------------------------
+ ! { num -= den;
+ ! res |= bit;
+ ! }
+ ! ---------------------------------------------------------------------
+ sub $r0, $r0, $r1 ! $r0 <- num -= den
+ or $r2, $r2, $r4 ! $r2 <- res |= bit
+.L9:
+ ! ---------------------------------------------------------------------
+ ! bit >> = 1;
+ ! den >> = 1;
+ ! }
+ !!if (modwanted)
+ !! return num;
+ !!return res;
+ ! ---------------------------------------------------------------------
+ srli $r4, $r4, 1 ! $r4 <- bit >> = 1
+ srli $r1, $r1, 1 ! $r1 <- den >> = 1
+ bnez $r4, .L5 ! if bit != 0, continue loop
+.L1:
+ ! ---------------------------------------------------------------------
+ ! if (neg)
+ ! res = -res;
+ ! return res;
+ ! ---------------------------------------------------------------------
+ subri $r0, $r2, 0 ! $r0 <- -res
+ cmovz $r0, $r2, $r5 ! $r0 <- neg ? -res : res
+ ! ---------------------------------------------------------------------
+ ret
+ .size __divsi3, .-__divsi3
+#endif /* L_divsi3 */
+
+
+
+#ifdef L_divdi3
+
+ !--------------------------------------
+ #ifdef __big_endian__
+ #define V1H $r0
+ #define V1L $r1
+ #define V2H $r2
+ #define V2L $r3
+ #else
+ #define V1H $r1
+ #define V1L $r0
+ #define V2H $r3
+ #define V2L $r2
+ #endif
+ !--------------------------------------
+ .text
+ .align 2
+ .globl __divdi3
+ .type __divdi3, @function
+__divdi3:
+ ! prologue
+#ifdef __NDS32_ISA_V3M__
+ push25 $r10, 0
+#else
+ smw.adm $r6, [$sp], $r10, 2
+#endif
+ ! end of prologue
+ move $r8, V1L
+ move $r9, V1H
+ move $r6, V2L
+ move $r7, V2H
+ movi $r10, 0
+ bgez V1H, .L80
+ bal __negdi2
+ move $r8, V1L
+ move $r9, V1H
+ movi $r10, -1
+.L80:
+ bgez $r7, .L81
+ move V1L, $r6
+ move V1H, $r7
+ bal __negdi2
+ move $r6, V1L
+ move $r7, V1H
+ nor $r10, $r10, $r10
+.L81:
+ move V2L, $r6
+ move V2H, $r7
+ move V1L, $r8
+ move V1H, $r9
+ movi $r4, 0
+ bal __udivmoddi4
+ beqz $r10, .L82
+ bal __negdi2
+.L82:
+ ! epilogue
+#ifdef __NDS32_ISA_V3M__
+ pop25 $r10, 0
+#else
+ lmw.bim $r6, [$sp], $r10, 2
+ ret
+#endif
+ .size __divdi3, .-__divdi3
+#endif /* L_divdi3 */
+
+
+
+#ifdef L_modsi3
+
+ .text
+ .align 2
+ .globl __modsi3
+ .type __modsi3, @function
+__modsi3:
+ ! ---------------------------------------------------------------------
+ ! neg=0;
+ ! if (a<0)
+ ! { a=-a;
+ ! neg=1;
+ ! }
+ ! ---------------------------------------------------------------------
+ sltsi $r5, $r0, 0 ! $r5 <- neg < 0 ? 1 : 0
+ subri $r4, $r0, 0 ! $r4 <- -a
+ cmovn $r0, $r4, $r5 ! $r0 <- |a|
+ ! ---------------------------------------------------------------------
+ ! if (b < 0)
+#ifndef __NDS32_PERF_EXT__
+ ! ---------------------------------------------------------------------
+ bgez $r1, .L3 ! if b >= 0, skip
+ ! ---------------------------------------------------------------------
+ ! b = -b;
+ ! ---------------------------------------------------------------------
+ subri $r1, $r1, 0 ! $r1 <- |b|
+.L3:
+ ! ---------------------------------------------------------------------
+ !!res = udivmodsi4 (a, b, 1);
+ ! if (den != 0)
+ ! ---------------------------------------------------------------------
+#else /* __NDS32_PERF_EXT__ */
+ ! b = -b;
+ !!res = udivmodsi4 (a, b, 1);
+ ! if (den != 0)
+ ! ---------------------------------------------------------------------
+ abs $r1, $r1 ! $r1 <- |b|
+#endif /* __NDS32_PERF_EXT__ */
+ beqz $r1, .L1 ! if den == 0, skip
+ ! ---------------------------------------------------------------------
+ ! { bit = 1;
+ ! res = 0;
+ ! ---------------------------------------------------------------------
+ movi $r4, 1 ! $r4 <- bit = 1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+ ! ---------------------------------------------------------------------
+ ! while (den < num&&bit && !(den & (1L << 31)))
+ ! ---------------------------------------------------------------------
+ slt $ta, $r1, $r0 ! $ta <- den < num ?
+ beqz $ta, .L5 ! if no, skip
+ ! ---------------------------------------------------------------------
+ ! { den << = 1;
+ ! bit << = 1;
+ ! }
+ ! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__)
+ clz $r3, $r1 ! $r3 <- leading zero count for den
+ clz $ta, $r0 ! $ta <- leading zero count for num
+ sub $r3, $r3, $ta ! $r3 <- number of bits to shift
+ sll $r1, $r1, $r3 ! $r1 <- den
+ sll $r4, $r4, $r3 ! $r2 <- bit
+#else
+ slli $r1, $r1, 1 ! $r1 <- den << = 1
+ slli $r4, $r4, 1 ! $r4 <- bit << = 1
+ b .L6 ! continue loop
+#endif
+.L5:
+ ! ---------------------------------------------------------------------
+ ! while (bit)
+ ! { if (num >= den)
+ ! { num -= den;
+ ! res |= bit;
+ ! }
+ ! bit >> = 1;
+ ! den >> = 1;
+ ! }
+ ! }
+ !!if (modwanted)
+ !! return num;
+ !!return res;
+ ! ---------------------------------------------------------------------
+ sub $r2, $r0, $r1 ! $r2 <- num - den
+ slt $ta, $r0, $r1 ! $ta <- num < den ?
+ srli $r4, $r4, 1 ! $r4 <- bit >> = 1
+ cmovz $r0, $r2, $ta ! $r0 <- num = (num < den) ? num : num - den
+ srli $r1, $r1, 1 ! $r1 <- den >> = 1
+ bnez $r4, .L5 ! if bit != 0, continue loop
+.L1:
+ ! ---------------------------------------------------------------------
+ ! if (neg)
+ ! res = -res;
+ ! return res;
+ ! ---------------------------------------------------------------------
+ subri $r3, $r0, 0 ! $r3 <- -res
+ cmovn $r0, $r3, $r5 ! $r0 <- neg ? -res : res
+ ! ---------------------------------------------------------------------
+ ret
+ .size __modsi3, .-__modsi3
+#endif /* L_modsi3 */
+
+
+
+#ifdef L_moddi3
+
+ !--------------------------------------
+ #ifdef __big_endian__
+ #define V1H $r0
+ #define V1L $r1
+ #define V2H $r2
+ #define V2L $r3
+ #else
+ #define V1H $r1
+ #define V1L $r0
+ #define V2H $r3
+ #define V2L $r2
+ #endif
+ !--------------------------------------
+ .text
+ .align 2
+ .globl __moddi3
+ .type __moddi3, @function
+__moddi3:
+ ! =====================================================================
+ ! stack allocation:
+ ! sp+32 +-----------------------+
+ ! | $lp |
+ ! sp+28 +-----------------------+
+ ! | $r6 - $r10 |
+ ! sp+8 +-----------------------+
+ ! | |
+ ! sp+4 +-----------------------+
+ ! | |
+ ! sp +-----------------------+
+ ! =====================================================================
+ ! prologue
+#ifdef __NDS32_ISA_V3M__
+ push25 $r10, 8
+#else
+ smw.adm $r6, [$sp], $r10, 2
+ addi $sp, $sp, -8
+#endif
+ ! end of prologue
+ !------------------------------------------
+ ! __moddi3 (DWtype u, DWtype v)
+ ! {
+ ! word_type c = 0;
+ ! DWunion uu = {.ll = u};
+ ! DWunion vv = {.ll = v};
+ ! DWtype w;
+ ! if (uu.s.high < 0)
+ ! c = ~c,
+ ! uu.ll = -uu.ll;
+ !---------------------------------------------
+ move $r8, V1L
+ move $r9, V1H
+ move $r6, V2L
+ move $r7, V2H
+ movi $r10, 0 ! r10 = c = 0
+ bgez V1H, .L80 ! if u > 0 , go L80
+ bal __negdi2
+ move $r8, V1L
+ move $r9, V1H
+ movi $r10, -1 ! r10 = c = ~c
+ !------------------------------------------------
+ ! if (vv.s.high < 0)
+ ! vv.ll = -vv.ll;
+ !----------------------------------------------
+.L80:
+ bgez $r7, .L81 ! if v > 0 , go L81
+ move V1L, $r6
+ move V1H, $r7
+ bal __negdi2
+ move $r6, V1L
+ move $r7, V1H
+ !------------------------------------------
+ ! (void) __udivmoddi4 (uu.ll, vv.ll, &w);
+ ! if (c)
+ ! w = -w;
+ ! return w;
+ !-----------------------------------------
+.L81:
+ move V2L, $r6
+ move V2H, $r7
+ move V1L, $r8
+ move V1H, $r9
+ addi $r4, $sp, 0
+ bal __udivmoddi4
+ lwi $r0, [$sp+(0)] ! le: sp + 0 is low, be: sp + 0 is high
+ lwi $r1, [$sp+(4)] ! le: sp + 4 is low, be: sp + 4 is high
+ beqz $r10, .L82
+ bal __negdi2
+.L82:
+ ! epilogue
+#ifdef __NDS32_ISA_V3M__
+ pop25 $r10, 8
+#else
+ addi $sp, $sp, 8
+ lmw.bim $r6, [$sp], $r10, 2
+ ret
+#endif
+ .size __moddi3, .-__moddi3
+#endif /* L_moddi3 */
+
+
+
+#ifdef L_mulsi3
+
+ .text
+ .align 2
+ .globl __mulsi3
+ .type __mulsi3, @function
+__mulsi3:
+ ! ---------------------------------------------------------------------
+ ! r = 0;
+ ! while (a)
+ ! $r0: r
+ ! $r1: b
+ ! $r2: a
+ ! ---------------------------------------------------------------------
+ beqz $r0, .L7 ! if a == 0, done
+ move $r2, $r0 ! $r2 <- a
+ movi $r0, 0 ! $r0 <- r <- 0
+.L8:
+ ! ---------------------------------------------------------------------
+ ! { if (a & 1)
+ ! r += b;
+ ! a >> = 1;
+ ! b << = 1;
+ ! }
+ ! $r0: r
+ ! $r1: b
+ ! $r2: a
+ ! $r3: scratch
+ ! $r4: scratch
+ ! ---------------------------------------------------------------------
+ andi $r3, $r2, 1 ! $r3 <- a & 1
+ add $r4, $r0, $r1 ! $r4 <- r += b
+ cmovn $r0, $r4, $r3 ! $r0 <- r
+ srli $r2, $r2, 1 ! $r2 <- a >> = 1
+ slli $r1, $r1, 1 ! $r1 <- b << = 1
+ bnez $r2, .L8 ! if a != 0, continue loop
+.L7:
+ ! ---------------------------------------------------------------------
+ ! $r0: return code
+ ! ---------------------------------------------------------------------
+ ret
+ .size __mulsi3, .-__mulsi3
+#endif /* L_mulsi3 */
+
+
+
+#ifdef L_udivsi3
+
+ .text
+ .align 2
+ .globl __udivsi3
+ .type __udivsi3, @function
+__udivsi3:
+ ! ---------------------------------------------------------------------
+ !!res=udivmodsi4(a,b,0);
+ ! res=0;
+ ! if (den!=0)
+ ! ---------------------------------------------------------------------
+ movi $r2, 0 ! $r2 <- res=0
+ beqz $r1, .L1 ! if den==0, skip
+ ! ---------------------------------------------------------------------
+ ! { bit=1;
+ ! ---------------------------------------------------------------------
+ movi $r4, 1 ! $r4 <- bit=1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+ ! ---------------------------------------------------------------------
+ ! while (den<num
+ ! ---------------------------------------------------------------------
+ slt $ta, $r1, $r0 ! $ta <- den<num?
+ beqz $ta, .L5 ! if no, skip
+ ! ---------------------------------------------------------------------
+ ! &&bit&&!(den&(1L<<31)))
+ ! ---------------------------------------------------------------------
+ bltz $r1, .L5 ! if den<0, skip
+ ! ---------------------------------------------------------------------
+ ! { den<<=1;
+ ! bit<<=1;
+ ! }
+ ! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__)
+ clz $r3, $r1 ! $r3 <- leading zero count for den
+ clz $ta, $r0 ! $ta <- leading zero count for num
+ sub $r3, $r3, $ta ! $r3 <- number of bits to shift
+ sll $r1, $r1, $r3 ! $r1 <- den
+ sll $r2, $r2, $r3 ! $r2 <- bit
+#else
+ slli $r1, $r1, 1 ! $r1 <- den<<=1
+ slli $r4, $r4, 1 ! $r4 <- bit<<=1
+ b .L6 ! continue loop
+#endif
+.L5:
+ ! ---------------------------------------------------------------------
+ ! while (bit)
+ ! { if (num>=den)
+ ! ---------------------------------------------------------------------
+ slt $ta, $r0, $r1 ! $ta <- num<den?
+ bnez $ta, .L9 ! if yes, skip
+ ! ---------------------------------------------------------------------
+ ! { num-=den;
+ ! res|=bit;
+ ! }
+ ! ---------------------------------------------------------------------
+ sub $r0, $r0, $r1 ! $r0 <- num-=den
+ or $r2, $r2, $r4 ! $r2 <- res|=bit
+.L9:
+ ! ---------------------------------------------------------------------
+ ! bit>>=1;
+ ! den>>=1;
+ ! }
+ ! }
+ !!if (modwanted)
+ !! return num;
+ !!return res;
+ ! ---------------------------------------------------------------------
+ srli $r4, $r4, 1 ! $r4 <- bit>>=1
+ srli $r1, $r1, 1 ! $r1 <- den>>=1
+ bnez $r4, .L5 ! if bit!=0, continue loop
+.L1:
+ ! ---------------------------------------------------------------------
+ ! return res;
+ ! ---------------------------------------------------------------------
+ move $r0, $r2 ! $r0 <- return value
+ ! ---------------------------------------------------------------------
+ ! ---------------------------------------------------------------------
+ ret
+ .size __udivsi3, .-__udivsi3
+#endif /* L_udivsi3 */
+
+
+
+#ifdef L_udivdi3
+
+ !--------------------------------------
+ #ifdef __big_endian__
+ #define V1H $r0
+ #define V1L $r1
+ #define V2H $r2
+ #define V2L $r3
+ #else
+ #define V1H $r1
+ #define V1L $r0
+ #define V2H $r3
+ #define V2L $r2
+ #endif
+ !--------------------------------------
+
+ .text
+ .align 2
+ .globl __udivdi3
+ .type __udivdi3, @function
+__udivdi3:
+ ! prologue
+#ifdef __NDS32_ISA_V3M__
+ push25 $r8, 0
+#else
+ smw.adm $r6, [$sp], $r8, 2
+#endif
+ ! end of prologue
+ movi $r4, 0
+ bal __udivmoddi4
+ ! epilogue
+#ifdef __NDS32_ISA_V3M__
+ pop25 $r8, 0
+#else
+ lmw.bim $r6, [$sp], $r8, 2
+ ret
+#endif
+ .size __udivdi3, .-__udivdi3
+#endif /* L_udivdi3 */
+
+
+
+#ifdef L_udivmoddi4
+
+ .text
+ .align 2
+ .globl fudiv_qrnnd
+ .type fudiv_qrnnd, @function
+ #ifdef __big_endian__
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+ #define W6H $r4
+ #define W6L $r5
+ #define OFFSET_L 4
+ #define OFFSET_H 0
+ #else
+ #define P1H $r1
+ #define P1L $r0
+ #define P2H $r3
+ #define P2L $r2
+ #define W6H $r5
+ #define W6L $r4
+ #define OFFSET_L 0
+ #define OFFSET_H 4
+ #endif
+fudiv_qrnnd:
+ !------------------------------------------------------
+ ! function: fudiv_qrnnd(quotient, remainder, high_numerator, low_numerator, denominator)
+ ! divides a UDWtype, composed by the UWtype integers,HIGH_NUMERATOR (from $r4)
+ ! and LOW_NUMERATOR(from $r5) by DENOMINATOR(from $r6), and places the quotient
+ ! in $r7 and the remainder in $r8.
+ !------------------------------------------------------
+ ! in reg:$r4(n1), $r5(n0), $r6(d0)
+ ! __d1 = ((USItype) (d) >> ((4 * 8) / 2));
+ ! __d0 = ((USItype) (d) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+ ! __r1 = (n1) % __d1;
+ ! __q1 = (n1) / __d1;
+ ! __m = (USItype) __q1 * __d0;
+ ! __r1 = __r1 * ((USItype) 1 << ((4 * 8) / 2)) | ((USItype) (n0) >> ((4 * 8) / 2));
+ ! if (__r1 < __m)
+ ! {
+ !------------------------------------------------------
+ smw.adm $r0, [$sp], $r4, 2 ! store $lp, when use BASELINE_V1,and must store $r0-$r3
+ srli $r7, $r6, 16 ! $r7 = d1 =__ll_highpart (d)
+ movi $ta, 65535
+ and $r8, $r6, $ta ! $r8 = d0 = __ll_lowpart (d)
+
+ divr $r9, $r10, $r4, $r7 ! $r9 = q1, $r10 = r1
+ and $r4, $r5, $ta ! $r4 = __ll_lowpart (n0)
+ slli $r10, $r10, 16 ! $r10 = r1 << 16
+ srli $ta, $r5, 16 ! $ta = __ll_highpart (n0)
+
+ or $r10, $r10, $ta ! $r10 <- $r0|$r3=__r1
+ mul $r5, $r9, $r8 ! $r5 = m = __q1*__d0
+ slt $ta, $r10, $r5 ! $ta <- __r1<__m
+ beqz $ta, .L2 !if yes,skip
+ !------------------------------------------------------
+ ! __q1--, __r1 += (d);
+ ! if (__r1 >= (d))
+ ! {
+ !------------------------------------------------------
+
+ add $r10, $r10, $r6 !$r10 <- __r1+d=__r1
+ addi $r9, $r9, -1 !$r9 <- __q1--=__q1
+ slt $ta, $r10, $r6 !$ta <- __r1<d
+ bnez $ta, .L2 !if yes,skip
+ !------------------------------------------------------
+ ! if (__r1 < __m)
+ ! {
+ !------------------------------------------------------
+
+ slt $ta, $r10, $r5 !$ta <- __r1<__m
+ beqz $ta, .L2 !if yes,skip
+ !------------------------------------------------------
+ ! __q1--, __r1 += (d);
+ ! }
+ ! }
+ ! }
+ !------------------------------------------------------
+
+ addi $r9, $r9, -1 !$r9 <- __q1--=__q1
+ add $r10, $r10, $r6 !$r2 <- __r1+d=__r1
+.L2:
+ !------------------------------------------------------
+ ! __r1 -= __m;
+ ! __r0 = __r1 % __d1;
+ ! __q0 = __r1 / __d1;
+ ! __m = (USItype) __q0 * __d0;
+ ! __r0 = __r0 * ((USItype) 1 << ((4 * 8) / 2)) \
+ ! | ((USItype) (n0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+ ! if (__r0 < __m)
+ ! {
+ !------------------------------------------------------
+ sub $r10, $r10, $r5 !$r10 <- __r1-__m=__r1
+ divr $r7, $r10, $r10, $r7 !$r7 <- r1/__d1=__q0,$r10 <- r1%__d1=__r0
+ slli $r10, $r10, 16 !$r10 <- __r0<<16
+ mul $r5, $r8, $r7 !$r5 <- __q0*__d0=__m
+ or $r10, $r4, $r10 !$r3 <- $r0|__ll_lowpart (n0) =__r0
+ slt $ta, $r10, $r5 !$ta <- __r0<__m
+ beqz $ta, .L5 !if yes,skip
+ !------------------------------------------------------
+ ! __q0--, __r0 += (d);
+ ! if (__r0 >= (d))
+ ! {
+ !------------------------------------------------------
+
+ add $r10, $r10, $r6 !$r10 <- __r0+d=__r0
+ addi $r7, $r7, -1 !$r7 <- __q0--=__q0
+ slt $ta, $r10, $r6 !$ta <- __r0<d
+ bnez $ta, .L5 !if yes,skip
+ !------------------------------------------------------
+ ! if (__r0 < __m)
+ ! {
+ !------------------------------------------------------
+
+ slt $ta, $r10, $r5 !$ta <- __r0<__m
+ beqz $ta, .L5 !if yes,skip
+ !------------------------------------------------------
+ ! __q0--, __r0 += (d);
+ ! }
+ ! }
+ ! }
+ !------------------------------------------------------
+
+ add $r10, $r10, $r6 !$r3 <- __r0+d=__r0
+ addi $r7, $r7, -1 !$r2 <- __q0--=__q0
+.L5:
+ !------------------------------------------------------
+ ! __r0 -= __m;
+ ! *q = (USItype) __q1 * ((USItype) 1 << ((4 * 8) / 2)) | __q0;
+ ! *r = __r0;
+ !}
+ !------------------------------------------------------
+
+ sub $r8, $r10, $r5 !$r8 = r = r0 = __r0-__m
+ slli $r9, $r9, 16 !$r9 <- __q1<<16
+ or $r7, $r9, $r7 !$r7 = q = $r9|__q0
+ lmw.bim $r0, [$sp], $r4, 2
+ ret
+ .size fudiv_qrnnd, .-fudiv_qrnnd
+
+ .align 2
+ .globl __udivmoddi4
+ .type __udivmoddi4, @function
+__udivmoddi4:
+ ! =====================================================================
+ ! stack allocation:
+ ! sp+40 +------------------+
+ ! | q1 |
+ ! sp+36 +------------------+
+ ! | q0 |
+ ! sp+32 +------------------+
+ ! | bm |
+ ! sp+28 +------------------+
+ ! | $lp |
+ ! sp+24 +------------------+
+ ! | $fp |
+ ! sp+20 +------------------+
+ ! | $r6 - $r10 |
+ ! sp +------------------+
+ ! =====================================================================
+
+ addi $sp, $sp, -40
+ smw.bi $r6, [$sp], $r10, 10
+ !------------------------------------------------------
+ ! d0 = dd.s.low;
+ ! d1 = dd.s.high;
+ ! n0 = nn.s.low;
+ ! n1 = nn.s.high;
+ ! if (d1 == 0)
+ ! {
+ !------------------------------------------------------
+
+ move $fp, $r4 !$fp <- rp
+ bnez P2H, .L9 !if yes,skip
+ !------------------------------------------------------
+ ! if (d0 > n1)
+ ! {
+ !------------------------------------------------------
+
+ slt $ta, P1H, P2L !$ta <- n1<d0
+ beqz $ta, .L10 !if yes,skip
+#ifndef __NDS32_PERF_EXT__
+ smw.adm $r0, [$sp], $r5, 0
+ move $r0, P2L
+ bal __clzsi2
+ move $r7, $r0
+ lmw.bim $r0, [$sp], $r5, 0
+#else
+ clz $r7, P2L
+#endif
+ swi $r7, [$sp+(28)]
+ beqz $r7, .L18 !if yes,skip
+ !------------------------------------------------------
+ ! d0 = d0 << bm;
+ ! n1 = (n1 << bm) | (n0 >> ((4 * 8) - bm));
+ ! n0 = n0 << bm;
+ ! }
+ !------------------------------------------------------
+
+ subri $r5, $r7, 32 !$r5 <- 32-bm
+ srl $r5, P1L, $r5 !$r5 <- n0>>$r5
+ sll $r6, P1H, $r7 !$r6 <- n1<<bm
+ or P1H, $r6, $r5 !P2h <- $r5|$r6=n1
+ sll P1L, P1L, $r7 !P1H <- n0<<bm=n0
+ sll P2L, P2L, $r7 !P2L <- d0<<bm=d0
+.L18:
+ !------------------------------------------------------
+ ! fudiv_qrnnd (&q0, &n0, n1, n0, d0);
+ ! q1 = 0;
+ ! } #if (d0 > n1)
+ !------------------------------------------------------
+
+ move $r4,P1H ! give fudiv_qrnnd args
+ move $r5,P1L !
+ move $r6,P2L !
+ bal fudiv_qrnnd !calcaulte q0 n0
+ movi $r6, 0 !P1L <- 0
+ swi $r7,[$sp+32] !q0
+ swi $r6,[$sp+36] !q1
+ move P1L,$r8 !n0
+ b .L19
+.L10:
+ !------------------------------------------------------
+ ! else #if (d0 > n1)
+ ! {
+ ! if(d0 == 0)
+ !------------------------------------------------------
+
+ bnez P2L, .L20 !if yes,skip
+ !------------------------------------------------------
+ ! d0 = 1 / d0;
+ !------------------------------------------------------
+
+ movi $r4, 1 !P1L <- 1
+ divr P2L, $r4, $r4, P2L !$r9=1/d0,P1L=1%d0
+.L20:
+
+#ifndef __NDS32_PERF_EXT__
+ smw.adm $r0, [$sp], $r5, 0
+ move $r0, P2L
+ bal __clzsi2
+ move $r7, $r0
+ lmw.bim $r0, [$sp], $r5, 0
+#else
+ clz $r7, P2L
+#endif
+ swi $r7,[$sp+(28)] ! store bm
+ beqz $r7, .L28 ! if yes,skip
+ !------------------------------------------------------
+ ! b = (4 * 8) - bm;
+ ! d0 = d0 << bm;
+ ! n2 = n1 >> b;
+ ! n1 = (n1 << bm) | (n0 >> b);
+ ! n0 = n0 << bm;
+ ! fudiv_qrnnd (&q1, &n1, n2, n1, d0);
+ ! }
+ !------------------------------------------------------
+
+ subri $r10, $r7, 32 !$r10 <- 32-bm=b
+ srl $r4, P1L, $r10 !$r4 <- n0>>b
+ sll $r5, P1H, $r7 !$r5 <- n1<<bm
+ or $r5, $r5, $r4 !$r5 <- $r5|$r4=n1 !for fun
+ sll P2L, P2L, $r7 !P2L <- d0<<bm=d0 !for fun
+ sll P1L, P1L, $r7 !P1L <- n0<<bm=n0
+ srl $r4, P1H, $r10 !$r4 <- n1>>b=n2 !for fun
+
+ move $r6,P2L !for fun
+ bal fudiv_qrnnd !caculate q1, n1
+
+ swi $r7,[$sp+(36)] ! q1 store
+ move P1H,$r8 ! n1 store
+
+ move $r4,$r8 ! prepare for next fudiv_qrnnd()
+ move $r5,P1L
+ move $r6,P2L
+ b .L29
+.L28:
+ !------------------------------------------------------
+ ! else // bm != 0
+ ! {
+ ! n1 -= d0;
+ ! q1 = 1;
+ !
+ !------------------------------------------------------
+
+ sub P1H, P1H, P2L !P1L <- n1-d0=n1
+ movi $ta, 1 !
+ swi $ta, [$sp+(36)] !1 -> [$sp+(36)]
+
+ move $r4,P1H ! give fudiv_qrnnd args
+ move $r5,P1L
+ move $r6,P2L
+.L29:
+ !------------------------------------------------------
+ ! fudiv_qrnnd (&q0, &n0, n1, n0, d0);
+ !------------------------------------------------------
+
+ bal fudiv_qrnnd !calcuate q0, n0
+ swi $r7,[$sp+(32)] !q0 store
+ move P1L,$r8 !n0
+.L19:
+ !------------------------------------------------------
+ ! if (rp != 0)
+ ! {
+ !------------------------------------------------------
+
+ beqz $fp, .L31 !if yes,skip
+ !------------------------------------------------------
+ ! rr.s.low = n0 >> bm;
+ ! rr.s.high = 0;
+ ! *rp = rr.ll;
+ ! }
+ !------------------------------------------------------
+
+ movi $r5, 0 !$r5 <- 0
+ lwi $r7,[$sp+(28)] !load bm
+ srl $r4, P1L, $r7 !$r4 <- n0>>bm
+ swi $r4, [$fp+OFFSET_L] !r0 !$r4 -> [$sp+(48)]
+ swi $r5, [$fp+OFFSET_H] !r1 !0 -> [$sp+(52)]
+ b .L31
+.L9:
+ !------------------------------------------------------
+ ! else # d1 == 0
+ ! {
+ ! if(d1 > n1)
+ ! {
+ !------------------------------------------------------
+
+ slt $ta, P1H, P2H !$ta <- n1<d1
+ beqz $ta, .L32 !if yes,skip
+ !------------------------------------------------------
+ ! q0 = 0;
+ ! q1 = 0;
+ ! if (rp != 0)
+ ! {
+ !------------------------------------------------------
+
+ movi $r5, 0 !$r5 <- 0
+ swi $r5, [$sp+(32)] !q0 !0 -> [$sp+(40)]=q1
+ swi $r5, [$sp+(36)] !q1 !0 -> [$sp+(32)]=q0
+ beqz $fp, .L31 !if yes,skip
+ !------------------------------------------------------
+ ! rr.s.low = n0;
+ ! rr.s.high = n1;
+ ! *rp = rr.ll;
+ ! }
+ !------------------------------------------------------
+
+ swi P1L, [$fp+OFFSET_L] !P1L -> [rp]
+ swi P1H, [$fp+OFFSET_H] !P1H -> [rp+4]
+ b .L31
+.L32:
+#ifndef __NDS32_PERF_EXT__
+ smw.adm $r0, [$sp], $r5, 0
+ move $r0, P2H
+ bal __clzsi2
+ move $r7, $r0
+ lmw.bim $r0, [$sp], $r5, 0
+#else
+ clz $r7,P2H
+#endif
+ swi $r7,[$sp+(28)] !$r7=bm store
+ beqz $r7, .L42 !if yes,skip
+ !------------------------------------------------------
+ ! USItype m1, m0;
+ ! b = (4 * 8) - bm;
+ ! d1 = (d0 >> b) | (d1 << bm);
+ ! d0 = d0 << bm;
+ ! n2 = n1 >> b;
+ ! n1 = (n0 >> b) | (n1 << bm);
+ ! n0 = n0 << bm;
+ ! fudiv_qrnnd (&q0, &n1, n2, n1, d1);
+ !------------------------------------------------------
+
+ subri $r10, $r7, 32 !$r10 <- 32-bm=b
+ srl $r5, P2L, $r10 !$r5 <- d0>>b
+ sll $r6, P2H, $r7 !$r6 <- d1<<bm
+ or $r6, $r5, $r6 !$r6 <- $r5|$r6=d1 !! func
+ move P2H, $r6 !P2H <- d1
+ srl $r4, P1H, $r10 !$r4 <- n1>>b=n2 !!! func
+ srl $r8, P1L, $r10 !$r8 <- n0>>b !!$r8
+ sll $r9, P1H, $r7 !$r9 <- n1<<bm
+ or $r5, $r8, $r9 !$r5 <- $r8|$r9=n1 !func
+ sll P2L, P2L, $r7 !P2L <- d0<<bm=d0
+ sll P1L, P1L, $r7 !P1L <- n0<<bm=n0
+
+ bal fudiv_qrnnd ! cal q0,n1
+ swi $r7,[$sp+(32)]
+ move P1H,$r8 ! fudiv_qrnnd (&q0, &n1, n2, n1, d1);
+ move $r6, $r7 ! from func
+
+ !----------------------------------------------------
+ ! #umul_ppmm (m1, m0, q0, d0);
+ ! do
+ ! { USItype __x0, __x1, __x2, __x3;
+ ! USItype __ul, __vl, __uh, __vh;
+ ! __ul = ((USItype) (q0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+ ! __uh = ((USItype) (q0) >> ((4 * 8) / 2));
+ ! __vl = ((USItype) (d0) & (((USItype) 1 << ((4 * 8) / 2)) - 1));
+ ! __vh = ((USItype) (d0) >> ((4 * 8) / 2));
+ ! __x0 = (USItype) __ul * __vl;
+ ! __x1 = (USItype) __ul * __vh;
+ ! __x2 = (USItype) __uh * __vl;
+ ! __x3 = (USItype) __uh * __vh;
+ ! __x1 += ((USItype) (__x0) >> ((4 * 8) / 2));
+ ! __x1 += __x2;
+ ! if (__x1 < __x2)
+ ! __x3 += ((USItype) 1 << ((4 * 8) / 2));
+ ! (m1) = __x3 + ((USItype) (__x1) >> ((4 * 8) / 2));
+ ! (m0) = (USItype)(q0*d0);
+ ! }
+ ! if (m1 > n1)
+ !---------------------------------------------------
+#ifdef __NDS32_ISA_V3M__
+ !mulr64 $r4, P2L, $r6
+ smw.adm $r0, [$sp], $r3, 0
+ move P1L, P2L
+ move P2L, $r6
+ movi P1H, 0
+ movi P2H, 0
+ bal __muldi3
+ movd44 $r4, $r0
+ lmw.bim $r0, [$sp], $r3, 0
+ move $r8, W6H
+ move $r5, W6L
+#else
+ mulr64 $r4, P2L, $r6
+ move $r8, W6H
+ move $r5, W6L
+#endif
+ slt $ta, P1H, $r8 !$ta <- n1<m1
+ bnez $ta, .L46 !if yes,skip
+ !------------------------------------------------------
+ ! if(m1 == n1)
+ !------------------------------------------------------
+
+ bne $r8, P1H, .L45 !if yes,skip
+ !------------------------------------------------------
+ ! if(m0 > n0)
+ !------------------------------------------------------
+
+ slt $ta, P1L, $r5 !$ta <- n0<m0
+ beqz $ta, .L45 !if yes,skip
+.L46:
+ !------------------------------------------------------
+ ! {
+ ! q0--;
+ ! # sub_ddmmss (m1, m0, m1, m0, d1, d0);
+ ! do
+ ! { USItype __x;
+ ! __x = (m0) - (d0);
+ ! (m1) = (m1) - (d1) - (__x > (m0));
+ ! (m0) = __x;
+ ! }
+ ! }
+ !------------------------------------------------------
+
+ sub $r4, $r5, P2L !$r4 <- m0-d0=__x
+ addi $r6, $r6, -1 !$r6 <- q0--=q0
+ sub $r8, $r8, P2H !$r8 <- m1-d1
+ swi $r6, [$sp+(32)] ! q0 !$r6->[$sp+(32)]
+ slt $ta, $r5, $r4 !$ta <- m0<__x
+ sub $r8, $r8, $ta !$r8 <- P1H-P1L=m1
+ move $r5, $r4 !$r5 <- __x=m0
+.L45:
+ !------------------------------------------------------
+ ! q1 = 0;
+ ! if (rp != 0)
+ ! {
+ !------------------------------------------------------
+
+ movi $r4, 0 !$r4 <- 0
+ swi $r4, [$sp+(36)] !0 -> [$sp+(40)]=q1
+ beqz $fp, .L31 !if yes,skip
+ !------------------------------------------------------
+ ! # sub_ddmmss (n1, n0, n1, n0, m1, m0);
+ ! do
+ ! { USItype __x;
+ ! __x = (n0) - (m0);
+ ! (n1) = (n1) - (m1) - (__x > (n0));
+ ! (n0) = __x;
+ ! }
+ ! rr.s.low = (n1 << b) | (n0 >> bm);
+ ! rr.s.high = n1 >> bm;
+ ! *rp = rr.ll;
+ !------------------------------------------------------
+
+ sub $r4, P1H, $r8 !$r4 <- n1-m1
+ sub $r6, P1L, $r5 !$r6 <- n0-m0=__x=n0
+ slt $ta, P1L, $r6 !$ta <- n0<__x
+ sub P1H, $r4, $ta !P1H <- $r4-$ta=n1
+ move P1L, $r6
+
+ lwi $r7,[$sp+(28)] ! load bm
+ subri $r10,$r7,32
+ sll $r4, P1H, $r10 !$r4 <- n1<<b
+ srl $r5, P1L, $r7 !$r5 <- __x>>bm
+ or $r6, $r5, $r4 !$r6 <- $r5|$r4=rr.s.low
+ srl $r8, P1H, $r7 !$r8 <- n1>>bm =rr.s.high
+ swi $r6, [$fp+OFFSET_L] !
+ swi $r8, [$fp+OFFSET_H] !
+ b .L31
+.L42:
+ !------------------------------------------------------
+ ! else
+ ! {
+ ! if(n1 > d1)
+ !------------------------------------------------------
+
+ slt $ta, P2H, P1H !$ta <- P2H<P1H
+ bnez $ta, .L52 !if yes,skip
+ !------------------------------------------------------
+ ! if (n0 >= d0)
+ !------------------------------------------------------
+
+ slt $ta, P1L, P2L !$ta <- P1L<P2L
+ bnez $ta, .L51 !if yes,skip
+ !------------------------------------------------------
+ ! q0 = 1;
+ ! do
+ ! { USItype __x;
+ ! __x = (n0) - (d0);
+ ! (n1) = (n1) - (d1) - (__x > (n0));
+ ! (n0) = __x;
+ ! }
+ !------------------------------------------------------
+.L52:
+ sub $r4, P1H, P2H !$r4 <- P1H-P2H
+ sub $r6, P1L, P2L !$r6 <- no-d0=__x=n0
+ slt $ta, P1L, $r6 !$ta <- no<__x
+ sub P1H, $r4, $ta !P1H <- $r4-$ta=n1
+ move P1L, $r6 !n0
+ movi $r5, 1 !
+ swi $r5, [$sp+(32)] !1 -> [$sp+(32)]=q0
+ b .L54
+.L51:
+ !------------------------------------------------------
+ ! q0 = 0;
+ !------------------------------------------------------
+
+ movi $r5,0
+ swi $r5, [$sp+(32)] !$r5=0 -> [$sp+(32)]
+.L54:
+ !------------------------------------------------------
+ ! q1 = 0;
+ ! if (rp != 0)
+ ! {
+ !------------------------------------------------------
+
+ movi $r5, 0 !
+ swi $r5, [$sp+(36)] !0 -> [$sp+(36)]
+ beqz $fp, .L31
+ !------------------------------------------------------
+ ! rr.s.low = n0;
+ ! rr.s.high = n1;
+ ! *rp = rr.ll;
+ ! }
+ !------------------------------------------------------
+
+ swi P1L, [$fp+OFFSET_L] !remainder
+ swi P1H, [$fp+OFFSET_H] !
+.L31:
+ !------------------------------------------------------
+ ! const DWunion ww = {{.low = q0, .high = q1}};
+ ! return ww.ll;
+ !}
+ !------------------------------------------------------
+
+ lwi P1L, [$sp+(32)] !quotient
+ lwi P1H, [$sp+(36)]
+ lmw.bim $r6, [$sp], $r10, 10
+ addi $sp, $sp, 12
+ ret
+ .size __udivmoddi4, .-__udivmoddi4
+#endif /* L_udivmoddi4 */
+
+
+
+#ifdef L_umodsi3
+
+ ! =====================================================================
+ .text
+ .align 2
+ .globl __umodsi3
+ .type __umodsi3, @function
+__umodsi3:
+ ! ---------------------------------------------------------------------
+ !!res=udivmodsi4(a,b,1);
+ ! if (den==0)
+ ! return num;
+ ! ---------------------------------------------------------------------
+ beqz $r1, .L1 ! if den==0, skip
+ ! ---------------------------------------------------------------------
+ ! bit=1;
+ ! res=0;
+ ! ---------------------------------------------------------------------
+ movi $r4, 1 ! $r4 <- bit=1
+#ifndef __OPTIMIZE_SIZE__
+.L6:
+#endif
+ ! ---------------------------------------------------------------------
+ ! while (den<num
+ ! ---------------------------------------------------------------------
+ slt $ta, $r1, $r0 ! $ta <- den<num?
+ beqz $ta, .L5 ! if no, skip
+ ! ---------------------------------------------------------------------
+ ! &&bit&&!(den&(1L<<31)))
+ ! ---------------------------------------------------------------------
+ bltz $r1, .L5 ! if den<0, skip
+ ! ---------------------------------------------------------------------
+ ! { den<<=1;
+ ! bit<<=1;
+ ! }
+ ! ---------------------------------------------------------------------
+#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__)
+ clz $r3, $r1 ! $r3 <- leading zero count for den
+ clz $ta, $r0 ! $ta <- leading zero count for num
+ sub $r3, $r3, $ta ! $r3 <- number of bits to shift
+ sll $r1, $r1, $r3 ! $r1 <- den
+ sll $r4, $r4, $r3 ! $r2 <- bit
+#else
+ slli $r1, $r1, 1 ! $r1 <- den<<=1
+ slli $r4, $r4, 1 ! $r4 <- bit<<=1
+ b .L6 ! continue loop
+#endif
+.L5:
+ ! ---------------------------------------------------------------------
+ ! while (bit)
+ ! { if (num>=den)
+ ! { num-=den;
+ ! res|=bit;
+ ! }
+ ! bit>>=1;
+ ! den>>=1;
+ ! }
+ !!if (modwanted)
+ !! return num;
+ !!return res;
+ ! ---------------------------------------------------------------------
+ sub $r2, $r0, $r1 ! $r2 <- num-den
+ slt $ta, $r0, $r1 ! $ta <- num<den?
+ srli $r4, $r4, 1 ! $r4 <- bit>>=1
+ cmovz $r0, $r2, $ta ! $r0 <- num=(num<den)?num:num-den
+ srli $r1, $r1, 1 ! $r1 <- den>>=1
+ bnez $r4, .L5 ! if bit!=0, continue loop
+.L1:
+ ! ---------------------------------------------------------------------
+ ! return res;
+ ! ---------------------------------------------------------------------
+ ret
+ .size __umodsi3, .-__umodsi3
+#endif /* L_umodsi3 */
+
+
+
+#ifdef L_umoddi3
+
+ !--------------------------------------
+ #ifdef __big_endian__
+ #define V1H $r0
+ #define V1L $r1
+ #define V2H $r2
+ #define V2L $r3
+ #else
+ #define V1H $r1
+ #define V1L $r0
+ #define V2H $r3
+ #define V2L $r2
+ #endif
+ !--------------------------------------
+ .text
+ .align 2
+ .globl __umoddi3
+ .type __umoddi3, @function
+__umoddi3:
+ ! prologue
+ addi $sp, $sp, -12
+ swi $lp, [$sp+(0)]
+ ! end of prologue
+ addi $r4, $sp, 4
+ bal __udivmoddi4
+ lwi $r0, [$sp+(4)] ! __udivmoddi4 return low when LE mode or return high when BE mode
+ lwi $r1, [$sp+(8)] !
+.L82:
+ ! epilogue
+ lwi $lp, [$sp+(0)]
+ addi $sp, $sp, 12
+ ret
+ .size __umoddi3, .-__umoddi3
+#endif /* L_umoddi3 */
+
+
+
+#ifdef __NDS32_ISA_V3M__
+#else /* not __NDS32_ISA_V3M__ */
+#ifdef L_mcu_muldi3
+ ! ====================================================================
+ .text
+ .align 2
+ .globl __muldi3
+ .type __muldi3, @function
+__muldi3:
+ ! parameter passing for libgcc functions normally involves 2 doubles
+ !---------------------------------------
+ #ifdef __big_endian__
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+
+ #define V2H $r4
+ #define V2L $r5
+ #else
+ #define P1H $r1
+ #define P1L $r0
+ #define P2H $r3
+ #define P2L $r2
+
+ #define V2H $r5
+ #define V2L $r4
+ #endif
+ mul $ta, P1L, P2H
+ mulr64 $r4, P1L, P2L
+ maddr32 $ta, P1H, P2L
+ move P1L, V2L
+ add P1H, $ta, V2H
+ ret
+ .size __muldi3, .-__muldi3
+#endif /* L_mcu_muldi3 */
+#endif /* not __NDS32_ISA_V3M__ */
+
+
+
+#ifdef L_addsub_df
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+ #define P3L $r4
+ #define P3H $r5
+ #define O1L $r7
+ #define O1H $r8
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+ #define P3H $r4
+ #define P3L $r5
+ #define O1H $r7
+ #define O1L $r8
+#endif
+ .text
+ .align 1
+ .global __subdf3
+ .type __subdf3, @function
+__subdf3:
+ push $lp
+ pushm $r6, $r10
+
+ move $r4, #0x80000000
+ xor P2H, P2H, $r4
+
+ j .Lsdpadd
+
+ .global __adddf3
+ .type __adddf3, @function
+__adddf3:
+ push $lp
+ pushm $r6, $r10
+.Lsdpadd:
+ slli $r6, P1H, #1
+ srli $r6, $r6, #21
+ slli P3H, P1H, #11
+ srli $r10, P1L, #21
+ or P3H, P3H, $r10
+ slli P3L, P1L, #11
+ move O1L, #0x80000000
+ or P3H, P3H, O1L
+ slli $r9, P2H, #1
+ srli $r9, $r9, #21
+ slli O1H, P2H, #11
+ srli $r10, P2L, #21
+ or O1H, O1H, $r10
+ or O1H, O1H, O1L
+ slli O1L, P2L, #11
+
+ addi $r10, $r6, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LEspecA
+
+.LElab1:
+ addi $r10, $r9, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LEspecB
+
+.LElab2:
+ #NORMd($r4, P2L, P1L)
+ bnez P3H, .LL1
+ bnez P3L, .LL2
+ move $r6, #0
+ j .LL3
+.LL2:
+ move P3H, P3L
+ move P3L, #0
+ move P2L, #32
+ sub $r6, $r6, P2L
+.LL1:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r2, $r5
+#else
+ pushm $r0, $r1
+ pushm $r3, $r5
+ move $r0, $r5
+ bal __clzsi2
+ move $r2, $r0
+ popm $r3, $r5
+ popm $r0, $r1
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r3, $r4
+#else
+ pushm $r0, $r2
+ pushm $r4, $r5
+ move $r0, $r4
+ bal __clzsi2
+ move $r3, $r0
+ popm $r4, $r5
+ popm $r0, $r2
+#endif
+#endif /* __big_endian__ */
+ beqz P2L, .LL3
+ sub $r6, $r6, P2L
+ subri P1L, P2L, #32
+ srl P1L, P3L, P1L
+ sll P3L, P3L, P2L
+ sll P3H, P3H, P2L
+ or P3H, P3H, P1L
+.LL3:
+ #NORMd End
+
+ #NORMd($r7, P2L, P1L)
+ bnez O1H, .LL4
+ bnez O1L, .LL5
+ move $r9, #0
+ j .LL6
+.LL5:
+ move O1H, O1L
+ move O1L, #0
+ move P2L, #32
+ sub $r9, $r9, P2L
+.LL4:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r2, O1H
+#else
+ pushm $r0, $r1
+ pushm $r3, $r5
+ move $r0, O1H
+ bal __clzsi2
+ move $r2, $r0
+ popm $r3, $r5
+ popm $r0, $r1
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r3, O1H
+#else
+ pushm $r0, $r2
+ pushm $r4, $r5
+ move $r0, O1H
+ bal __clzsi2
+ move $r3, $r0
+ popm $r4, $r5
+ popm $r0, $r2
+#endif
+#endif /* __big_endian__ */
+ beqz P2L, .LL6
+ sub $r9, $r9, P2L
+ subri P1L, P2L, #32
+ srl P1L, O1L, P1L
+ sll O1L, O1L, P2L
+ sll O1H, O1H, P2L
+ or O1H, O1H, P1L
+.LL6:
+ #NORMd End
+
+ move $r10, #0x80000000
+ and P1H, P1H, $r10
+
+ beq $r6, $r9, .LEadd3
+ slts $r15, $r9, $r6
+ beqzs8 .Li1
+ sub $r9, $r6, $r9
+ move P2L, #0
+.LL7:
+ move $r10, #0x20
+ slt $r15, $r9, $r10
+ bnezs8 .LL8
+ or P2L, P2L, O1L
+ move O1L, O1H
+ move O1H, #0
+ addi $r9, $r9, #0xffffffe0
+ bnez O1L, .LL7
+.LL8:
+ beqz $r9, .LEadd3
+ move P1L, O1H
+ move $r10, O1L
+ srl O1L, O1L, $r9
+ srl O1H, O1H, $r9
+ subri $r9, $r9, #0x20
+ sll P1L, P1L, $r9
+ or O1L, O1L, P1L
+ sll $r10, $r10, $r9
+ or P2L, P2L, $r10
+ beqz P2L, .LEadd3
+ ori O1L, O1L, #1
+ j .LEadd3
+.Li1:
+ move $r15, $r6
+ move $r6, $r9
+ sub $r9, $r9, $r15
+ move P2L, #0
+.LL10:
+ move $r10, #0x20
+ slt $r15, $r9, $r10
+ bnezs8 .LL11
+ or P2L, P2L, P3L
+ move P3L, P3H
+ move P3H, #0
+ addi $r9, $r9, #0xffffffe0
+ bnez P3L, .LL10
+.LL11:
+ beqz $r9, .LEadd3
+ move P1L, P3H
+ move $r10, P3L
+ srl P3L, P3L, $r9
+ srl P3H, P3H, $r9
+ subri $r9, $r9, #0x20
+ sll P1L, P1L, $r9
+ or P3L, P3L, P1L
+ sll $r10, $r10, $r9
+ or P2L, P2L, $r10
+ beqz P2L, .LEadd3
+ ori P3L, P3L, #1
+
+.LEadd3:
+ xor $r10, P1H, P2H
+ sltsi $r15, $r10, #0
+ bnezs8 .LEsub1
+
+ #ADD(P3L, O1L)
+ add P3L, P3L, O1L
+ slt $r15, P3L, O1L
+
+ #ADDCC(P3H, O1H)
+ beqzs8 .LL13
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .LL14
+ addi P3H, P3H, #0x1
+ j .LL15
+.LL14:
+ move $r15, #1
+ add P3H, P3H, $r15
+ slt $r15, P3H, $r15
+ j .LL15
+.LL13:
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+.LL15:
+
+ beqzs8 .LEres
+ andi $r10, P3L, #1
+ beqz $r10, .Li3
+ ori P3L, P3L, #2
+.Li3:
+ srli P3L, P3L, #1
+ slli $r10, P3H, #31
+ or P3L, P3L, $r10
+ srli P3H, P3H, #1
+ move $r10, #0x80000000
+ or P3H, P3H, $r10
+ addi $r6, $r6, #1
+ subri $r15, $r6, #0x7ff
+ bnezs8 .LEres
+ move $r10, #0x7ff00000
+ or P1H, P1H, $r10
+ move P1L, #0
+ j .LEretA
+
+.LEsub1:
+ #SUB(P3L, O1L)
+ move $r15, P3L
+ sub P3L, P3L, O1L
+ slt $r15, $r15, P3L
+
+ #SUBCC(P3H, O1H)
+ beqzs8 .LL16
+ move $r15, P3H
+ sub P3H, P3H, O1H
+ slt $r15, $r15, P3H
+ beqzs8 .LL17
+ subi333 P3H, P3H, #1
+ j .LL18
+.LL17:
+ move $r15, P3H
+ subi333 P3H, P3H, #1
+ slt $r15, $r15, P3H
+ j .LL18
+.LL16:
+ move $r15, P3H
+ sub P3H, P3H, O1H
+ slt $r15, $r15, P3H
+.LL18:
+
+ beqzs8 .Li5
+ move $r10, #0x80000000
+ xor P1H, P1H, $r10
+
+ subri P3H, P3H, #0
+ beqz P3L, .LL19
+ subri P3L, P3L, #0
+ subi45 P3H, #1
+.LL19:
+
+.Li5:
+ #NORMd($r4, $r9, P1L)
+ bnez P3H, .LL20
+ bnez P3L, .LL21
+ move $r6, #0
+ j .LL22
+.LL21:
+ move P3H, P3L
+ move P3L, #0
+ move $r9, #32
+ sub $r6, $r6, $r9
+.LL20:
+#ifdef __NDS32_PERF_EXT__
+ clz $r9, P3H
+#else
+ pushm $r0, $r5
+ move $r0, P3H
+ bal __clzsi2
+ move $r9, $r0
+ popm $r0, $r5
+#endif
+ beqz $r9, .LL22
+ sub $r6, $r6, $r9
+ subri P1L, $r9, #32
+ srl P1L, P3L, P1L
+ sll P3L, P3L, $r9
+ sll P3H, P3H, $r9
+ or P3H, P3H, P1L
+.LL22:
+ #NORMd End
+
+ or $r10, P3H, P3L
+ bnez $r10, .LEres
+ move P1H, #0
+
+.LEres:
+ blez $r6, .LEund
+
+.LElab8:
+ #ADD(P3L, $0x400)
+ move $r15, #0x400
+ add P3L, P3L, $r15
+ slt $r15, P3L, $r15
+
+ #ADDCC(P3H, $0x0)
+ beqzs8 .LL25
+ add P3H, P3H, $r15
+ slt $r15, P3H, $r15
+.LL25:
+
+ #ADDC($r6, $0x0)
+ add $r6, $r6, $r15
+ srli $r10, P3L, #11
+ andi $r10, $r10, #1
+ sub P3L, P3L, $r10
+ srli P1L, P3L, #11
+ slli $r10, P3H, #21
+ or P1L, P1L, $r10
+ slli $r10, P3H, #1
+ srli $r10, $r10, #12
+ or P1H, P1H, $r10
+ slli $r10, $r6, #20
+ or P1H, P1H, $r10
+
+.LEretA:
+.LE999:
+ popm $r6, $r10
+ pop $lp
+ ret5 $lp
+
+.LEspecA:
+ #ADD(P3L, P3L)
+ move $r15, P3L
+ add P3L, P3L, P3L
+ slt $r15, P3L, $r15
+
+ #ADDC(P3H, P3H)
+ add P3H, P3H, P3H
+ add P3H, P3H, $r15
+ bnez $r6, .Li7
+ or $r10, P3H, P3L
+ beqz $r10, .Li8
+ j .LElab1
+.Li8:
+ subri $r15, $r9, #0x7ff
+ beqzs8 .LEspecB
+ add P3L, P2H, P2H
+ or $r10, P3L, P2L
+ bnez $r10, .LEretB
+ sltsi $r15, P2H, #0
+ bnezs8 .LEretA
+
+.LEretB:
+ move P1L, P2L
+ move P1H, P2H
+ j .LE999
+.Li7:
+ or $r10, P3H, P3L
+ bnez $r10, .LEnan
+ subri $r15, $r9, #0x7ff
+ bnezs8 .LEretA
+ xor $r10, P1H, P2H
+ sltsi $r15, $r10, #0
+ bnezs8 .LEnan
+ j .LEretB
+
+.LEspecB:
+ #ADD(O1L, O1L)
+ move $r15, O1L
+ add O1L, O1L, O1L
+ slt $r15, O1L, $r15
+
+ #ADDC(O1H, O1H)
+ add O1H, O1H, O1H
+ add O1H, O1H, $r15
+ bnez $r9, .Li11
+ or $r10, O1H, O1L
+ beqz $r10, .LEretA
+ j .LElab2
+.Li11:
+ or $r10, O1H, O1L
+ beqz $r10, .LEretB
+
+.LEnan:
+ move P1H, #0xfff80000
+ move P1L, #0
+ j .LEretA
+
+.LEund:
+ subri $r9, $r6, #1
+ move P2L, #0
+.LL26:
+ move $r10, #0x20
+ slt $r15, $r9, $r10
+ bnezs8 .LL27
+ or P2L, P2L, P3L
+ move P3L, P3H
+ move P3H, #0
+ addi $r9, $r9, #0xffffffe0
+ bnez P3L, .LL26
+.LL27:
+ beqz $r9, .LL28
+ move P1L, P3H
+ move $r10, P3L
+ srl P3L, P3L, $r9
+ srl P3H, P3H, $r9
+ subri $r9, $r9, #0x20
+ sll P1L, P1L, $r9
+ or P3L, P3L, P1L
+ sll $r10, $r10, $r9
+ or P2L, P2L, $r10
+ beqz P2L, .LL28
+ ori P3L, P3L, #1
+.LL28:
+ move $r6, #0
+ j .LElab8
+ .size __subdf3, .-__subdf3
+ .size __adddf3, .-__adddf3
+#endif /* L_addsub_df */
+
+
+
+#ifdef L_mul_sf
+
+#if !defined (__big_endian__)
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+#endif
+ .text
+ .align 1
+ .global __mulsf3
+ .type __mulsf3, @function
+__mulsf3:
+ push $lp
+ pushm $r6, $r10
+
+ srli $r3, $r0, #23
+ andi $r3, $r3, #0xff
+ srli $r5, $r1, #23
+ andi $r5, $r5, #0xff
+ move $r6, #0x80000000
+ slli $r2, $r0, #8
+ or $r2, $r2, $r6
+ slli $r4, $r1, #8
+ or $r4, $r4, $r6
+ xor $r8, $r0, $r1
+ and $r6, $r6, $r8
+
+ addi $r8, $r3, #-1
+ slti $r15, $r8, #0xfe
+ beqzs8 .LFspecA
+
+.LFlab1:
+ addi $r8, $r5, #-1
+ slti $r15, $r8, #0xfe
+ beqzs8 .LFspecB
+
+.LFlab2:
+ move $r10, $r3
+/* This is a 64-bit multiple. ($r2, $r7) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r2, $r2, $r4
+#else
+ pushm $r0, $r1
+ pushm $r4, $r5
+ move P1L, $r2
+ movi P1H, #0
+ move P2L, $r4
+ movi P2H, #0
+ bal __muldi3
+ movd44 $r2, $r0
+ popm $r4, $r5
+ popm $r0, $r1
+#endif
+#ifndef __big_endian__
+ move $r7, $r2
+ move $r2, $r3
+#else
+ move $r7, $r3
+#endif
+ move $r3, $r10
+
+ beqz $r7, .Li17
+ ori $r2, $r2, #1
+
+.Li17:
+ sltsi $r15, $r2, #0
+ bnezs8 .Li18
+ slli $r2, $r2, #1
+ addi $r3, $r3, #-1
+.Li18:
+ addi $r8, $r5, #0xffffff82
+ add $r3, $r3, $r8
+ addi $r8, $r3, #-1
+ slti $r15, $r8, #0xfe
+ beqzs8 .LFoveund
+
+.LFlab8:
+ #ADD($r2, $0x80)
+ move $r15, #0x80
+ add $r2, $r2, $r15
+ slt $r15, $r2, $r15
+
+ #ADDC($r3, $0x0)
+ add $r3, $r3, $r15
+ srli $r8, $r2, #8
+ andi $r8, $r8, #1
+ sub $r2, $r2, $r8
+ slli $r2, $r2, #1
+ srli $r2, $r2, #9
+ slli $r8, $r3, #23
+ or $r2, $r2, $r8
+ or $r0, $r2, $r6
+
+.LF999:
+ popm $r6, $r10
+ pop $lp
+ ret5 $lp
+
+.LFspecA:
+ bnez $r3, .Li19
+ add $r2, $r2, $r2
+ beqz $r2, .Li20
+#ifdef __NDS32_PERF_EXT__
+ clz $r7, $r2
+#else
+ pushm $r0, $r5
+ move $r0, $r2
+ bal __clzsi2
+ move $r7, $r0
+ popm $r0, $r5
+#endif
+ sub $r3, $r3, $r7
+ sll $r2, $r2, $r7
+ j .LFlab1
+.Li20:
+ subri $r15, $r5, #0xff
+ beqzs8 .LFnan
+ j .LFzer
+.Li19:
+ add $r8, $r2, $r2
+ bnez $r8, .LFnan
+ bnez $r5, .Li21
+ add $r8, $r4, $r4
+ beqz $r8, .LFnan
+.Li21:
+ subri $r15, $r5, #0xff
+ bnezs8 .LFinf
+
+.LFspecB:
+ bnez $r5, .Li22
+ add $r4, $r4, $r4
+ beqz $r4, .LFzer
+#ifdef __NDS32_PERF_EXT__
+ clz $r7, $r4
+#else
+ pushm $r0, $r5
+ move $r0, $r4
+ bal __clzsi2
+ move $r7, $r0
+ popm $r0, $r5
+#endif
+ sub $r5, $r5, $r7
+ sll $r4, $r4, $r7
+ j .LFlab2
+
+.LFzer:
+ move $r0, $r6
+ j .LF999
+.Li22:
+ add $r8, $r4, $r4
+ bnez $r8, .LFnan
+
+.LFinf:
+ move $r8, #0x7f800000
+ or $r0, $r6, $r8
+ j .LF999
+
+.LFnan:
+ move $r0, #0xffc00000
+ j .LF999
+
+.LFoveund:
+ bgtz $r3, .LFinf
+ subri $r7, $r3, #1
+ slti $r15, $r7, #0x20
+ beqzs8 .LFzer
+ subri $r8, $r7, #0x20
+ sll $r3, $r2, $r8
+ srl $r2, $r2, $r7
+ beqz $r3, .Li25
+ ori $r2, $r2, #2
+.Li25:
+ move $r3, #0
+ addi $r8, $r2, #0x80
+ sltsi $r15, $r8, #0
+ beqzs8 .LFlab8
+ move $r3, #1
+ j .LFlab8
+ .size __mulsf3, .-__mulsf3
+#endif /* L_mul_sf */
+
+
+
+#ifdef L_mul_df
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+ #define P3L $r4
+ #define P3H $r5
+ #define O1L $r7
+ #define O1H $r8
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+ #define P3H $r4
+ #define P3L $r5
+ #define O1H $r7
+ #define O1L $r8
+#endif
+ .text
+ .align 1
+ .global __muldf3
+ .type __muldf3, @function
+__muldf3:
+ push $lp
+ pushm $r6, $r10
+
+ slli $r6, P1H, #1
+ srli $r6, $r6, #21
+ slli P3H, P1H, #11
+ srli $r10, P1L, #21
+ or P3H, P3H, $r10
+ slli P3L, P1L, #11
+ move O1L, #0x80000000
+ or P3H, P3H, O1L
+ slli $r9, P2H, #1
+ srli $r9, $r9, #21
+ slli O1H, P2H, #11
+ srli $r10, P2L, #21
+ or O1H, O1H, $r10
+ or O1H, O1H, O1L
+ xor P1H, P1H, P2H
+ and P1H, P1H, O1L
+ slli O1L, P2L, #11
+
+ addi $r10, $r6, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LFspecA
+
+.LFlab1:
+ addi $r10, $r9, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LFspecB
+
+.LFlab2:
+ addi $r10, $r9, #0xfffffc02
+ add $r6, $r6, $r10
+
+ move $r10, $r8
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r9, $r3) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r8, $r5, $r8
+#else
+ pushm $r0, $r5
+ move $r0, $r5
+ movi $r1, #0
+ move $r2, $r8
+ movi $r3, #0
+ bal __muldi3
+ movd44 $r8, $r0
+ popm $r0, $r5
+#endif
+ move $r3, $r8
+#else /* __big_endian__ */
+/* For big endain: ($r9, $r2) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r8, $r4, $r7
+#else
+ pushm $r0, $r5
+ move $r1, $r4
+ movi $r0, #0
+ move $r3, $r7
+ movi $r2, #0
+ bal __muldi3
+ movd44 $r8, $r0
+ popm $r0, $r5
+#endif
+ move $r2, $r9
+ move $r9, $r8
+#endif /* __big_endian__ */
+ move $r8, $r10
+
+ move $r10, P1H
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r2) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r4, $r8
+#else
+ pushm $r2, $r5
+ move $r0, $r4
+ movi $r1, #0
+ move $r2, $r8
+ movi $r3, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r2, $r0
+ move $r0, $r1
+#else /* __big_endian__ */
+/* For big endain: ($r1, $r3) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r5, $r7
+#else
+ pushm $r2, $r5
+ move $r1, $r5
+ movi $r0, #0
+ move $r3, $r7
+ movi $r2, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r3, $r1
+ move $r1, $r0
+#endif /* __big_endian__ */
+ move P1H, $r10
+
+ #ADD(P2H, P1L)
+ add P2H, P2H, P1L
+ slt $r15, P2H, P1L
+
+ #ADDC($r9, $0x0)
+ add $r9, $r9, $r15
+
+ move $r10, P1H
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r8) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r5, $r7
+#else
+ pushm $r2, $r5
+ move $r0, $r5
+ movi $r1, #0
+ move $r2, $r7
+ movi $r3, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r8, $r0
+ move $r0, $r1
+#else /* __big_endian__ */
+/* For big endian: ($r1, $r7) is (high, low). */
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r4, $r8
+#else
+ pushm $r2, $r5
+ move $r1, $r4
+ movi $r0, #0
+ move $r3, $r8
+ movi $r2, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r7, $r1
+ move $r1, $r0
+#endif /* __big_endian__ */
+ move P1H, $r10
+
+ #ADD(P2L, O1H)
+ add P2L, P2L, O1H
+ slt $r15, P2L, O1H
+
+
+ #ADDCC(P2H, P1L)
+ beqzs8 .LL29
+ add P2H, P2H, P1L
+ slt $r15, P2H, P1L
+ beqzs8 .LL30
+ addi P2H, P2H, #0x1
+ j .LL31
+.LL30:
+ move $r15, #1
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+ j .LL31
+.LL29:
+ add P2H, P2H, P1L
+ slt $r15, P2H, P1L
+.LL31:
+
+ #ADDC($r9, $0x0)
+ add $r9, $r9, $r15
+
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r8, $r0) is (high, low). */
+ move $r10, $r9
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r8, $r4, $r7
+#else
+ pushm $r0, $r5
+ move $r0, $r4
+ movi $r1, #0
+ move $r2, $r7
+ movi $r3, #0
+ bal __muldi3
+ movd44 $r8, $r0
+ popm $r0, $r5
+#endif
+ move $r0, $r8
+ move $r8, $r9
+ move $r9, $r10
+#else /* __big_endian__ */
+/* For big endian: ($r7, $r1) is (high, low). */
+ move $r10, $r6
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r6, $r5, $r8
+#else
+ pushm $r0, $r5
+ move $r1, $r5
+ movi $r0, #0
+ move $r3, $r8
+ movi $r2, #0
+ bal __muldi3
+ movd44 $r6, $r0
+ popm $r0, $r5
+#endif
+ move $r1, $r7
+ move $r7, $r6
+ move $r6, $r10
+#endif /* __big_endian__ */
+
+ #ADD(P2L, O1H)
+ add P2L, P2L, O1H
+ slt $r15, P2L, O1H
+
+
+ #ADDCC(P2H, $0x0)
+ beqzs8 .LL34
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+.LL34:
+
+ #ADDC($r9, $0x0)
+ add $r9, $r9, $r15
+ or $r10, P1L, P2L
+ beqz $r10, .Li13
+ ori P2H, P2H, #1
+.Li13:
+ move P3H, $r9
+ move P3L, P2H
+ sltsi $r15, P3H, #0
+ bnezs8 .Li14
+
+ move $r15, P3L
+ add P3L, P3L, P3L
+ slt $r15, P3L, $r15
+ add P3H, P3H, P3H
+ add P3H, P3H, $r15
+ addi $r6, $r6, #-1
+.Li14:
+ addi $r10, $r6, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LFoveund
+
+ #ADD(P3L, $0x400)
+ move $r15, #0x400
+ add P3L, P3L, $r15
+ slt $r15, P3L, $r15
+
+
+ #ADDCC(P3H, $0x0)
+ beqzs8 .LL37
+ add P3H, P3H, $r15
+ slt $r15, P3H, $r15
+.LL37:
+
+ #ADDC($r6, $0x0)
+ add $r6, $r6, $r15
+
+.LFlab8:
+ srli $r10, P3L, #11
+ andi $r10, $r10, #1
+ sub P3L, P3L, $r10
+ srli P1L, P3L, #11
+ slli $r10, P3H, #21
+ or P1L, P1L, $r10
+ slli $r10, P3H, #1
+ srli $r10, $r10, #12
+ or P1H, P1H, $r10
+ slli $r10, $r6, #20
+ or P1H, P1H, $r10
+
+.LFret:
+.LF999:
+ popm $r6, $r10
+ pop $lp
+ ret5 $lp
+
+.LFspecA:
+ #ADD(P3L, P3L)
+ move $r15, P3L
+ add P3L, P3L, P3L
+ slt $r15, P3L, $r15
+
+ #ADDC(P3H, P3H)
+ add P3H, P3H, P3H
+ add P3H, P3H, $r15
+ bnez $r6, .Li15
+ or $r10, P3H, P3L
+ beqz $r10, .Li16
+
+
+ #NORMd($r4, P1L, P2H)
+ bnez P3H, .LL38
+ bnez P3L, .LL39
+ move $r6, #0
+ j .LL40
+.LL39:
+ move P3H, P3L
+ move P3L, #0
+ move P1L, #32
+ sub $r6, $r6, P1L
+.LL38:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r0, P3H
+#else
+ pushm $r1, P3H
+ move $r0, P3H
+ bal __clzsi2
+ popm $r1, $r5
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r1, $r4
+#else
+ push $r0
+ pushm $r2, $r5
+ move $r0, $r4
+ bal __clzsi2
+ move $r1, $r0
+ popm $r2, $r5
+ pop $r0
+#endif
+#endif /* __big_endian__ */
+ beqz P1L, .LL40
+ sub $r6, $r6, P1L
+ subri P2H, P1L, #32
+ srl P2H, P3L, P2H
+ sll P3L, P3L, P1L
+ sll P3H, P3H, P1L
+ or P3H, P3H, P2H
+.LL40:
+ #NORMd End
+
+ j .LFlab1
+.Li16:
+ subri $r15, $r9, #0x7ff
+ beqzs8 .LFnan
+ j .LFret
+.Li15:
+ or $r10, P3H, P3L
+ bnez $r10, .LFnan
+ bnez $r9, .Li17
+ slli $r10, O1H, #1
+ or $r10, $r10, O1L
+ beqz $r10, .LFnan
+.Li17:
+ subri $r15, $r9, #0x7ff
+ bnezs8 .LFinf
+
+.LFspecB:
+ #ADD(O1L, O1L)
+ move $r15, O1L
+ add O1L, O1L, O1L
+ slt $r15, O1L, $r15
+
+ #ADDC(O1H, O1H)
+ add O1H, O1H, O1H
+ add O1H, O1H, $r15
+ bnez $r9, .Li18
+ or $r10, O1H, O1L
+ beqz $r10, .Li19
+
+
+ #NORMd($r7, P2L, P1L)
+ bnez O1H, .LL41
+ bnez O1L, .LL42
+ move $r9, #0
+ j .LL43
+.LL42:
+ move O1H, O1L
+ move O1L, #0
+ move P2L, #32
+ sub $r9, $r9, P2L
+.LL41:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r2, $r8
+#else
+ pushm $r0, $r1
+ pushm $r3, $r5
+ move $r0, $r8
+ bal __clzsi2
+ move $r2, $r0
+ popm $r3, $r5
+ popm $r0, $r1
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r3, $r7
+#else
+ pushm $r0, $r2
+ pushm $r4, $r5
+ move $r0, $r7
+ bal __clzsi2
+ move $r3, $r0
+ popm $r4, $r5
+ popm $r0, $r2
+#endif
+#endif /* __big_endian__ */
+ beqz P2L, .LL43
+ sub $r9, $r9, P2L
+ subri P1L, P2L, #32
+ srl P1L, O1L, P1L
+ sll O1L, O1L, P2L
+ sll O1H, O1H, P2L
+ or O1H, O1H, P1L
+.LL43:
+ #NORMd End
+
+ j .LFlab2
+.Li19:
+ move P1L, #0
+ j .LFret
+.Li18:
+ or $r10, O1H, O1L
+ bnez $r10, .LFnan
+
+.LFinf:
+ move $r10, #0x7ff00000
+ or P1H, P1H, $r10
+ move P1L, #0
+ j .LFret
+
+.LFnan:
+ move P1H, #0xfff80000
+ move P1L, #0
+ j .LFret
+
+.LFoveund:
+ bgtz $r6, .LFinf
+ subri P1L, $r6, #1
+ move P2L, #0
+.LL44:
+ move $r10, #0x20
+ slt $r15, P1L, $r10
+ bnezs8 .LL45
+ or P2L, P2L, P3L
+ move P3L, P3H
+ move P3H, #0
+ addi P1L, P1L, #0xffffffe0
+ bnez P3L, .LL44
+.LL45:
+ beqz P1L, .LL46
+ move P2H, P3H
+ move $r10, P3L
+ srl P3L, P3L, P1L
+ srl P3H, P3H, P1L
+ subri P1L, P1L, #0x20
+ sll P2H, P2H, P1L
+ or P3L, P3L, P2H
+ sll $r10, $r10, P1L
+ or P2L, P2L, $r10
+ beqz P2L, .LL46
+ ori P3L, P3L, #1
+.LL46:
+ #ADD(P3L, $0x400)
+ move $r15, #0x400
+ add P3L, P3L, $r15
+ slt $r15, P3L, $r15
+
+ #ADDC(P3H, $0x0)
+ add P3H, P3H, $r15
+ srli $r6, P3H, #31
+ j .LFlab8
+ .size __muldf3, .-__muldf3
+#endif /* L_mul_df */
+
+
+
+#ifdef L_div_sf
+
+ .text
+ .align 1
+ .global __divsf3
+ .type __divsf3, @function
+__divsf3:
+ push $lp
+ pushm $r6, $r10
+
+ move $r7, #0x80000000
+ srli $r4, $r0, #23
+ andi $r4, $r4, #0xff
+ srli $r6, $r1, #23
+ andi $r6, $r6, #0xff
+ slli $r3, $r0, #8
+ or $r3, $r3, $r7
+ slli $r5, $r1, #8
+ or $r5, $r5, $r7
+ xor $r10, $r0, $r1
+ and $r7, $r7, $r10
+
+ addi $r10, $r4, #-1
+ slti $r15, $r10, #0xfe
+ beqzs8 .LGspecA
+
+.LGlab1:
+ addi $r10, $r6, #-1
+ slti $r15, $r10, #0xfe
+ beqzs8 .LGspecB
+
+.LGlab2:
+ slt $r15, $r3, $r5
+ bnezs8 .Li27
+ srli $r3, $r3, #1
+ addi $r4, $r4, #1
+.Li27:
+ srli $r8, $r5, #14
+ divr $r0, $r2, $r3, $r8
+ andi $r9, $r5, #0x3fff
+ mul $r1, $r9, $r0
+ slli $r2, $r2, #14
+
+ #SUB($r2, $r1)
+ move $r15, $r2
+ sub $r2, $r2, $r1
+ slt $r15, $r15, $r2
+ beqzs8 .Li28
+ addi $r0, $r0, #-1
+
+ #ADD($r2, $r5)
+ add $r2, $r2, $r5
+ slt $r15, $r2, $r5
+.Li28:
+ divr $r3, $r2, $r2, $r8
+ mul $r1, $r9, $r3
+ slli $r2, $r2, #14
+
+ #SUB($r2, $r1)
+ move $r15, $r2
+ sub $r2, $r2, $r1
+ slt $r15, $r15, $r2
+ beqzs8 .Li29
+ addi $r3, $r3, #-1
+
+ #ADD($r2, $r5)
+ add $r2, $r2, $r5
+ slt $r15, $r2, $r5
+.Li29:
+ slli $r10, $r0, #14
+ add $r3, $r3, $r10
+ slli $r3, $r3, #4
+ beqz $r2, .Li30
+ ori $r3, $r3, #1
+.Li30:
+ subri $r10, $r6, #0x7e
+ add $r4, $r4, $r10
+ addi $r10, $r4, #-1
+ slti $r15, $r10, #0xfe
+ beqzs8 .LGoveund
+
+.LGlab8:
+ #ADD($r3, $0x80)
+ move $r15, #0x80
+ add $r3, $r3, $r15
+ slt $r15, $r3, $r15
+
+ #ADDC($r4, $0x0)
+ add $r4, $r4, $r15
+ srli $r10, $r3, #8
+ andi $r10, $r10, #1
+ sub $r3, $r3, $r10
+ slli $r3, $r3, #1
+ srli $r3, $r3, #9
+ slli $r10, $r4, #23
+ or $r3, $r3, $r10
+ or $r0, $r3, $r7
+
+.LG999:
+ popm $r6, $r10
+ pop $lp
+ ret5 $lp
+
+.LGspecA:
+ bnez $r4, .Li31
+ add $r3, $r3, $r3
+ beqz $r3, .Li31
+#ifdef __NDS32_PERF_EXT__
+ clz $r8, $r3
+#else
+ pushm $r0, $r5
+ move $r0, $r3
+ bal __clzsi2
+ move $r8, $r0
+ popm $r0, $r5
+#endif
+ sub $r4, $r4, $r8
+ sll $r3, $r3, $r8
+ j .LGlab1
+.Li31:
+ bne $r6, $r4, .Li33
+ add $r10, $r5, $r5
+ beqz $r10, .LGnan
+.Li33:
+ subri $r15, $r6, #0xff
+ beqzs8 .LGspecB
+ beqz $r4, .LGzer
+ add $r10, $r3, $r3
+ bnez $r10, .LGnan
+ j .LGinf
+
+.LGspecB:
+ bnez $r6, .Li34
+ add $r5, $r5, $r5
+ beqz $r5, .LGinf
+#ifdef __NDS32_PERF_EXT__
+ clz $r8, $r5
+#else
+ pushm $r0, $r5
+ move $r0, $r5
+ bal __clzsi2
+ move $r8, $r0
+ popm $r0, $r5
+#endif
+ sub $r6, $r6, $r8
+ sll $r5, $r5, $r8
+ j .LGlab2
+.Li34:
+ add $r10, $r5, $r5
+ bnez $r10, .LGnan
+
+.LGzer:
+ move $r0, $r7
+ j .LG999
+
+.LGoveund:
+ bgtz $r4, .LGinf
+ subri $r8, $r4, #1
+ slti $r15, $r8, #0x20
+ beqzs8 .LGzer
+ subri $r10, $r8, #0x20
+ sll $r4, $r3, $r10
+ srl $r3, $r3, $r8
+ beqz $r4, .Li37
+ ori $r3, $r3, #2
+.Li37:
+ move $r4, #0
+ addi $r10, $r3, #0x80
+ sltsi $r15, $r10, #0
+ beqzs8 .LGlab8
+ move $r4, #1
+ j .LGlab8
+
+.LGinf:
+ move $r10, #0x7f800000
+ or $r0, $r7, $r10
+ j .LG999
+
+.LGnan:
+ move $r0, #0xffc00000
+ j .LG999
+ .size __divsf3, .-__divsf3
+#endif /* L_div_sf */
+
+
+
+#ifdef L_div_df
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+ #define P3L $r4
+ #define P3H $r5
+ #define O1L $r7
+ #define O1H $r8
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+ #define P3H $r4
+ #define P3L $r5
+ #define O1H $r7
+ #define O1L $r8
+#endif
+ .text
+ .align 1
+ .global __divdf3
+ .type __divdf3, @function
+__divdf3:
+ push $lp
+ pushm $r6, $r10
+
+ slli $r6, P1H, #1
+ srli $r6, $r6, #21
+ slli P3H, P1H, #11
+ srli $r10, P1L, #21
+ or P3H, P3H, $r10
+ slli P3L, P1L, #11
+ move O1L, #0x80000000
+ or P3H, P3H, O1L
+ slli $r9, P2H, #1
+ srli $r9, $r9, #21
+ slli O1H, P2H, #11
+ srli $r10, P2L, #21
+ or O1H, O1H, $r10
+ or O1H, O1H, O1L
+ xor P1H, P1H, P2H
+ and P1H, P1H, O1L
+ slli O1L, P2L, #11
+
+ addi $r10, $r6, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LGspecA
+
+.LGlab1:
+ addi $r10, $r9, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LGspecB
+
+.LGlab2:
+ sub $r6, $r6, $r9
+ addi $r6, $r6, #0x3ff
+ srli P3L, P3L, #1
+ slli $r10, P3H, #31
+ or P3L, P3L, $r10
+ srli P3H, P3H, #1
+ srli $r9, O1H, #16
+ divr P2H, P3H, P3H, $r9
+ move $r10, #0xffff
+ and P2L, O1H, $r10
+ mul P1L, P2L, P2H
+ slli P3H, P3H, #16
+ srli $r10, P3L, #16
+ or P3H, P3H, $r10
+
+ #SUB(P3H, P1L)
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+ beqzs8 .Li20
+
+.Lb21:
+ addi P2H, P2H, #-1
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .Lb21
+.Li20:
+ divr $r9, P3H, P3H, $r9
+ mul P1L, P2L, $r9
+ slli P3H, P3H, #16
+ move $r15, #0xffff
+ and $r10, P3L, $r15
+ or P3H, P3H, $r10
+
+ #SUB(P3H, P1L)
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+ beqzs8 .Li22
+
+.Lb23:
+ addi $r9, $r9, #-1
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .Lb23
+.Li22:
+ slli P2H, P2H, #16
+ add P2H, P2H, $r9
+
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r9) is (high, low). */
+ move $r10, $r1
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r3, $r7
+#else
+ pushm $r2, $r5
+ move $r0, $r3
+ movi $r1, #0
+ move $r2, $r7
+ movi $r3, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r9, $r0
+ move $r0, $r1
+ move $r1, $r10
+#else /* __big_endian__ */
+/* For big endian: ($r1, $r9) is (high, low). */
+ move $r10, $r0
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r2, $r8
+#else
+ pushm $r2, $r5
+ move $r1, $r2
+ movi $r0, #0
+ move $r3, $r8
+ movi $r2, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r9, $r1
+ move $r1, $r0
+ move $r0, $r10
+#endif /* __big_endian__ */
+
+ move P3L, #0
+
+ #SUB(P3L, $r9)
+ move $r15, P3L
+ sub P3L, P3L, $r9
+ slt $r15, $r15, P3L
+
+
+ #SUBCC(P3H, P1L)
+ beqzs8 .LL47
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+ beqzs8 .LL48
+ subi333 P3H, P3H, #1
+ j .LL49
+.LL48:
+ move $r15, P3H
+ subi333 P3H, P3H, #1
+ slt $r15, $r15, P3H
+ j .LL49
+.LL47:
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+.LL49:
+
+ beqzs8 .Li24
+
+.LGlab3:
+ addi P2H, P2H, #-1
+
+ #ADD(P3L, O1L)
+ add P3L, P3L, O1L
+ slt $r15, P3L, O1L
+
+
+ #ADDCC(P3H, O1H)
+ beqzs8 .LL50
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .LL51
+ addi P3H, P3H, #0x1
+ j .LL52
+.LL51:
+ move $r15, #1
+ add P3H, P3H, $r15
+ slt $r15, P3H, $r15
+ j .LL52
+.LL50:
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+.LL52:
+
+ beqzs8 .LGlab3
+.Li24:
+ bne P3H, O1H, .Li25
+ move P1L, O1L
+ move P3H, P3L
+ move $r9, #0
+ move P2L, $r9
+ j .Le25
+.Li25:
+ srli P2L, O1H, #16
+ divr $r9, P3H, P3H, P2L
+ move $r10, #0xffff
+ and $r10, O1H, $r10
+ mul P1L, $r10, $r9
+ slli P3H, P3H, #16
+ srli $r15, P3L, #16
+ or P3H, P3H, $r15
+
+ #SUB(P3H, P1L)
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+ beqzs8 .Li26
+
+.Lb27:
+ addi $r9, $r9, #-1
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .Lb27
+.Li26:
+ divr P2L, P3H, P3H, P2L
+ mul P1L, $r10, P2L
+ slli P3H, P3H, #16
+ move $r10, #0xffff
+ and $r10, P3L, $r10
+ or P3H, P3H, $r10
+
+ #SUB(P3H, P1L)
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+ beqzs8 .Li28
+
+.Lb29:
+ addi P2L, P2L, #-1
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .Lb29
+.Li28:
+ slli $r9, $r9, #16
+ add $r9, $r9, P2L
+
+/* This is a 64-bit multiple. */
+#ifndef __big_endian__
+/* For little endian: ($r0, $r2) is (high, low). */
+ move $r10, $r1
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r9, $r7
+#else
+ pushm $r2, $r5
+ move $r0, $r9
+ movi $r1, #0
+ move $r2, $r7
+ movi $r3, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r2, $r0
+ move $r0, $r1
+ move $r1, $r10
+#else /* __big_endian__ */
+/* For big endian: ($r1, $r3) is (high, low). */
+ move $r10, $r0
+#ifndef __NDS32_ISA_V3M__
+ mulr64 $r0, $r9, $r8
+#else
+ pushm $r2, $r5
+ move $r0, $r9
+ movi $r1, #0
+ move $r2, $r7
+ movi $r3, #0
+ bal __muldi3
+ popm $r2, $r5
+#endif
+ move $r3, $r1
+ move $r1, $r0
+ move $r0, $r10
+#endif /* __big_endian__ */
+
+.Le25:
+ move P3L, #0
+
+ #SUB(P3L, P2L)
+ move $r15, P3L
+ sub P3L, P3L, P2L
+ slt $r15, $r15, P3L
+
+
+ #SUBCC(P3H, P1L)
+ beqzs8 .LL53
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+ beqzs8 .LL54
+ subi333 P3H, P3H, #1
+ j .LL55
+.LL54:
+ move $r15, P3H
+ subi333 P3H, P3H, #1
+ slt $r15, $r15, P3H
+ j .LL55
+.LL53:
+ move $r15, P3H
+ sub P3H, P3H, P1L
+ slt $r15, $r15, P3H
+.LL55:
+
+ beqzs8 .Li30
+
+.LGlab4:
+ addi $r9, $r9, #-1
+
+ #ADD(P3L, O1L)
+ add P3L, P3L, O1L
+ slt $r15, P3L, O1L
+
+
+ #ADDCC(P3H, O1H)
+ beqzs8 .LL56
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+ beqzs8 .LL57
+ addi P3H, P3H, #0x1
+ j .LL58
+.LL57:
+ move $r15, #1
+ add P3H, P3H, $r15
+ slt $r15, P3H, $r15
+ j .LL58
+.LL56:
+ add P3H, P3H, O1H
+ slt $r15, P3H, O1H
+.LL58:
+
+ beqzs8 .LGlab4
+.Li30:
+ sltsi $r15, P2H, #0
+ bnezs8 .Li31
+
+ #ADD($r9, $r9)
+ move $r15, $r9
+ add $r9, $r9, $r9
+ slt $r15, $r9, $r15
+
+ #ADDC(P2H, P2H)
+ add P2H, P2H, P2H
+ add P2H, P2H, $r15
+ addi $r6, $r6, #-1
+.Li31:
+ or $r10, P3H, P3L
+ beqz $r10, .Li32
+ ori $r9, $r9, #1
+.Li32:
+ move P3H, P2H
+ move P3L, $r9
+ addi $r10, $r6, #-1
+ slti $r15, $r10, #0x7fe
+ beqzs8 .LGoveund
+
+ #ADD(P3L, $0x400)
+ move $r15, #0x400
+ add P3L, P3L, $r15
+ slt $r15, P3L, $r15
+
+
+ #ADDCC(P3H, $0x0)
+ beqzs8 .LL61
+ add P3H, P3H, $r15
+ slt $r15, P3H, $r15
+.LL61:
+
+ #ADDC($r6, $0x0)
+ add $r6, $r6, $r15
+
+.LGlab8:
+ srli $r10, P3L, #11
+ andi $r10, $r10, #1
+ sub P3L, P3L, $r10
+ srli P1L, P3L, #11
+ slli $r10, P3H, #21
+ or P1L, P1L, $r10
+ slli $r10, P3H, #1
+ srli $r10, $r10, #12
+ or P1H, P1H, $r10
+ slli $r10, $r6, #20
+ or P1H, P1H, $r10
+
+.LGret:
+.LG999:
+ popm $r6, $r10
+ pop $lp
+ ret5 $lp
+
+.LGoveund:
+ bgtz $r6, .LGinf
+ subri P2H, $r6, #1
+ move P1L, #0
+.LL62:
+ move $r10, #0x20
+ slt $r15, P2H, $r10
+ bnezs8 .LL63
+ or P1L, P1L, P3L
+ move P3L, P3H
+ move P3H, #0
+ addi P2H, P2H, #0xffffffe0
+ bnez P3L, .LL62
+.LL63:
+ beqz P2H, .LL64
+ move P2L, P3H
+ move $r10, P3L
+ srl P3L, P3L, P2H
+ srl P3H, P3H, P2H
+ subri P2H, P2H, #0x20
+ sll P2L, P2L, P2H
+ or P3L, P3L, P2L
+ sll $r10, $r10, P2H
+ or P1L, P1L, $r10
+ beqz P1L, .LL64
+ ori P3L, P3L, #1
+.LL64:
+ #ADD(P3L, $0x400)
+ move $r15, #0x400
+ add P3L, P3L, $r15
+ slt $r15, P3L, $r15
+
+ #ADDC(P3H, $0x0)
+ add P3H, P3H, $r15
+ srli $r6, P3H, #31
+ j .LGlab8
+
+.LGspecA:
+ #ADD(P3L, P3L)
+ move $r15, P3L
+ add P3L, P3L, P3L
+ slt $r15, P3L, $r15
+
+ #ADDC(P3H, P3H)
+ add P3H, P3H, P3H
+ add P3H, P3H, $r15
+ bnez $r6, .Li33
+ or $r10, P3H, P3L
+ beqz $r10, .Li33
+
+
+ #NORMd($r4, P2H, P2L)
+ bnez P3H, .LL65
+ bnez P3L, .LL66
+ move $r6, #0
+ j .LL67
+.LL66:
+ move P3H, P3L
+ move P3L, #0
+ move P2H, #32
+ sub $r6, $r6, P2H
+.LL65:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r3, $r5
+#else
+ pushm $r0, $r2
+ pushm $r4, $r5
+ move $r0, $r5
+ bal __clzsi2
+ move $r3, $r0
+ popm $r4, $r5
+ popm $r0, $r2
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r2, $r4
+#else
+ pushm $r0, $r1
+ pushm $r3, $r5
+ move $r0, $r4
+ bal __clzsi2
+ move $r2, $r0
+ popm $r3, $r5
+ popm $r0, $r1
+#endif
+#endif /* __big_endian_ */
+ beqz P2H, .LL67
+ sub $r6, $r6, P2H
+ subri P2L, P2H, #32
+ srl P2L, P3L, P2L
+ sll P3L, P3L, P2H
+ sll P3H, P3H, P2H
+ or P3H, P3H, P2L
+.LL67:
+ #NORMd End
+
+ j .LGlab1
+.Li33:
+ bne $r6, $r9, .Li35
+ slli $r10, O1H, #1
+ or $r10, $r10, O1L
+ beqz $r10, .LGnan
+.Li35:
+ subri $r15, $r9, #0x7ff
+ beqzs8 .LGspecB
+ beqz $r6, .LGret
+ or $r10, P3H, P3L
+ bnez $r10, .LGnan
+
+.LGinf:
+ move $r10, #0x7ff00000
+ or P1H, P1H, $r10
+ move P1L, #0
+ j .LGret
+
+.LGspecB:
+ #ADD(O1L, O1L)
+ move $r15, O1L
+ add O1L, O1L, O1L
+ slt $r15, O1L, $r15
+
+ #ADDC(O1H, O1H)
+ add O1H, O1H, O1H
+ add O1H, O1H, $r15
+ bnez $r9, .Li36
+ or $r10, O1H, O1L
+ beqz $r10, .LGinf
+
+
+ #NORMd($r7, P2H, P2L)
+ bnez O1H, .LL68
+ bnez O1L, .LL69
+ move $r9, #0
+ j .LL70
+.LL69:
+ move O1H, O1L
+ move O1L, #0
+ move P2H, #32
+ sub $r9, $r9, P2H
+.LL68:
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r3, $r8
+#else
+ pushm $r0, $r2
+ pushm $r4, $r5
+ move $r0, $r8
+ bal __clzsi2
+ move $r3, $r0
+ popm $r4, $r5
+ popm $r0, $r2
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r2, $r7
+#else
+ pushm $r0, $r1
+ pushm $r3, $r5
+ move $r0, $r7
+ bal __clzsi2
+ move $r2, $r0
+ popm $r3, $r5
+ popm $r0, $r1
+#endif
+#endif /* __big_endian__ */
+ beqz P2H, .LL70
+ sub $r9, $r9, P2H
+ subri P2L, P2H, #32
+ srl P2L, O1L, P2L
+ sll O1L, O1L, P2H
+ sll O1H, O1H, P2H
+ or O1H, O1H, P2L
+.LL70:
+ #NORMd End
+
+ j .LGlab2
+.Li36:
+ or $r10, O1H, O1L
+ beqz $r10, .Li38
+
+.LGnan:
+ move P1H, #0xfff80000
+.Li38:
+ move P1L, #0
+ j .LGret
+ .size __divdf3, .-__divdf3
+#endif /* L_div_df */
+
+
+
+#ifdef L_negate_sf
+
+ .text
+ .align 1
+ .global __negsf2
+ .type __negsf2, @function
+__negsf2:
+ push $lp
+
+ move $r1, #0x80000000
+ xor $r0, $r0, $r1
+
+.LN999:
+ pop $lp
+ ret5 $lp
+ .size __negsf2, .-__negsf2
+#endif /* L_negate_sf */
+
+
+
+#ifdef L_negate_df
+
+#ifndef __big_endian__
+ #define P1H $r1
+#else
+ #define P1H $r0
+#endif
+ .text
+ .align 1
+ .global __negdf2
+ .type __negdf2, @function
+__negdf2:
+ push $lp
+
+ move $r2, #0x80000000
+ xor P1H, P1H, $r2
+
+.LP999:
+ pop $lp
+ ret5 $lp
+ .size __negdf2, .-__negdf2
+#endif /* L_negate_df */
+
+
+
+#ifdef L_sf_to_df
+
+#ifndef __big_endian__
+ #define O1L $r1
+ #define O1H $r2
+#else
+ #define O1H $r1
+ #define O1L $r2
+#endif
+ .text
+ .align 1
+ .global __extendsfdf2
+ .type __extendsfdf2, @function
+__extendsfdf2:
+ push $lp
+
+ srli $r3, $r0, #23
+ andi $r3, $r3, #0xff
+ move $r5, #0x80000000
+ and O1H, $r0, $r5
+ addi $r5, $r3, #-1
+ slti $r15, $r5, #0xfe
+ beqzs8 .LJspec
+
+.LJlab1:
+ addi $r3, $r3, #0x380
+ slli $r5, $r0, #9
+ srli $r5, $r5, #12
+ or O1H, O1H, $r5
+ slli O1L, $r0, #29
+
+.LJret:
+ slli $r5, $r3, #20
+ or O1H, O1H, $r5
+ move $r0, $r1
+ move $r1, $r2
+
+.LJ999:
+ pop $lp
+ ret5 $lp
+
+.LJspec:
+ move O1L, #0
+ add $r0, $r0, $r0
+ beqz $r0, .LJret
+ bnez $r3, .Li42
+
+.Lb43:
+ addi $r3, $r3, #-1
+ add $r0, $r0, $r0
+ move $r5, #0x800000
+ slt $r15, $r0, $r5
+ bnezs8 .Lb43
+ j .LJlab1
+.Li42:
+ move $r3, #0x7ff
+ move $r5, #0xff000000
+ slt $r15, $r5, $r0
+ beqzs8 .LJret
+ move O1H, #0xfff80000
+ j .LJret
+ .size __extendsfdf2, .-__extendsfdf2
+#endif /* L_sf_to_df */
+
+
+
+#ifdef L_df_to_sf
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+#endif
+ .text
+ .align 1
+ .global __truncdfsf2
+ .type __truncdfsf2, @function
+__truncdfsf2:
+ push $lp
+ pushm $r6, $r8
+
+ slli P2H, P1H, #11
+ srli $r7, P1L, #21
+ or P2H, P2H, $r7
+ slli P2L, P1L, #11
+ move $r7, #0x80000000
+ or P2H, P2H, $r7
+ and $r5, P1H, $r7
+ slli $r4, P1H, #1
+ srli $r4, $r4, #21
+ addi $r4, $r4, #0xfffffc80
+ addi $r7, $r4, #-1
+ slti $r15, $r7, #0xfe
+ beqzs8 .LKspec
+
+.LKlab1:
+ beqz P2L, .Li45
+ ori P2H, P2H, #1
+.Li45:
+ #ADD(P2H, $0x80)
+ move $r15, #0x80
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+
+ #ADDC($r4, $0x0)
+ add $r4, $r4, $r15
+ srli $r7, P2H, #8
+ andi $r7, $r7, #1
+ sub P2H, P2H, $r7
+ slli P2H, P2H, #1
+ srli P2H, P2H, #9
+ slli $r7, $r4, #23
+ or P2H, P2H, $r7
+ or $r0, P2H, $r5
+
+.LK999:
+ popm $r6, $r8
+ pop $lp
+ ret5 $lp
+
+.LKspec:
+ subri $r15, $r4, #0x47f
+ bnezs8 .Li46
+ slli $r7, P2H, #1
+ or $r7, $r7, P2L
+ beqz $r7, .Li46
+ move $r0, #0xffc00000
+ j .LK999
+.Li46:
+ sltsi $r15, $r4, #0xff
+ bnezs8 .Li48
+ move $r7, #0x7f800000
+ or $r0, $r5, $r7
+ j .LK999
+.Li48:
+ subri $r6, $r4, #1
+ move $r7, #0x20
+ slt $r15, $r6, $r7
+ bnezs8 .Li49
+ move $r0, $r5
+ j .LK999
+.Li49:
+ subri $r8, $r6, #0x20
+ sll $r7, P2H, $r8
+ or P2L, P2L, $r7
+ srl P2H, P2H, $r6
+ move $r4, #0
+ move $r7, #0x80000000
+ or P2H, P2H, $r7
+ j .LKlab1
+ .size __truncdfsf2, .-__truncdfsf2
+#endif /* L_df_to_sf */
+
+
+
+#ifdef L_df_to_si
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+#else
+ #define P1H $r0
+ #define P1L $r1
+#endif
+ .global __fixdfsi
+ .type __fixdfsi, @function
+__fixdfsi:
+ push $lp
+ pushm $r6, $r6
+
+ slli $r3, P1H, #11
+ srli $r6, P1L, #21
+ or $r3, $r3, $r6
+ move $r6, #0x80000000
+ or $r3, $r3, $r6
+ slli $r6, P1H, #1
+ srli $r6, $r6, #21
+ subri $r2, $r6, #0x41e
+ blez $r2, .LLnaninf
+ move $r6, #0x20
+ slt $r15, $r2, $r6
+ bnezs8 .LL72
+ move $r3, #0
+.LL72:
+ srl $r3, $r3, $r2
+ sltsi $r15, P1H, #0
+ beqzs8 .Li50
+ subri $r3, $r3, #0
+.Li50:
+ move $r0, $r3
+
+.LL999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+
+.LLnaninf:
+ beqz P1L, .Li51
+ ori P1H, P1H, #1
+.Li51:
+ move $r6, #0x7ff00000
+ slt $r15, $r6, P1H
+ beqzs8 .Li52
+ move $r0, #0x80000000
+ j .LL999
+.Li52:
+ move $r0, #0x7fffffff
+ j .LL999
+ .size __fixdfsi, .-__fixdfsi
+#endif /* L_df_to_si */
+
+
+
+#ifdef L_fixsfdi
+
+#ifndef __big_endian__
+ #define O1L $r1
+ #define O1H $r2
+#else
+ #define O1H $r1
+ #define O1L $r2
+#endif
+ .text
+ .align 1
+ .global __fixsfdi
+ .type __fixsfdi, @function
+__fixsfdi:
+ push $lp
+
+ srli $r3, $r0, #23
+ andi $r3, $r3, #0xff
+ slli O1H, $r0, #8
+ move $r5, #0x80000000
+ or O1H, O1H, $r5
+ move O1L, #0
+ sltsi $r15, $r3, #0xbe
+ beqzs8 .LCinfnan
+ subri $r3, $r3, #0xbe
+.LL8:
+ move $r5, #0x20
+ slt $r15, $r3, $r5
+ bnezs8 .LL9
+ move O1L, O1H
+ move O1H, #0
+ addi $r3, $r3, #0xffffffe0
+ bnez O1L, .LL8
+.LL9:
+ beqz $r3, .LL10
+ move $r4, O1H
+ srl O1L, O1L, $r3
+ srl O1H, O1H, $r3
+ subri $r3, $r3, #0x20
+ sll $r4, $r4, $r3
+ or O1L, O1L, $r4
+.LL10:
+ sltsi $r15, $r0, #0
+ beqzs8 .LCret
+
+ subri O1H, O1H, #0
+ beqz O1L, .LL11
+ subri O1L, O1L, #0
+ subi45 O1H, #1
+.LL11:
+
+.LCret:
+ move $r0, $r1
+ move $r1, $r2
+
+.LC999:
+ pop $lp
+ ret5 $lp
+
+.LCinfnan:
+ sltsi $r15, $r0, #0
+ bnezs8 .LCret3
+ subri $r15, $r3, #0xff
+ bnezs8 .Li7
+ slli $r5, O1H, #1
+ beqz $r5, .Li7
+
+.LCret3:
+ move O1H, #0x80000000
+ j .LCret
+.Li7:
+ move O1H, #0x7fffffff
+ move O1L, #-1
+ j .LCret
+ .size __fixsfdi, .-__fixsfdi
+#endif /* L_fixsfdi */
+
+
+
+#ifdef L_fixdfdi
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define O1L $r3
+ #define O1H $r4
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define O1H $r3
+ #define O1L $r4
+#endif
+ .text
+ .align 1
+ .global __fixdfdi
+ .type __fixdfdi, @function
+__fixdfdi:
+ push $lp
+ pushm $r6, $r6
+
+ slli $r5, P1H, #1
+ srli $r5, $r5, #21
+ slli O1H, P1H, #11
+ srli $r6, P1L, #21
+ or O1H, O1H, $r6
+ slli O1L, P1L, #11
+ move $r6, #0x80000000
+ or O1H, O1H, $r6
+ slti $r15, $r5, #0x43e
+ beqzs8 .LCnaninf
+ subri $r2, $r5, #0x43e
+.LL14:
+ move $r6, #0x20
+ slt $r15, $r2, $r6
+ bnezs8 .LL15
+ move O1L, O1H
+ move O1H, #0
+ addi $r2, $r2, #0xffffffe0
+ bnez O1L, .LL14
+.LL15:
+ beqz $r2, .LL16
+ move P1L, O1H
+ srl O1L, O1L, $r2
+ srl O1H, O1H, $r2
+ subri $r2, $r2, #0x20
+ sll P1L, P1L, $r2
+ or O1L, O1L, P1L
+.LL16:
+ sltsi $r15, P1H, #0
+ beqzs8 .LCret
+
+ subri O1H, O1H, #0
+ beqz O1L, .LL17
+ subri O1L, O1L, #0
+ subi45 O1H, #1
+.LL17:
+
+.LCret:
+ move P1L, O1L
+ move P1H, O1H
+
+.LC999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+
+.LCnaninf:
+ sltsi $r15, P1H, #0
+ bnezs8 .LCret3
+ subri $r15, $r5, #0x7ff
+ bnezs8 .Li5
+ slli $r6, O1H, #1
+ or $r6, $r6, O1L
+ beqz $r6, .Li5
+
+.LCret3:
+ move O1H, #0x80000000
+ move O1L, #0
+ j .LCret
+.Li5:
+ move O1H, #0x7fffffff
+ move O1L, #-1
+ j .LCret
+ .size __fixdfdi, .-__fixdfdi
+#endif /* L_fixdfdi */
+
+
+
+#ifdef L_fixunssfsi
+
+ .global __fixunssfsi
+ .type __fixunssfsi, @function
+__fixunssfsi:
+ push $lp
+
+ slli $r1, $r0, #8
+ move $r3, #0x80000000
+ or $r1, $r1, $r3
+ srli $r3, $r0, #23
+ andi $r3, $r3, #0xff
+ subri $r2, $r3, #0x9e
+ sltsi $r15, $r2, #0
+ bnezs8 .LLspec
+ sltsi $r15, $r2, #0x20
+ bnezs8 .Li45
+ move $r0, #0
+ j .LL999
+.Li45:
+ srl $r1, $r1, $r2
+ sltsi $r15, $r0, #0
+ beqzs8 .Li46
+ subri $r1, $r1, #0
+.Li46:
+ move $r0, $r1
+
+.LL999:
+ pop $lp
+ ret5 $lp
+
+.LLspec:
+ move $r3, #0x7f800000
+ slt $r15, $r3, $r0
+ beqzs8 .Li47
+ move $r0, #0x80000000
+ j .LL999
+.Li47:
+ move $r0, #-1
+ j .LL999
+ .size __fixunssfsi, .-__fixunssfsi
+#endif /* L_fixunssfsi */
+
+
+
+#ifdef L_fixunsdfsi
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+#else
+ #define P1H $r0
+ #define P1L $r1
+#endif
+ .text
+ .align 1
+ .global __fixunsdfsi
+ .type __fixunsdfsi, @function
+__fixunsdfsi:
+ push $lp
+ pushm $r6, $r6
+
+ slli $r3, P1H, #11
+ srli $r6, P1L, #21
+ or $r3, $r3, $r6
+ move $r6, #0x80000000
+ or $r3, $r3, $r6
+ slli $r6, P1H, #1
+ srli $r6, $r6, #21
+ subri $r2, $r6, #0x41e
+ sltsi $r15, $r2, #0
+ bnezs8 .LNnaninf
+ move $r6, #0x20
+ slt $r15, $r2, $r6
+ bnezs8 .LL73
+ move $r3, #0
+.LL73:
+ srl $r3, $r3, $r2
+ sltsi $r15, P1H, #0
+ beqzs8 .Li53
+ subri $r3, $r3, #0
+.Li53:
+ move $r0, $r3
+
+.LN999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+
+.LNnaninf:
+ beqz P1L, .Li54
+ ori P1H, P1H, #1
+.Li54:
+ move $r6, #0x7ff00000
+ slt $r15, $r6, P1H
+ beqzs8 .Li55
+ move $r0, #0x80000000
+ j .LN999
+.Li55:
+ move $r0, #-1
+ j .LN999
+ .size __fixunsdfsi, .-__fixunsdfsi
+#endif /* L_fixunsdfsi */
+
+
+
+#ifdef L_fixunssfdi
+
+#ifndef __big_endian__
+ #define O1L $r1
+ #define O1H $r2
+#else
+ #define O1H $r1
+ #define O1L $r2
+#endif
+ .text
+ .align 1
+ .global __fixunssfdi
+ .type __fixunssfdi, @function
+__fixunssfdi:
+ push $lp
+
+ srli $r3, $r0, #23
+ andi $r3, $r3, #0xff
+ slli O1H, $r0, #8
+ move $r5, #0x80000000
+ or O1H, O1H, $r5
+ move O1L, #0
+ sltsi $r15, $r3, #0xbe
+ beqzs8 .LDinfnan
+ subri $r3, $r3, #0xbe
+.LL12:
+ move $r5, #0x20
+ slt $r15, $r3, $r5
+ bnezs8 .LL13
+ move O1L, O1H
+ move O1H, #0
+ addi $r3, $r3, #0xffffffe0
+ bnez O1L, .LL12
+.LL13:
+ beqz $r3, .LL14
+ move $r4, O1H
+ srl O1L, O1L, $r3
+ srl O1H, O1H, $r3
+ subri $r3, $r3, #0x20
+ sll $r4, $r4, $r3
+ or O1L, O1L, $r4
+.LL14:
+ sltsi $r15, $r0, #0
+ beqzs8 .LDret
+
+ subri O1H, O1H, #0
+ beqz O1L, .LL15
+ subri O1L, O1L, #0
+ subi45 O1H, #1
+.LL15:
+
+.LDret:
+ move $r0, $r1
+ move $r1, $r2
+
+.LD999:
+ pop $lp
+ ret5 $lp
+
+.LDinfnan:
+ move O1H, #0x80000000
+ move O1L, #0
+ j .LDret
+ .size __fixunssfdi, .-__fixunssfdi
+#endif /* L_fixunssfdi */
+
+
+
+#ifdef L_fixunsdfdi
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define O1L $r3
+ #define O1H $r4
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define O1H $r3
+ #define O1L $r4
+#endif
+ .text
+ .align 1
+ .global __fixunsdfdi
+ .type __fixunsdfdi, @function
+__fixunsdfdi:
+ push $lp
+ pushm $r6, $r6
+
+ slli $r5, P1H, #1
+ srli $r5, $r5, #21
+ slli O1H, P1H, #11
+ srli $r6, P1L, #21
+ or O1H, O1H, $r6
+ slli O1L, P1L, #11
+ move $r6, #0x80000000
+ or O1H, O1H, $r6
+ slti $r15, $r5, #0x43e
+ beqzs8 .LDnaninf
+ subri $r2, $r5, #0x43e
+.LL18:
+ move $r6, #0x20
+ slt $r15, $r2, $r6
+ bnezs8 .LL19
+ move O1L, O1H
+ move O1H, #0
+ addi $r2, $r2, #0xffffffe0
+ bnez O1L, .LL18
+.LL19:
+ beqz $r2, .LL20
+ move P1L, O1H
+ srl O1L, O1L, $r2
+ srl O1H, O1H, $r2
+ subri $r2, $r2, #0x20
+ sll P1L, P1L, $r2
+ or O1L, O1L, P1L
+.LL20:
+ sltsi $r15, P1H, #0
+ beqzs8 .LDret
+
+ subri O1H, O1H, #0
+ beqz O1L, .LL21
+ subri O1L, O1L, #0
+ subi45 O1H, #1
+.LL21:
+
+.LDret:
+ move P1L, O1L
+ move P1H, O1H
+
+.LD999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+
+.LDnaninf:
+ move O1H, #0x80000000
+ move O1L, #0
+ j .LDret
+ .size __fixunsdfdi, .-__fixunsdfdi
+#endif /* L_fixunsdfdi */
+
+
+
+#ifdef L_si_to_sf
+
+ .text
+ .align 1
+ .global __floatsisf
+ .type __floatsisf, @function
+__floatsisf:
+ push $lp
+
+ move $r4, #0x80000000
+ and $r2, $r0, $r4
+ beqz $r0, .Li39
+ sltsi $r15, $r0, #0
+ beqzs8 .Li40
+ subri $r0, $r0, #0
+.Li40:
+ move $r1, #0x9e
+#ifdef __NDS32_PERF_EXT__
+ clz $r3, $r0
+#else
+ pushm $r0, $r2
+ pushm $r4, $r5
+ bal __clzsi2
+ move $r3, $r0
+ popm $r4, $r5
+ popm $r0, $r2
+#endif
+ sub $r1, $r1, $r3
+ sll $r0, $r0, $r3
+
+ #ADD($r0, $0x80)
+ move $r15, #0x80
+ add $r0, $r0, $r15
+ slt $r15, $r0, $r15
+
+ #ADDC($r1, $0x0)
+ add $r1, $r1, $r15
+ srai $r4, $r0, #8
+ andi $r4, $r4, #1
+ sub $r0, $r0, $r4
+ slli $r0, $r0, #1
+ srli $r0, $r0, #9
+ slli $r4, $r1, #23
+ or $r0, $r0, $r4
+.Li39:
+ or $r0, $r0, $r2
+
+.LH999:
+ pop $lp
+ ret5 $lp
+ .size __floatsisf, .-__floatsisf
+#endif /* L_si_to_sf */
+
+
+
+#ifdef L_si_to_df
+
+#ifndef __big_endian__
+ #define O1L $r1
+ #define O1H $r2
+ #define O2L $r4
+ #define O2H $r5
+#else
+ #define O1H $r1
+ #define O1L $r2
+ #define O2H $r4
+ #define O2L $r5
+#endif
+ .text
+ .align 1
+ .global __floatsidf
+ .type __floatsidf, @function
+__floatsidf:
+ push $lp
+ pushm $r6, $r6
+
+ move O1L, #0
+ move O2H, O1L
+ move $r3, O1L
+ move O1H, $r0
+ beqz O1H, .Li39
+ sltsi $r15, O1H, #0
+ beqzs8 .Li40
+ move O2H, #0x80000000
+
+ subri O1H, O1H, #0
+ beqz O1L, .LL71
+ subri O1L, O1L, #0
+ subi45 O1H, #1
+.LL71:
+.Li40:
+ move $r3, #0x41e
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r4, $r2
+#else
+ pushm $r0, $r3
+ push $r5
+ move $r0, $r2
+ bal __clzsi2
+ move $r4, $r0
+ pop $r5
+ popm $r0, $r3
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r5, $r1
+#else
+ pushm $r0, $r4
+ move $r0, $r1
+ bal __clzsi2
+ move $r5, $r0
+ popm $r0, $r4
+#endif
+#endif /* __big_endian__ */
+ sub $r3, $r3, O2L
+ sll O1H, O1H, O2L
+.Li39:
+ srli O2L, O1L, #11
+ slli $r6, O1H, #21
+ or O2L, O2L, $r6
+ slli $r6, O1H, #1
+ srli $r6, $r6, #12
+ or O2H, O2H, $r6
+ slli $r6, $r3, #20
+ or O2H, O2H, $r6
+ move $r0, $r4
+ move $r1, $r5
+
+.LH999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+ .size __floatsidf, .-__floatsidf
+#endif /* L_si_to_df */
+
+
+
+#ifdef L_floatdisf
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+#endif
+ .text
+ .align 1
+ .global __floatdisf
+ .type __floatdisf, @function
+__floatdisf:
+ push $lp
+ pushm $r6, $r7
+
+ move $r7, #0x80000000
+ and $r5, P1H, $r7
+ move P2H, P1H
+ move P2L, P1L
+ or $r7, P1H, P1L
+ beqz $r7, .Li1
+ sltsi $r15, P1H, #0
+ beqzs8 .Li2
+
+ subri P2H, P2H, #0
+ beqz P2L, .LL1
+ subri P2L, P2L, #0
+ subi45 P2H, #1
+.LL1:
+.Li2:
+ move $r4, #0xbe
+
+
+ #NORMd($r2, $r6, P1L)
+ bnez P2H, .LL2
+ bnez P2L, .LL3
+ move $r4, #0
+ j .LL4
+.LL3:
+ move P2H, P2L
+ move P2L, #0
+ move $r6, #32
+ sub $r4, $r4, $r6
+.LL2:
+#ifdef __NDS32_PERF_EXT__
+ clz $r6, P2H
+#else
+ pushm $r0, $r5
+ move $r0, P2H
+ bal __clzsi2
+ move $r6, $r0
+ popm $r0, $r5
+#endif
+ beqz $r6, .LL4
+ sub $r4, $r4, $r6
+ subri P1L, $r6, #32
+ srl P1L, P2L, P1L
+ sll P2L, P2L, $r6
+ sll P2H, P2H, $r6
+ or P2H, P2H, P1L
+.LL4:
+ #NORMd End
+
+ beqz P2L, .Li3
+ ori P2H, P2H, #1
+.Li3:
+ #ADD(P2H, $0x80)
+ move $r15, #0x80
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+
+ #ADDC($r4, $0x0)
+ add $r4, $r4, $r15
+ srli $r7, P2H, #8
+ andi $r7, $r7, #1
+ sub P2H, P2H, $r7
+ slli P2H, P2H, #1
+ srli P2H, P2H, #9
+ slli $r7, $r4, #23
+ or P2H, P2H, $r7
+.Li1:
+ or $r0, P2H, $r5
+
+.LA999:
+ popm $r6, $r7
+ pop $lp
+ ret5 $lp
+ .size __floatdisf, .-__floatdisf
+#endif /* L_floatdisf */
+
+
+
+#ifdef L_floatdidf
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+ #define O1L $r5
+ #define O1H $r6
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+ #define O1H $r5
+ #define O1L $r6
+#endif
+ .text
+ .align 1
+ .global __floatdidf
+ .type __floatdidf, @function
+__floatdidf:
+ push $lp
+ pushm $r6, $r8
+
+ move $r4, #0
+ move $r7, $r4
+ move P2H, P1H
+ move P2L, P1L
+ or $r8, P1H, P1L
+ beqz $r8, .Li1
+ move $r4, #0x43e
+ sltsi $r15, P1H, #0
+ beqzs8 .Li2
+ move $r7, #0x80000000
+
+ subri P2H, P2H, #0
+ beqz P2L, .LL1
+ subri P2L, P2L, #0
+ subi45 P2H, #1
+.LL1:
+
+.Li2:
+ #NORMd($r2, O1H, O1L)
+ bnez P2H, .LL2
+ bnez P2L, .LL3
+ move $r4, #0
+ j .LL4
+.LL3:
+ move P2H, P2L
+ move P2L, #0
+ move O1H, #32
+ sub $r4, $r4, O1H
+.LL2:
+#ifdef __NDS32_PERF_EXT__
+ clz O1H, P2H
+#else /* not __NDS32_PERF_EXT__ */
+/*
+ Replace clz with function call.
+ clz O1H, P2H
+ EL: clz $r6, $r3
+ EB: clz $r5, $r2
+*/
+#ifndef __big_endian__
+ pushm $r0, $r5
+ move $r0, $r3
+ bal __clzsi2
+ move $r6, $r0
+ popm $r0, $r5
+#else
+ pushm $r0, $r4
+ move $r0, $r2
+ bal __clzsi2
+ move $r5, $r0
+ popm $r0, $r4
+#endif
+#endif /* not __NDS32_PERF_EXT__ */
+ beqz O1H, .LL4
+ sub $r4, $r4, O1H
+ subri O1L, O1H, #32
+ srl O1L, P2L, O1L
+ sll P2L, P2L, O1H
+ sll P2H, P2H, O1H
+ or P2H, P2H, O1L
+.LL4:
+ #NORMd End
+
+ #ADD(P2L, $0x400)
+ move $r15, #0x400
+ add P2L, P2L, $r15
+ slt $r15, P2L, $r15
+
+
+ #ADDCC(P2H, $0x0)
+ beqzs8 .LL7
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+.LL7:
+
+ #ADDC($r4, $0x0)
+ add $r4, $r4, $r15
+ srli $r8, P2L, #11
+ andi $r8, $r8, #1
+ sub P2L, P2L, $r8
+.Li1:
+ srli O1L, P2L, #11
+ slli $r8, P2H, #21
+ or O1L, O1L, $r8
+ slli O1H, P2H, #1
+ srli O1H, O1H, #12
+ slli $r8, $r4, #20
+ or O1H, O1H, $r8
+ or O1H, O1H, $r7
+ move P1L, O1L
+ move P1H, O1H
+
+.LA999:
+ popm $r6, $r8
+ pop $lp
+ ret5 $lp
+ .size __floatdidf, .-__floatdidf
+#endif /* L_floatdidf */
+
+
+
+#ifdef L_floatunsisf
+
+ .text
+ .align 1
+ .global __floatunsisf
+ .type __floatunsisf, @function
+__floatunsisf:
+ push $lp
+
+ beqz $r0, .Li41
+ move $r2, #0x9e
+#ifdef __NDS32_PERF_EXT__
+ clz $r1, $r0
+#else
+ push $r0
+ pushm $r2, $r5
+ bal __clzsi2
+ move $r1, $r0
+ popm $r2, $r5
+ pop $r0
+#endif
+
+ sub $r2, $r2, $r1
+ sll $r0, $r0, $r1
+
+ #ADD($r0, $0x80)
+ move $r15, #0x80
+ add $r0, $r0, $r15
+ slt $r15, $r0, $r15
+
+ #ADDC($r2, $0x0)
+ add $r2, $r2, $r15
+ srli $r3, $r0, #8
+ andi $r3, $r3, #1
+ sub $r0, $r0, $r3
+ slli $r0, $r0, #1
+ srli $r0, $r0, #9
+ slli $r3, $r2, #23
+ or $r0, $r0, $r3
+
+.Li41:
+.LI999:
+ pop $lp
+ ret5 $lp
+ .size __floatunsisf, .-__floatunsisf
+#endif /* L_floatunsisf */
+
+
+
+#ifdef L_floatunsidf
+
+#ifndef __big_endian__
+ #define O1L $r1
+ #define O1H $r2
+ #define O2L $r4
+ #define O2H $r5
+#else
+ #define O1H $r1
+ #define O1L $r2
+ #define O2H $r4
+ #define O2L $r5
+#endif
+ .text
+ .align 1
+ .global __floatunsidf
+ .type __floatunsidf, @function
+__floatunsidf:
+ push $lp
+ pushm $r6, $r6
+
+ move O1L, #0
+ move $r3, O1L
+ move O1H, $r0
+ beqz O1H, .Li41
+ move $r3, #0x41e
+#ifndef __big_endian__
+#ifdef __NDS32_PERF_EXT__
+ clz $r5, $r2
+#else
+ pushm $r0, $r4
+ move $r0, $r2
+ bal __clzsi2
+ move $r5, $r0
+ popm $r0, $r4
+#endif
+#else /* __big_endian__ */
+#ifdef __NDS32_PERF_EXT__
+ clz $r4, $r1
+#else
+ pushm $r0, $r3
+ push $r5
+ move $r0, $r1
+ bal __clzsi2
+ move $r4, $r0
+ pop $r5
+ popm $r0, $r3
+#endif
+#endif /* __big_endian__ */
+ sub $r3, $r3, O2H
+ sll O1H, O1H, O2H
+.Li41:
+ srli O2L, O1L, #11
+ slli $r6, O1H, #21
+ or O2L, O2L, $r6
+ slli O2H, O1H, #1
+ srli O2H, O2H, #12
+ slli $r6, $r3, #20
+ or O2H, O2H, $r6
+ move $r0, $r4
+ move $r1, $r5
+
+.LI999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+ .size __floatunsidf, .-__floatunsidf
+#endif /* L_floatunsidf */
+
+
+
+#ifdef L_floatundisf
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+#endif
+ .text
+ .align 1
+ .global __floatundisf
+ .type __floatundisf, @function
+__floatundisf:
+ push $lp
+ pushm $r6, $r6
+
+ move P2H, P1H
+ move P2L, P1L
+ or $r6, P1H, P1L
+ beqz $r6, .Li4
+ move $r4, #0xbe
+
+
+ #NORMd($r2, $r5, P1L)
+ bnez P2H, .LL5
+ bnez P2L, .LL6
+ move $r4, #0
+ j .LL7
+.LL6:
+ move P2H, P2L
+ move P2L, #0
+ move $r5, #32
+ sub $r4, $r4, $r5
+.LL5:
+#ifdef __NDS32_PERF_EXT__
+ clz $r5, P2H
+#else
+ pushm $r0, $r4
+ move $r0, P2H
+ bal __clzsi2
+ move $r5, $r0
+ popm $r0, $r4
+#endif
+ beqz $r5, .LL7
+ sub $r4, $r4, $r5
+ subri P1L, $r5, #32
+ srl P1L, P2L, P1L
+ sll P2L, P2L, $r5
+ sll P2H, P2H, $r5
+ or P2H, P2H, P1L
+.LL7:
+ #NORMd End
+
+ beqz P2L, .Li5
+ ori P2H, P2H, #1
+.Li5:
+ #ADD(P2H, $0x80)
+ move $r15, #0x80
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+
+ #ADDC($r4, $0x0)
+ add $r4, $r4, $r15
+ srli $r6, P2H, #8
+ andi $r6, $r6, #1
+ sub P2H, P2H, $r6
+ slli P2H, P2H, #1
+ srli P2H, P2H, #9
+ slli $r6, $r4, #23
+ or P2H, P2H, $r6
+.Li4:
+ move $r0, P2H
+
+.LB999:
+ popm $r6, $r6
+ pop $lp
+ ret5 $lp
+ .size __floatundisf, .-__floatundisf
+#endif /* L_floatundisf */
+
+
+
+#ifdef L_floatundidf
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+ #define O1L $r5
+ #define O1H $r6
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+ #define O1H $r5
+ #define O1L $r6
+#endif
+ .text
+ .align 1
+ .global __floatundidf
+ .type __floatundidf, @function
+__floatundidf:
+ push $lp
+ pushm $r6, $r7
+
+ move $r4, #0
+ move P2H, P1H
+ move P2L, P1L
+ or $r7, P1H, P1L
+ beqz $r7, .Li3
+ move $r4, #0x43e
+
+
+ #NORMd($r2, O1H, O1L)
+ bnez P2H, .LL8
+ bnez P2L, .LL9
+ move $r4, #0
+ j .LL10
+.LL9:
+ move P2H, P2L
+ move P2L, #0
+ move O1H, #32
+ sub $r4, $r4, O1H
+.LL8:
+#ifdef __NDS32_PERF_EXT__
+ clz O1H, P2H
+#else /* not __NDS32_PERF_EXT__ */
+/*
+ Replace clz with function call.
+ clz O1H, P2H
+ EL: clz $r6, $r3
+ EB: clz $r5, $r2
+*/
+#ifndef __big_endian__
+ pushm $r0, $r5
+ move $r0, $r3
+ bal __clzsi2
+ move $r6, $r0
+ popm $r0, $r5
+#else
+ pushm $r0, $r4
+ move $r0, $r2
+ bal __clzsi2
+ move $r5, $r0
+ popm $r0, $r4
+#endif
+#endif /* not __NDS32_PERF_EXT__ */
+ beqz O1H, .LL10
+ sub $r4, $r4, O1H
+ subri O1L, O1H, #32
+ srl O1L, P2L, O1L
+ sll P2L, P2L, O1H
+ sll P2H, P2H, O1H
+ or P2H, P2H, O1L
+.LL10:
+ #NORMd End
+
+ #ADD(P2L, $0x400)
+ move $r15, #0x400
+ add P2L, P2L, $r15
+ slt $r15, P2L, $r15
+
+
+ #ADDCC(P2H, $0x0)
+ beqzs8 .LL13
+ add P2H, P2H, $r15
+ slt $r15, P2H, $r15
+.LL13:
+
+ #ADDC($r4, $0x0)
+ add $r4, $r4, $r15
+ srli $r7, P2L, #11
+ andi $r7, $r7, #1
+ sub P2L, P2L, $r7
+.Li3:
+ srli O1L, P2L, #11
+ slli $r7, P2H, #21
+ or O1L, O1L, $r7
+ slli O1H, P2H, #1
+ srli O1H, O1H, #12
+ slli $r7, $r4, #20
+ or O1H, O1H, $r7
+ move P1L, O1L
+ move P1H, O1H
+
+.LB999:
+ popm $r6, $r7
+ pop $lp
+ ret5 $lp
+ .size __floatundidf, .-__floatundidf
+#endif /* L_floatundidf */
+
+
+
+#ifdef L_compare_sf
+
+ .text
+ .align 1
+ .global __cmpsf2
+ .type __cmpsf2, @function
+__cmpsf2:
+ .global __eqsf2
+ .type __eqsf2, @function
+__eqsf2:
+ .global __ltsf2
+ .type __ltsf2, @function
+__ltsf2:
+ .global __lesf2
+ .type __lesf2, @function
+__lesf2:
+ .global __nesf2
+ .type __nesf2, @function
+__nesf2:
+ move $r4, #1
+ j .LA
+
+ .global __gesf2
+ .type __gesf2, @function
+__gesf2:
+ .global __gtsf2
+ .type __gtsf2, @function
+__gtsf2:
+ move $r4, #-1
+.LA:
+ push $lp
+
+ slli $r2, $r0, #1
+ slli $r3, $r1, #1
+ or $r5, $r2, $r3
+ beqz $r5, .LMequ
+ move $r5, #0xff000000
+ slt $r15, $r5, $r2
+ bnezs8 .LMnan
+ slt $r15, $r5, $r3
+ bnezs8 .LMnan
+ srli $r2, $r2, #1
+ sltsi $r15, $r0, #0
+ beqzs8 .Li48
+ subri $r2, $r2, #0
+.Li48:
+ srli $r3, $r3, #1
+ sltsi $r15, $r1, #0
+ beqzs8 .Li49
+ subri $r3, $r3, #0
+.Li49:
+ slts $r15, $r2, $r3
+ beqzs8 .Li50
+ move $r0, #-1
+ j .LM999
+.Li50:
+ slts $r15, $r3, $r2
+ beqzs8 .LMequ
+ move $r0, #1
+ j .LM999
+
+.LMequ:
+ move $r0, #0
+
+.LM999:
+ pop $lp
+ ret5 $lp
+
+.LMnan:
+ move $r0, $r4
+ j .LM999
+ .size __cmpsf2, .-__cmpsf2
+ .size __eqsf2, .-__eqsf2
+ .size __ltsf2, .-__ltsf2
+ .size __lesf2, .-__lesf2
+ .size __nesf2, .-__nesf2
+ .size __gesf2, .-__gesf2
+ .size __gtsf2, .-__gtsf2
+#endif /* L_compare_sf */
+
+
+
+#ifdef L_compare_df
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+#endif
+ .text
+ .align 1
+ .global __cmpdf2
+ .type __cmpdf2, @function
+__cmpdf2:
+ .global __eqdf2
+ .type __eqdf2, @function
+__eqdf2:
+ .global __ltdf2
+ .type __ltdf2, @function
+__ltdf2:
+ .global __ledf2
+ .type __ledf2, @function
+__ledf2:
+ .global __nedf2
+ .type __nedf2, @function
+__nedf2:
+ move $r5, #1
+ j 1f
+
+ .global __gtdf2
+ .type __gtdf2, @function
+__gtdf2:
+ .global __gedf2
+ .type __gedf2, @function
+__gedf2:
+ move $r5, #-1
+1:
+ push $lp
+ pushm $r6, $r7
+
+ slli $r6, P1H, #1
+ slli $r7, P2H, #1
+ or $r7, $r7, P1L
+ or $r7, $r7, P2L
+ or $r6, $r6, $r7
+ bnez $r6, .Li56
+ move $r0, #0
+ j .LO999
+.Li56:
+ slli $r4, P1H, #1
+ beqz P1L, .Li57
+ addi $r4, $r4, #1
+.Li57:
+ move $r6, #0xffe00000
+ slt $r15, $r6, $r4
+ bnezs8 .LOnan
+ slli $r4, P2H, #1
+ beqz P2L, .Li58
+ addi $r4, $r4, #1
+.Li58:
+ move $r6, #0xffe00000
+ slt $r15, $r6, $r4
+ bnezs8 .LOnan
+ sltsi $r15, P1H, #0
+ beqzs8 .Li59
+ sltsi $r15, P2H, #0
+ bnezs8 .Li60
+ move $r0, #-1
+ j .LO999
+.Li60:
+ #SUB(P1L, P2L)
+ move $r15, P1L
+ sub P1L, P1L, P2L
+ slt $r15, $r15, P1L
+
+
+ #SUBCC(P1H, P2H)
+ beqzs8 .LL74
+ move $r15, P1H
+ sub P1H, P1H, P2H
+ slt $r15, $r15, P1H
+ beqzs8 .LL75
+ subi333 P1H, P1H, #1
+ j .LL76
+.LL75:
+ move $r15, P1H
+ subi333 P1H, P1H, #1
+ slt $r15, $r15, P1H
+ j .LL76
+.LL74:
+ move $r15, P1H
+ sub P1H, P1H, P2H
+ slt $r15, $r15, P1H
+.LL76:
+
+ beqzs8 .Li61
+ move $r0, #1
+ j .LO999
+.Li61:
+ or $r6, P1H, P1L
+ beqz $r6, .Li62
+ move $r0, #-1
+ j .LO999
+.Li62:
+ move $r0, #0
+ j .LO999
+.Li59:
+ sltsi $r15, P2H, #0
+ beqzs8 .Li63
+ move $r0, #1
+ j .LO999
+.Li63:
+ #SUB(P1L, P2L)
+ move $r15, P1L
+ sub P1L, P1L, P2L
+ slt $r15, $r15, P1L
+
+
+ #SUBCC(P1H, P2H)
+ beqzs8 .LL77
+ move $r15, P1H
+ sub P1H, P1H, P2H
+ slt $r15, $r15, P1H
+ beqzs8 .LL78
+ subi333 P1H, P1H, #1
+ j .LL79
+.LL78:
+ move $r15, P1H
+ subi333 P1H, P1H, #1
+ slt $r15, $r15, P1H
+ j .LL79
+.LL77:
+ move $r15, P1H
+ sub P1H, P1H, P2H
+ slt $r15, $r15, P1H
+.LL79:
+
+ beqzs8 .Li64
+ move $r0, #-1
+ j .LO999
+.Li64:
+ or $r6, P1H, P1L
+ beqz $r6, .Li65
+ move $r0, #1
+ j .LO999
+.Li65:
+ move $r0, #0
+
+.LO999:
+ popm $r6, $r7
+ pop $lp
+ ret5 $lp
+
+.LOnan:
+ move $r0, $r5
+ j .LO999
+ .size __cmpdf2, .-__cmpdf2
+ .size __eqdf2, .-__eqdf2
+ .size __ltdf2, .-__ltdf2
+ .size __ledf2, .-__ledf2
+ .size __nedf2, .-__nedf2
+ .size __gtdf2, .-__gtdf2
+ .size __gedf2, .-__gedf2
+#endif /* L_compare_df */
+
+
+
+#ifdef L_unord_sf
+
+ .text
+ .align 1
+ .global __unordsf2
+ .type __unordsf2, @function
+__unordsf2:
+ push $lp
+
+ slli $r2, $r0, #1
+ move $r3, #0xff000000
+ slt $r15, $r3, $r2
+ beqzs8 .Li52
+ move $r0, #1
+ j .LP999
+.Li52:
+ slli $r2, $r1, #1
+ move $r3, #0xff000000
+ slt $r15, $r3, $r2
+ beqzs8 .Li53
+ move $r0, #1
+ j .LP999
+.Li53:
+ move $r0, #0
+
+.LP999:
+ pop $lp
+ ret5 $lp
+ .size __unordsf2, .-__unordsf2
+#endif /* L_unord_sf */
+
+
+
+#ifdef L_unord_df
+
+#ifndef __big_endian__
+ #define P1L $r0
+ #define P1H $r1
+ #define P2L $r2
+ #define P2H $r3
+#else
+ #define P1H $r0
+ #define P1L $r1
+ #define P2H $r2
+ #define P2L $r3
+#endif
+ .text
+ .align 1
+ .global __unorddf2
+ .type __unorddf2, @function
+__unorddf2:
+ push $lp
+
+ slli $r4, P1H, #1
+ beqz P1L, .Li66
+ addi $r4, $r4, #1
+.Li66:
+ move $r5, #0xffe00000
+ slt $r15, $r5, $r4
+ beqzs8 .Li67
+ move $r0, #1
+ j .LR999
+.Li67:
+ slli $r4, P2H, #1
+ beqz P2L, .Li68
+ addi $r4, $r4, #1
+.Li68:
+ move $r5, #0xffe00000
+ slt $r15, $r5, $r4
+ beqzs8 .Li69
+ move $r0, #1
+ j .LR999
+.Li69:
+ move $r0, #0
+
+.LR999:
+ pop $lp
+ ret5 $lp
+ .size __unorddf2, .-__unorddf2
+#endif /* L_unord_df */
+/* ------------------------------------------- */
+/* DPBIT floating point operations for libgcc */
+/* ------------------------------------------- */
diff --git libgcc/config/nds32/lib1asmsrc-newlib.S libgcc/config/nds32/lib1asmsrc-newlib.S
new file mode 100644
index 0000000..3488118
--- /dev/null
+++ libgcc/config/nds32/lib1asmsrc-newlib.S
@@ -0,0 +1,207 @@
+/* newlib libgcc routines of Andes NDS32 cpu for GNU compiler
+ Copyright (C) 2012-2013 Free Software Foundation, Inc.
+ Contributed by Andes Technology Corporation.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+ .section .mdebug.abi_nds32
+ .previous
+
+#ifdef L_divsi3
+
+ .text
+ .align 2
+ .globl __divsi3
+ .type __divsi3, @function
+__divsi3:
+ movi $r5, 0 ! res = 0
+ xor $r4, $r0, $r1 ! neg
+ bltz $r0, .L1
+ bltz $r1, .L2
+.L3:
+ movi $r2, 1 ! bit = 1
+ slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor
+ beqz $r3, .L5
+ bltz $r1, .L5
+
+.L4:
+ slli $r2, $r2, 1
+ beqz $r2, .L6
+ slli $r1, $r1, 1
+ slt $r3, $r1, $r0
+ beqz $r3, .L5
+ bgez $r1, .L4
+
+.L5:
+ slt $r3, $r0, $r1
+ bnez $r3, .L8
+ sub $r0, $r0, $r1
+ or $r5, $r5, $r2
+.L8:
+ srli $r1, $r1, 1
+ srli $r2, $r2, 1
+ bnez $r2, .L5
+.L6:
+ bgez $r4, .L7
+ subri $r5, $r5, 0 ! negate if $r4 < 0
+.L7:
+ move $r0, $r5
+ ret
+.L1:
+ subri $r0, $r0, 0 ! change neg to pos
+ bgez $r1, .L3
+.L2:
+ subri $r1, $r1, 0 ! change neg to pos
+ j .L3
+ .size __divsi3, .-__divsi3
+
+#endif /* L_divsi3 */
+
+
+#ifdef L_modsi3
+
+ .text
+ .align 2
+ .globl __modsi3
+ .type __modsi3, @function
+__modsi3:
+ movi $r5, 0 ! res = 0
+ move $r4, $r0 ! neg
+ bltz $r0, .L1
+ bltz $r1, .L2
+.L3:
+ movi $r2, 1 ! bit = 1
+ slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor
+ beqz $r3, .L5
+ bltz $r1, .L5
+
+.L4:
+ slli $r2, $r2, 1
+ beqz $r2, .L6
+ slli $r1, $r1, 1
+ slt $r3, $r1, $r0
+ beqz $r3, .L5
+ bgez $r1, .L4
+
+.L5:
+ slt $r3, $r0, $r1
+ bnez $r3, .L8
+ sub $r0, $r0, $r1
+ or $r5, $r5, $r2
+.L8:
+ srli $r1, $r1, 1
+ srli $r2, $r2, 1
+ bnez $r2, .L5
+.L6:
+ bgez $r4, .L7
+ subri $r0, $r0, 0 ! negate if $r4 < 0
+.L7:
+ ret
+.L1:
+ subri $r0, $r0, 0 ! change neg to pos
+ bgez $r1, .L3
+.L2:
+ subri $r1, $r1, 0 ! change neg to pos
+ j .L3
+ .size __modsi3, .-__modsi3
+
+#endif /* L_modsi3 */
+
+
+#ifdef L_udivsi3
+
+ .text
+ .align 2
+ .globl __udivsi3
+ .type __udivsi3, @function
+__udivsi3:
+ movi $r5, 0 ! res = 0
+ movi $r2, 1 ! bit = 1
+ slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor
+ beqz $r3, .L5
+ bltz $r1, .L5
+
+.L4:
+ slli $r2, $r2, 1
+ beqz $r2, .L6
+ slli $r1, $r1, 1
+ slt $r3, $r1, $r0
+ beqz $r3, .L5
+ bgez $r1, .L4
+
+.L5:
+ slt $r3, $r0, $r1
+ bnez $r3, .L8
+ sub $r0, $r0, $r1
+ or $r5, $r5, $r2
+.L8:
+ srli $r1, $r1, 1
+ srli $r2, $r2, 1
+ bnez $r2, .L5
+.L6:
+ move $r0, $r5
+ ret
+ .size __udivsi3, .-__udivsi3
+
+#endif /* L_udivsi3 */
+
+
+#ifdef L_umodsi3
+
+ .text
+ .align 2
+ .globl __umodsi3
+ .type __umodsi3, @function
+__umodsi3:
+ movi $r5, 0 ! res = 0
+ movi $r2, 1 ! bit = 1
+ slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor
+ beqz $r3, .L5
+ bltz $r1, .L5
+
+.L4:
+ slli $r2, $r2, 1
+ beqz $r2, .L6
+ slli $r1, $r1, 1
+ slt $r3, $r1, $r0
+ beqz $r3, .L5
+ bgez $r1, .L4
+
+.L5:
+ slt $r3, $r0, $r1
+ bnez $r3, .L8
+ sub $r0, $r0, $r1
+ or $r5, $r5, $r2
+.L8:
+ srli $r1, $r1, 1
+ srli $r2, $r2, 1
+ bnez $r2, .L5
+.L6:
+ ret
+ .size __umodsi3, .-__umodsi3
+
+#endif /* L_umodsi3 */
+
+/* ----------------------------------------------------------- */
diff --git libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c
new file mode 100644
index 0000000..a83d20a
--- /dev/null
+++ libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c
@@ -0,0 +1,41 @@
+/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
+ Copyright (C) 2012-2013 Free Software Foundation, Inc.
+ Contributed by Andes Technology Corporation.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+extern int __clzsi2 (int val);
+int
+__clzdi2 (long long val)
+{
+ if (val >> 32)
+ {
+ return __clzsi2 (val >> 32);
+ }
+ else
+ {
+ return __clzsi2 (val) + 32;
+ }
+}
diff --git libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c
new file mode 100644
index 0000000..6b0ce8e
--- /dev/null
+++ libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c
@@ -0,0 +1,52 @@
+/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler
+ Copyright (C) 2012-2013 Free Software Foundation, Inc.
+ Contributed by Andes Technology Corporation.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+int
+__clzsi2 (int val)
+{
+ int i = 32;
+ int j = 16;
+ int temp;
+
+ for (; j; j >>= 1)
+ {
+ if (temp = val >> j)
+ {
+ if (j == 1)
+ {
+ return (i - 2);
+ }
+ else
+ {
+ i -= j;
+ val = temp;
+ }
+ }
+ }
+ return (i - val);
+}
diff --git libgcc/config/nds32/sfp-machine.h libgcc/config/nds32/sfp-machine.h
new file mode 100644
index 0000000..99d3ae3
--- /dev/null
+++ libgcc/config/nds32/sfp-machine.h
@@ -0,0 +1,61 @@
+#define _FP_W_TYPE_SIZE 32
+#define _FP_W_TYPE unsigned long
+#define _FP_WS_TYPE signed long
+#define _FP_I_TYPE long
+
+/* The type of the result of a floating point comparison. This must
+ match `__libgcc_cmp_return__' in GCC for the target. */
+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
+#define CMPtype __gcc_CMPtype
+
+#define _FP_MUL_MEAT_S(R,X,Y) \
+ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_D(R,X,Y) \
+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
+#define _FP_NANSIGN_S 0
+#define _FP_NANSIGN_D 0
+#define _FP_NANSIGN_Q 0
+
+#define _FP_KEEPNANFRACP 1
+#define _FP_QNANNEGATEDP 0
+
+/* Someone please check this. */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
+ do { \
+ if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
+ && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
+ { \
+ R##_s = Y##_s; \
+ _FP_FRAC_COPY_##wc(R,Y); \
+ } \
+ else \
+ { \
+ R##_s = X##_s; \
+ _FP_FRAC_COPY_##wc(R,X); \
+ } \
+ R##_c = FP_CLS_NAN; \
+ } while (0)
+
+#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
+
+#if defined __big_endian__
+# define __BYTE_ORDER __BIG_ENDIAN
+#else
+# define __BYTE_ORDER __LITTLE_ENDIAN
+#endif
+
+/* Define ALIASNAME as a strong alias for NAME. */
+# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
+# define _strong_alias(name, aliasname) \
+ extern __typeof (name) aliasname __attribute__ ((alias (#name)));
diff --git libgcc/config/nds32/t-nds32 libgcc/config/nds32/t-nds32
new file mode 100644
index 0000000..25c184a
--- /dev/null
+++ libgcc/config/nds32/t-nds32
@@ -0,0 +1,58 @@
+# Rules of libgcc and crtstuff of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+
+# Note:
+# Because GCC has its own make rules for crtbegin.o and crtend.o,
+# we cannot use crtbegin.o and crtend.o rules.
+# So we create crtbegin1.o and crtend1.o instead.
+# Make sure the linker script include these two objects
+# for building .ctors/.dtors sections.
+
+# Use -DCRT_BEGIN to create beginning parts of .init and .fini content
+# Make sure you are building crtbegin1.o with -O0 optimization,
+# otherwise the static function will be optimized out
+crtbegin1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H)
+ $(GCC_FOR_TARGET) $(INCLUDES) \
+ $(CFLAGS) \
+ -DCRT_BEGIN \
+ -finhibit-size-directive -fno-inline-functions \
+ -O0 -c $(srcdir)/config/nds32/initfini.c -o crtbegin1.o
+
+# Use -DCRT_END to create ending parts of .init and .fini content
+# Make sure you are building crtend1.o with -O0 optimization,
+# otherwise the static function will be optimized out
+crtend1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H)
+ $(GCC_FOR_TARGET) $(INCLUDES) \
+ $(CFLAGS) \
+ -DCRT_END \
+ -finhibit-size-directive -fno-inline-functions \
+ -O0 -c $(srcdir)/config/nds32/initfini.c -o crtend1.o
+
+# Use this rule if and only if your crt0.o does not come from library
+# Also, be sure to add 'crtzero.o' in extra_parts in libgcc/config.host
+# and change STARTFILE_SPEC in nds32.h
+#
+#crtzero.o: $(srcdir)/config/nds32/crtzero.S $(GCC_PASSES) $(CONFIG_H)
+# $(GCC_FOR_TARGET) $(INCLUDES) \
+# -c $(srcdir)/config/nds32/crtzero.S -o crtzero.o
+
+
+# ------------------------------------------------------------------------
diff --git libgcc/config/nds32/t-nds32-isr libgcc/config/nds32/t-nds32-isr
new file mode 100644
index 0000000..24f798c
--- /dev/null
+++ libgcc/config/nds32/t-nds32-isr
@@ -0,0 +1,212 @@
+# Rules of c-isr library stuff of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+
+###############################################################################
+# Makfile fragment rules for libnds32_isr.a to support ISR attribute extension
+###############################################################################
+
+# basic flags setting
+ISR_CFLAGS = $(CFLAGS) -c
+
+# the object files we would like to create
+LIBNDS32_ISR_16B_OBJS = \
+ vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \
+ vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \
+ vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \
+ vec_vid12.o vec_vid13.o vec_vid14.o vec_vid15.o \
+ vec_vid16.o vec_vid17.o vec_vid18.o vec_vid19.o \
+ vec_vid20.o vec_vid21.o vec_vid22.o vec_vid23.o \
+ vec_vid24.o vec_vid25.o vec_vid26.o vec_vid27.o \
+ vec_vid28.o vec_vid29.o vec_vid30.o vec_vid31.o \
+ vec_vid32.o vec_vid33.o vec_vid34.o vec_vid35.o \
+ vec_vid36.o vec_vid37.o vec_vid38.o vec_vid39.o \
+ vec_vid40.o vec_vid41.o vec_vid42.o vec_vid43.o \
+ vec_vid44.o vec_vid45.o vec_vid46.o vec_vid47.o \
+ vec_vid48.o vec_vid49.o vec_vid50.o vec_vid51.o \
+ vec_vid52.o vec_vid53.o vec_vid54.o vec_vid55.o \
+ vec_vid56.o vec_vid57.o vec_vid58.o vec_vid59.o \
+ vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \
+ vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \
+ vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \
+ vec_vid72.o \
+ excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \
+ excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \
+ intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \
+ intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \
+ reset.o
+
+LIBNDS32_ISR_4B_OBJS = \
+ vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \
+ vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \
+ vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \
+ vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \
+ vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \
+ vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \
+ vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \
+ vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \
+ vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \
+ vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \
+ vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \
+ vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \
+ vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \
+ vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \
+ vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \
+ vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \
+ vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \
+ vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \
+ vec_vid72_4b.o \
+ excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \
+ excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \
+ intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \
+ intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \
+ reset_4b.o
+
+LIBNDS32_ISR_COMMON_OBJS = \
+ jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \
+ jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \
+ jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \
+ jmptbl_vid12.o jmptbl_vid13.o jmptbl_vid14.o jmptbl_vid15.o \
+ jmptbl_vid16.o jmptbl_vid17.o jmptbl_vid18.o jmptbl_vid19.o \
+ jmptbl_vid20.o jmptbl_vid21.o jmptbl_vid22.o jmptbl_vid23.o \
+ jmptbl_vid24.o jmptbl_vid25.o jmptbl_vid26.o jmptbl_vid27.o \
+ jmptbl_vid28.o jmptbl_vid29.o jmptbl_vid30.o jmptbl_vid31.o \
+ jmptbl_vid32.o jmptbl_vid33.o jmptbl_vid34.o jmptbl_vid35.o \
+ jmptbl_vid36.o jmptbl_vid37.o jmptbl_vid38.o jmptbl_vid39.o \
+ jmptbl_vid40.o jmptbl_vid41.o jmptbl_vid42.o jmptbl_vid43.o \
+ jmptbl_vid44.o jmptbl_vid45.o jmptbl_vid46.o jmptbl_vid47.o \
+ jmptbl_vid48.o jmptbl_vid49.o jmptbl_vid50.o jmptbl_vid51.o \
+ jmptbl_vid52.o jmptbl_vid53.o jmptbl_vid54.o jmptbl_vid55.o \
+ jmptbl_vid56.o jmptbl_vid57.o jmptbl_vid58.o jmptbl_vid59.o \
+ jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \
+ jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \
+ jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \
+ jmptbl_vid72.o \
+ nmih.o \
+ wrh.o
+
+LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS)
+
+
+# Build common objects for ISR library
+nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o
+
+wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o
+
+jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
+
+
+
+# Build 16b version objects for ISR library. (no "_4b" postfix string)
+vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
+
+excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o
+
+excp_isr_ps_ns.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_ns.o
+
+excp_isr_ps_nr.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nr.o
+
+excp_isr_sa_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_nn.o
+
+excp_isr_sa_ns.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_ns.o
+
+excp_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/excp_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_nr.o
+
+intr_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_nn.o
+
+intr_isr_ps_ns.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_ns.o
+
+intr_isr_ps_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_nr.o
+
+intr_isr_sa_nn.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_nn.o
+
+intr_isr_sa_ns.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_ns.o
+
+intr_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_nr.o
+
+reset.o: $(srcdir)/config/nds32/isr-library/reset.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o
+
+# Build 4b version objects for ISR library.
+vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@
+
+excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o
+
+excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o
+
+excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o
+
+excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o
+
+excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o
+
+excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o
+
+intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o
+
+intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o
+
+intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o
+
+intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o
+
+intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o
+
+intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o
+
+reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S
+ $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o
+
+
+# The rule to create libnds32_isr.a file
+libnds32_isr.a: $(LIBNDS32_ISR_COMPLETE_OBJS)
+ $(AR) rc libnds32_isr.a $(LIBNDS32_ISR_COMPLETE_OBJS)
+
+
+# ------------------------------------------------------------------------
diff --git libgcc/config/nds32/t-nds32-mculib libgcc/config/nds32/t-nds32-mculib
new file mode 100644
index 0000000..56da7fe
--- /dev/null
+++ libgcc/config/nds32/t-nds32-mculib
@@ -0,0 +1,77 @@
+# Rules of mculib library makefile of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# Compiler flags to use when compiling 'libgcc2.c'
+HOST_LIBGCC2_CFLAGS = -Os
+
+
+LIB1ASMSRC = nds32/lib1asmsrc-mculib.S
+
+LIB1ASMFUNCS = \
+ _addsub_sf \
+ _sf_to_si \
+ _divsi3 \
+ _divdi3 \
+ _modsi3 \
+ _moddi3 \
+ _mulsi3 \
+ _udivsi3 \
+ _udivdi3 \
+ _udivmoddi4 \
+ _umodsi3 \
+ _umoddi3 \
+ _mcu_muldi3 \
+ _addsub_df \
+ _mul_sf \
+ _mul_df \
+ _div_sf \
+ _div_df \
+ _negate_sf \
+ _negate_df \
+ _sf_to_df \
+ _df_to_sf \
+ _df_to_si \
+ _fixsfdi \
+ _fixdfdi \
+ _fixunssfsi \
+ _fixunsdfsi \
+ _fixunssfdi \
+ _fixunsdfdi \
+ _si_to_sf \
+ _si_to_df \
+ _floatdisf \
+ _floatdidf \
+ _floatunsisf \
+ _floatunsidf \
+ _floatundisf \
+ _floatundidf \
+ _compare_sf \
+ _compare_df \
+ _unord_sf \
+ _unord_df
+
+# List of functions not to build from libgcc2.c.
+LIB2FUNCS_EXCLUDE = _clzsi2 _clzdi2
+
+# List of extra C and assembler files(*.S) to add to static libgcc2.
+LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzsi2.c
+LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzdi2.c
+
+# ------------------------------------------------------------------------
diff --git libgcc/config/nds32/t-nds32-newlib libgcc/config/nds32/t-nds32-newlib
new file mode 100644
index 0000000..b2549a0
--- /dev/null
+++ libgcc/config/nds32/t-nds32-newlib
@@ -0,0 +1,34 @@
+# Rules of newlib library makefile of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# Compiler flags to use when compiling 'libgcc2.c'
+HOST_LIBGCC2_CFLAGS = -O2
+
+
+#LIB1ASMSRC = nds32/lib1asmsrc-newlib.S
+#LIB1ASMFUNCS = _divsi3 _modsi3 _udivsi3 _umodsi3
+
+# List of functions not to build from libgcc2.c.
+#LIB2FUNCS_EXCLUDE = _clzsi2
+
+# List of extra C and assembler files(*.S) to add to static libgcc2.
+#LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-newlib/_clzsi2.c
+
+# ------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 3/6] Andes nds32: libgcc of nds32 porting.
2013-07-08 11:01 [PATCH 3/6] Andes nds32: libgcc of nds32 porting Chung-Ju Wu
@ 2013-07-10 0:08 ` Joseph S. Myers
2013-07-24 16:53 ` Chung-Ju Wu
0 siblings, 1 reply; 5+ messages in thread
From: Joseph S. Myers @ 2013-07-10 0:08 UTC (permalink / raw)
To: Chung-Ju Wu; +Cc: gcc-patches
There are lots of files in this patch with no copyright or license
notices. GNU policy is that every file of more than ten lines needs
copyright and license notices (with the libgcc license exception in this
case), or a notice that the file is in the public domain.
License notices should be GPLv3+exception, not GPLv2 with the old version
of the exception which you have in
libgcc/config/nds32/lib1asmsrc-mculib.S and some other files.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 3/6] Andes nds32: libgcc of nds32 porting.
2013-07-10 0:08 ` Joseph S. Myers
@ 2013-07-24 16:53 ` Chung-Ju Wu
2013-07-31 12:04 ` Chung-Ju Wu
0 siblings, 1 reply; 5+ messages in thread
From: Chung-Ju Wu @ 2013-07-24 16:53 UTC (permalink / raw)
To: Joseph S. Myers; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1282 bytes --]
Hi, Joseph,
Sorry for that we have to zip this patch. It seems that the plaintext
revised patch is too large to be sent to mailing list due to lots of
copyright information.
And I am really sorry for that you probably kept receiving the same mail.
Somehow the this [PATCH 3/6] mail just didn't appear on mailing list archive.
So I tried several times. Really sorry about that.
On 7/10/13 8:04 AM, Joseph S. Myers wrote:
> There are lots of files in this patch with no copyright or license
> notices. GNU policy is that every file of more than ten lines needs
> copyright and license notices (with the libgcc license exception in this
> case), or a notice that the file is in the public domain.
>
> License notices should be GPLv3+exception, not GPLv2 with the old version
> of the exception which you have in
> libgcc/config/nds32/lib1asmsrc-mculib.S and some other files.
>
Thanks for the comment. We have add GPLv3+exception for all the files.
A revised patch is provided and here is a summary:
1. Add GPLv3+exception copyright and license notice for all
c-isr implementation and libgcc stuff.
libgcc/
2013-07-24 Chung-Ju Wu <jasonwucj@gmail.com>
Shiva Chen <shiva0217@gmail.com>
* config/nds32 : New directory and files.
Best regards,
jasonwucj
[-- Attachment #2: 3-nds32-libgcc.v2.patch.tar.gz --]
[-- Type: application/x-gzip, Size: 40843 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 3/6] Andes nds32: libgcc of nds32 porting.
2013-07-24 16:53 ` Chung-Ju Wu
@ 2013-07-31 12:04 ` Chung-Ju Wu
2013-09-08 16:18 ` Chung-Ju Wu
0 siblings, 1 reply; 5+ messages in thread
From: Chung-Ju Wu @ 2013-07-31 12:04 UTC (permalink / raw)
To: gcc-patches; +Cc: Joseph S. Myers
[-- Attachment #1: Type: text/plain, Size: 1221 bytes --]
On 7/25/13 12:41 AM, Chung-Ju Wu wrote:
> On 7/10/13 8:04 AM, Joseph S. Myers wrote:
>> There are lots of files in this patch with no copyright or license
>> notices. GNU policy is that every file of more than ten lines needs
>> copyright and license notices (with the libgcc license exception in this
>> case), or a notice that the file is in the public domain.
>>
>> License notices should be GPLv3+exception, not GPLv2 with the old version
>> of the exception which you have in
>> libgcc/config/nds32/lib1asmsrc-mculib.S and some other files.
>>
>
> Thanks for the comment. We have add GPLv3+exception for all the files.
>
> A revised patch is provided and here is a summary:
>
> 1. Add GPLv3+exception copyright and license notice for all
> c-isr implementation and libgcc stuff.
>
>
> libgcc/
> 2013-07-24 Chung-Ju Wu <jasonwucj@gmail.com>
> Shiva Chen <shiva0217@gmail.com>
>
> * config/nds32 : New directory and files.
>
>
According to Joseph's comment in this discussion thread:
http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01372.html
Using LGPLv2.1+ with exception seems appropriate for sfp-machine.h.
So I update our libgcc patch for nds32 port.
Best regards,
jasonwucj
[-- Attachment #2: 3-nds32-libgcc.v3.patch.tar.gz --]
[-- Type: application/x-gzip, Size: 41118 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 3/6] Andes nds32: libgcc of nds32 porting.
2013-07-31 12:04 ` Chung-Ju Wu
@ 2013-09-08 16:18 ` Chung-Ju Wu
0 siblings, 0 replies; 5+ messages in thread
From: Chung-Ju Wu @ 2013-09-08 16:18 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 537 bytes --]
On 7/31/13 7:07 PM, Chung-Ju Wu wrote:
> On 7/25/13 12:41 AM, Chung-Ju Wu wrote:
>
> According to Joseph's comment in this discussion thread:
> http://gcc.gnu.org/ml/gcc-patches/2013-07/msg01372.html
>
> Using LGPLv2.1+ with exception seems appropriate for sfp-machine.h.
> So I update our libgcc patch for nds32 port.
>
It has been a while since last v2 patch.
I create a new v3 patch with zip file for current trunk.
(The plain text file is too large to be attached.)
Is it OK to apply on the trunk?
Best regards,
jasonwucj
[-- Attachment #2: 3-nds32-libgcc.v3.patch.tar.gz --]
[-- Type: application/x-gzip, Size: 41371 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-09-08 16:17 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2013-07-08 11:01 [PATCH 3/6] Andes nds32: libgcc of nds32 porting Chung-Ju Wu
2013-07-10 0:08 ` Joseph S. Myers
2013-07-24 16:53 ` Chung-Ju Wu
2013-07-31 12:04 ` Chung-Ju Wu
2013-09-08 16:18 ` Chung-Ju Wu
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