From: Jeff Law <law@redhat.com>
To: DJ Delorie <dj@redhat.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: msp430 port
Date: Wed, 24 Jul 2013 21:36:00 -0000 [thread overview]
Message-ID: <51F04676.1020305@redhat.com> (raw)
In-Reply-To: <201307192332.r6JNW2m8013830@greed.delorie.com>
On 07/19/2013 05:32 PM, DJ Delorie wrote:
>> Every pattern that is using (subreg:SI (thing:PSI)) needs to be
>> explained on this list and given an explicit clearance. It really looks
>> like you're just papering over problems elsewhere.
>
> Most of them are just optimizations, but the problem with reload is
> that an SImode register *can't* hold a PSImode value. Registers are
> 20 bits; a PSImode value is 20 bits. SImode values require two
> registers (16 bits each).
Sorry, but I don't see how this is any different than what we've done
before. For example, the mn102 had 24bit address registers (PSImode),
but anytime you wanted to work on in SImode, you head to use a pair of
16 bit data registers.
What you need to do is explain the reload issue in enough detail that
someone can help guide you to what needs to be fixed either in reload or
in the port itself.
> Converting between SImode and PSImode is
> both nontrivial and very common (pointer math).
Yes, I'm painfully aware.
>
> What I really need is an int20_t type in the core of gcc, so I can set
> Pmode to *that*, to avoid the SImode stuff completely. But that's a
> core change, not a target change.
Right. I'm not aware of anything that'll make adding int20_t a
tractable problem in GCC.
>
>> As the comment in addhi_cy mentions, that is truly dangerous and
>> wrong. You can't let that stay in the port without proving GCC
>> won't do a code motion that causes problems. Just because sub, cmp,
>> shift, etc haven't shown up in your tests doesn't mean they can't
>> happen, they just didn't show up in your tests.
>
> I'll try again, but last time I put all the carry logic in all the
> insns, and code size grew quite a bit, and I couldn't figure out why.
> Do I need two patterns for each insn? One that clobbers the carry,
> and one that sets it?
Look at the x86, where we have all this pain as well.
My point is that by not modeling this right, you're running the risk of
having an insn which sets the carry flag get inserted right in between
these two insn sequences.
You might also get better code by keeping those two instruction
sequences as a single insn until after reload.
Jeff
next prev parent reply other threads:[~2013-07-24 21:26 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-17 20:39 Jeff Law
2013-07-19 22:39 ` DJ Delorie
2013-07-19 23:42 ` DJ Delorie
2013-07-24 21:36 ` Jeff Law [this message]
2013-07-26 1:22 ` DJ Delorie
2013-07-30 18:24 ` Jeff Law
2013-07-30 18:56 ` DJ Delorie
2013-07-30 20:44 ` Jeff Law
2013-08-01 10:40 ` Bernd Schmidt
2013-08-02 4:41 ` DJ Delorie
2013-07-23 22:23 ` DJ Delorie
2013-07-30 18:36 ` Jeff Law
2013-07-30 18:50 ` DJ Delorie
2013-07-30 20:23 ` Jeff Law
2013-07-30 20:22 ` Richard Henderson
2013-07-31 3:29 ` DJ Delorie
2013-07-31 13:48 ` nick clifton
2013-07-31 17:03 ` Richard Henderson
2013-07-31 17:14 ` DJ Delorie
2013-07-31 20:23 ` Richard Henderson
2013-08-14 20:55 ` DJ Delorie
2013-08-19 20:49 ` Jeff Law
2013-08-19 20:33 ` Jeff Law
2013-08-19 20:37 ` Jeff Law
2013-07-31 18:21 ` Mike Stump
2013-08-19 20:32 ` Jeff Law
2013-08-19 20:54 ` DJ Delorie
2013-08-19 20:58 ` Jeff Law
2013-08-19 21:23 ` DJ Delorie
2013-08-19 21:28 ` Richard Kenner
2013-08-20 1:14 ` Mike Stump
2013-08-20 8:44 ` Jeff Law
2013-08-23 20:50 ` DJ Delorie
2013-08-24 6:00 ` Jeff Law
2013-08-19 21:46 ` Oleg Endo
2013-08-20 1:04 ` Mike Stump
2013-08-04 18:15 ` Gerald Pfeifer
2013-08-05 17:39 ` DJ Delorie
-- strict thread matches above, loose matches on Subject: below --
2002-05-14 9:02 Dmitry
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