From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7DA383858423 for ; Fri, 14 Jan 2022 17:03:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7DA383858423 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BADB6D; Fri, 14 Jan 2022 09:03:17 -0800 (PST) Received: from [10.57.11.97] (unknown [10.57.11.97]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8596E3F766; Fri, 14 Jan 2022 09:03:16 -0800 (PST) Content-Type: multipart/mixed; boundary="------------pZ9xmI4RsurPQblr0xRr4oPS" Message-ID: <52549bc7-2784-c721-0420-67ad4d40a5ca@arm.com> Date: Fri, 14 Jan 2022 17:03:22 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: [arm] MVE: Relax addressing modes for full loads and stores Content-Language: en-US To: Christophe Lyon , gcc-patches@gcc.gnu.org References: <20220113145645.4077141-1-christophe.lyon@foss.st.com> <20220113145645.4077141-16-christophe.lyon@foss.st.com> From: "Andre Vieira (lists)" In-Reply-To: <20220113145645.4077141-16-christophe.lyon@foss.st.com> X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Jan 2022 17:03:19 -0000 This is a multi-part message in MIME format. --------------pZ9xmI4RsurPQblr0xRr4oPS Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Christophe, This patch relaxes the addressing modes for the mve full load and stores (by full loads and stores I mean non-widening or narrowing loads and stores resp). The code before was requiring a LO_REGNUM for these, where this is only a requirement if the load is widening or the store narrowing. So with this your patch should not be necessary. Regression tested on arm-none-eabi-gcc.  Can you please confirm this fixes the issue you were seeing too? gcc/ChangeLog:         * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.         * config/arm/arm.c (mve_vector_mem_operand): Relax constraint on         base register for non widening loads or narrowing stores. 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