From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3288 invoked by alias); 1 Jun 2016 16:56:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 3276 invoked by uid 89); 1 Jun 2016 16:56:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:7Bit, submission, metal X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 Jun 2016 16:55:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7907428; Wed, 1 Jun 2016 09:56:25 -0700 (PDT) Received: from e108577-lin.localnet (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BFCF13F253; Wed, 1 Jun 2016 09:55:55 -0700 (PDT) From: Thomas Preudhomme To: Kyrill Tkachov Cc: ramana.radhakrishnan@arm.com, richard.earnshaw@arm.com, GCC Patches Subject: Re: [PATCH, testsuite/ARM] Enable atomic tests in gcc.dg for -march=armv8-a bare metal Date: Wed, 01 Jun 2016 16:56:00 -0000 Message-ID: <5274958.VSj8DhqSZz@e108577-lin> User-Agent: KMail/4.13.3 (Linux/3.13.0-85-generic; KDE/4.13.3; x86_64; ; ) In-Reply-To: <574F004A.5070202@foss.arm.com> References: <1538006.87G1ae6iGf@e108577-lin> <574F004A.5070202@foss.arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart1766470.OlWqU9ZBsf" Content-Transfer-Encoding: 7Bit X-IsSubscribed: yes X-SW-Source: 2016-06/txt/msg00064.txt.bz2 This is a multi-part message in MIME format. --nextPart1766470.OlWqU9ZBsf Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" Content-length: 1629 On Wednesday 01 June 2016 16:33:30 Kyrill Tkachov wrote: > I see gcc-patches was not cc'ed on the original submission and I didn't CC > it myself in my reply, so here it is a resend with my reply... > > On 31/05/16 14:11, Thomas Preudhomme wrote: > > Hi, > > > > sync_char_short and sync_int_long used to restrict platform running > > gcc.dg/atomic* tests are only true for ARM when targetting Linux. > > However, > > ARMv8-A brought atomic instructions support so these tests could be run > > on > > bare metal ARMv8-A targets. > > > > This patch define these two effective target to be true for ARM when the > > platform supports lda* and stl* instructions. > > > > ChangeLog entry is as follows: > > > > > > *** gcc/ChangeLog *** > > > > 2016-05-26 Thomas Preud'homme > > > > * doc/sourcebuild.texi (arm_acq_rel): Document new effective > > target. > > > > *** gcc/testsuite/ChangeLog *** > > > > 2016-05-26 Thomas Preud'homme > > > > * lib/target-supports.exp (check_effective_target_arm_acq_rel): > > New > > procedure. > > Have you confirmed that the tests that now become enabled > for bare-metal pass on an arm-none-eabi test run with -march=armv8-a? I did but had a doubt about whether I also tried with -march=armv8-a -mthumb so I tried that just in case and it's all good. > If so, this is ok with the typo fixes below. Please resend the patch > you intend to commit to gcc-patches for archival purposes. Thanks. Committed the patch in attachment. Best regards, Thomas --nextPart1766470.OlWqU9ZBsf Content-Disposition: attachment; filename="enable_gccdg_atomic_tests_on_armv8a.patch" Content-Transfer-Encoding: 7Bit Content-Type: text/x-patch; charset="UTF-8"; name="enable_gccdg_atomic_tests_on_armv8a.patch" Content-length: 2287 diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 41657b5ea47dca7526d0b323e0e27580d50fe51d..0c03920cbec090b07f2559d6471c6eac9bb0c18a 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1597,6 +1597,9 @@ ARM target supports executing ARMv8.1 Adv.SIMD instructions. Some multilibs may be incompatible with the options needed. Implies arm_v8_1a_neon_ok. +@item arm_acq_rel +ARM target supports acquire-release instructions. + @item arm_prefer_ldrd_strd ARM target prefers @code{LDRD} and @code{STRD} instructions over @code{LDM} and @code{STM} instructions. diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 04ca17656f2f26dda710e8a0f9ca77dd963ab39b..f4cb276ed97eaf0f809b2c221f465747320d9a03 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3494,6 +3494,25 @@ proc check_effective_target_arm_neonv2 { } { } } +# Return 1 if this is an ARM target with load acquire and store release +# instructions for 8-, 16- and 32-bit types. + +proc check_effective_target_arm_acq_rel { } { + return [check_no_compiler_messages arm_acq_rel object { + void + load_acquire_store_release (void) + { + asm ("lda r0, [r1]\n\t" + "stl r0, [r1]\n\t" + "ldah r0, [r1]\n\t" + "stlh r0, [r1]\n\t" + "ldab r0, [r1]\n\t" + "stlb r0, [r1]" + : : : "r0", "memory"); + } + }] +} + # Return 1 if this a Loongson-2E or -2F target using an ABI that supports # the Loongson vector modes. @@ -5725,6 +5744,8 @@ proc check_effective_target_sync_int_long { } { || [istarget aarch64*-*-*] || [istarget alpha*-*-*] || [istarget arm*-*-linux-*] + || ([istarget arm*-*-*] + && [check_effective_target_arm_acq_rel]) || [istarget bfin*-*linux*] || [istarget hppa*-*linux*] || [istarget s390*-*-*] @@ -5758,6 +5779,8 @@ proc check_effective_target_sync_char_short { } { || [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget alpha*-*-*] || [istarget arm*-*-linux-*] + || ([istarget arm*-*-*] + && [check_effective_target_arm_acq_rel]) || [istarget hppa*-*linux*] || [istarget s390*-*-*] || [istarget powerpc*-*-*] --nextPart1766470.OlWqU9ZBsf--