Hi,

This patch fixes up the lane access patterns to be symmetric to the order in 
which vectors are stored in registers.

Tested for aarch64-none-elf and aarch64_be-none-elf. OK for trunk?

Thanks,
Tejas Belagod
ARM.

2013-11-21  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Adjust
	for big-endian element order.
	(aarch64_simd_vec_setv2di): Likewise.
	(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>,
	*aarch64_get_lane_zero_extendsi<mode>, aarch64_get_lane): Likewise.
	(vec_extract): Expand using aarch64_get_lane.
	* config/aarch64/aarch64.h (ENDIAN_LANE_N): New.