* [PATCH AArch64_BE 3/4] Big-Endian lane numbering fix
@ 2014-01-16 11:50 Alex Velenko
2014-01-21 13:32 ` Marcus Shawcroft
0 siblings, 1 reply; 3+ messages in thread
From: Alex Velenko @ 2014-01-16 11:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Marcus Shawcroft
[-- Attachment #1: Type: text/plain, Size: 1396 bytes --]
Hi,
This patch by James Greenhalgh fixes "by-lane" patterns broken by
previous patches.
Regression tested on aarch64-none-elf and aarch64_be-none-elf
with no unexpected issues.
OK?
Thanks,
Alex
---
gcc/
2014-01-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_dup_lane<mode>): Correct lane number on big-endian.
(aarch64_dup_lane_<vswap_widthi_name><mode>): Likewise.
(*aarch64_mul3_elt<mode>): Likewise.
(*aarch64_mul3_elt<vswap_width_name><mode>): Likewise.
(*aarch64_mul3_elt_to_64v2df): Likewise.
(*aarch64_mla_elt<mode>): Likewise.
(*aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_mls_elt<mode>): Likewise.
(*aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fma4_elt<mode>): Likewise.
(*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fma4_elt_to_64v2df): Likewise.
(*aarch64_fnma4_elt<mode>): Likewise.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(*aarch64_fnma4_elt_to_64v2df): Likewise.
(aarch64_sq<r>dmulh_lane<mode>): Likewise.
(aarch64_sq<r>dmulh_laneq<mode>): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise.
(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
(aarch64_sqdmull_lane<mode>_internal): Likewise.
(aarch64_sqdmull2_lane<mode>_internal): Likewise.
[-- Attachment #2: mdpattern_fix.patch --]
[-- Type: text/x-patch, Size: 9564 bytes --]
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index e819e6ff54b43f0b24ef176ffd883fd30b774e77..00e85f88feec8c2456c8947fc9925cc583d2ad46 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -67,7 +67,10 @@
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
)))]
"TARGET_SIMD"
- "dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+ return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
+ }
[(set_attr "type" "neon_dup<q>")]
)
@@ -79,7 +82,11 @@
(parallel [(match_operand:SI 2 "immediate_operand" "i")])
)))]
"TARGET_SIMD"
- "dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
+ INTVAL (operands[2])));
+ return "dup\\t%0.<Vtype>, %1.<Vetype>[%2]";
+ }
[(set_attr "type" "neon_dup<q>")]
)
@@ -288,7 +295,10 @@
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VMUL 3 "register_operand" "w")))]
"TARGET_SIMD"
- "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+ return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
+ }
[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
)
@@ -301,7 +311,11 @@
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VMUL_CHANGE_NLANES 3 "register_operand" "w")))]
"TARGET_SIMD"
- "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
+ INTVAL (operands[2])));
+ return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
+ }
[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
)
@@ -324,7 +338,10 @@
(parallel [(match_operand:SI 2 "immediate_operand")]))
(match_operand:DF 3 "register_operand" "w")))]
"TARGET_SIMD"
- "fmul\\t%0.2d, %3.2d, %1.d[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2])));
+ return "fmul\\t%0.2d, %3.2d, %1.d[%2]";
+ }
[(set_attr "type" "neon_fp_mul_d_scalar_q")]
)
@@ -783,7 +800,10 @@
(match_operand:VDQHS 3 "register_operand" "w"))
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
- "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+ return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -798,7 +818,11 @@
(match_operand:VDQHS 3 "register_operand" "w"))
(match_operand:VDQHS 4 "register_operand" "0")))]
"TARGET_SIMD"
- "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
+ INTVAL (operands[2])));
+ return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -823,7 +847,10 @@
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
- "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+ return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -838,7 +865,11 @@
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQHS 3 "register_operand" "w"))))]
"TARGET_SIMD"
- "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
+ INTVAL (operands[2])));
+ return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -1237,7 +1268,10 @@
(match_operand:VDQF 3 "register_operand" "w")
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
- "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+ return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -1251,7 +1285,11 @@
(match_operand:VDQSF 3 "register_operand" "w")
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
- "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
+ INTVAL (operands[2])));
+ return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -1276,7 +1314,10 @@
(match_operand:DF 3 "register_operand" "w")
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
- "fmla\\t%0.2d, %3.2d, %1.2d[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2])));
+ return "fmla\\t%0.2d, %3.2d, %1.2d[%2]";
+ }
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -1303,7 +1344,10 @@
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQF 4 "register_operand" "0")))]
"TARGET_SIMD"
- "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
+ return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -1318,7 +1362,11 @@
(parallel [(match_operand:SI 2 "immediate_operand")])))
(match_operand:VDQSF 4 "register_operand" "0")))]
"TARGET_SIMD"
- "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode,
+ INTVAL (operands[2])));
+ return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ }
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -1345,7 +1393,10 @@
(match_operand:DF 3 "register_operand" "w"))
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_SIMD"
- "fmls\\t%0.2d, %3.2d, %1.2d[%2]"
+ {
+ operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2])));
+ return "fmls\\t%0.2d, %3.2d, %1.2d[%2]";
+ }
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -2543,6 +2594,7 @@
"TARGET_SIMD"
"*
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCOND>mode));
+ operands[3] = GEN_INT (ENDIAN_LANE_N (<VCOND>mode, INTVAL (operands[3])));
return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -2558,6 +2610,7 @@
"TARGET_SIMD"
"*
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
+ operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
return \"sq<r>dmulh\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]\";"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -2573,6 +2626,7 @@
"TARGET_SIMD"
"*
aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode));
+ operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
return \"sq<r>dmulh\\t%<v>0, %<v>1, %2.<v>[%3]\";"
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar<q>")]
)
@@ -2613,7 +2667,11 @@
))
(const_int 1))))]
"TARGET_SIMD"
- "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
+ return
+ "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
+ }
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -2632,7 +2690,11 @@
)
(const_int 1))))]
"TARGET_SIMD"
- "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
+ return
+ "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
+ }
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -2783,7 +2845,11 @@
))))
(const_int 1))))]
"TARGET_SIMD"
- "sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"
+ {
+ operands[4] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[4])));
+ return
+ "sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]";
+ }
[(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
)
@@ -2930,7 +2996,10 @@
))
(const_int 1)))]
"TARGET_SIMD"
- "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
+ {
+ operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
+ return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
+ }
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -2947,7 +3016,10 @@
))
(const_int 1)))]
"TARGET_SIMD"
- "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
+ {
+ operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
+ return "sqdmull\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
+ }
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
@@ -3048,7 +3120,10 @@
))
(const_int 1)))]
"TARGET_SIMD"
- "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]"
+ {
+ operands[3] = GEN_INT (ENDIAN_LANE_N (<VCONQ>mode, INTVAL (operands[3])));
+ return "sqdmull2\\t%<vw2>0<Vmwtype>, %<v>1<Vmtype>, %2.<Vetype>[%3]";
+ }
[(set_attr "type" "neon_sat_mul_<Vetype>_scalar_long")]
)
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH AArch64_BE 3/4] Big-Endian lane numbering fix
2014-01-16 11:50 [PATCH AArch64_BE 3/4] Big-Endian lane numbering fix Alex Velenko
@ 2014-01-21 13:32 ` Marcus Shawcroft
2014-01-21 19:00 ` Alex Velenko
0 siblings, 1 reply; 3+ messages in thread
From: Marcus Shawcroft @ 2014-01-21 13:32 UTC (permalink / raw)
To: Alex Velenko; +Cc: gcc-patches, Marcus Shawcroft
On 16 January 2014 11:50, Alex Velenko <Alex.Velenko@arm.com> wrote:
> Hi,
>
> This patch by James Greenhalgh fixes "by-lane" patterns broken by
> previous patches.
>
>
> Regression tested on aarch64-none-elf and aarch64_be-none-elf
> with no unexpected issues.
>
> OK?
>
OK /Marcus
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH AArch64_BE 3/4] Big-Endian lane numbering fix
2014-01-21 13:32 ` Marcus Shawcroft
@ 2014-01-21 19:00 ` Alex Velenko
0 siblings, 0 replies; 3+ messages in thread
From: Alex Velenko @ 2014-01-21 19:00 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches, Marcus Shawcroft
Hi,
Can someone, please, commit this patch as I do not have privileges to
do so.
Kind regards,
Alex Velenko
On 21/01/14 13:32, Marcus Shawcroft wrote:
> On 16 January 2014 11:50, Alex Velenko <Alex.Velenko@arm.com> wrote:
>> Hi,
>>
>> This patch by James Greenhalgh fixes "by-lane" patterns broken by
>> previous patches.
>>
>>
>> Regression tested on aarch64-none-elf and aarch64_be-none-elf
>> with no unexpected issues.
>>
>> OK?
>>
>
> OK /Marcus
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-01-16 11:50 [PATCH AArch64_BE 3/4] Big-Endian lane numbering fix Alex Velenko
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