From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29645 invoked by alias); 12 Feb 2014 16:10:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 29604 invoked by uid 89); 12 Feb 2014 16:10:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Feb 2014 16:10:43 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 12 Feb 2014 16:10:39 +0000 Received: from [10.1.205.157] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 12 Feb 2014 16:10:40 +0000 Message-ID: <52FB9CFF.90809@arm.com> Date: Wed, 12 Feb 2014 16:10:00 -0000 From: Renlin Li User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130804 Thunderbird/17.0.8 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft , Richard Earnshaw Subject: [PATCH][AARCH64]Adjust address with offset assembler format X-MC-Unique: 114021216103907001 Content-Type: multipart/mixed; boundary="------------020008080708000604050504" X-IsSubscribed: yes X-SW-Source: 2014-02/txt/msg00796.txt.bz2 This is a multi-part message in MIME format. --------------020008080708000604050504 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 465 Hi all, This is a simple patch which adds a space between base register and=20 offset during the address asm translation, making the output assembler=20 code format consistent for aarch64 target. Is it Okay for stage-1? Kind regards, Renlin Li gcc/ChangeLog: 2014-02-12 Renlin Li * config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust=20 the output asm format by adding a space between base register and offset.= --------------020008080708000604050504 Content-Type: text/x-patch; name=offset.diff Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="offset.diff" Content-length: 3575 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d3c5cbc..50ecdd8 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3830,34 +3830,34 @@ aarch64_print_operand_address (FILE *f, rtx x) if (addr.offset =3D=3D const0_rtx) asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]); else - asm_fprintf (f, "[%s,%wd]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, %wd]", reg_names [REGNO (addr.base)], INTVAL (addr.offset)); return; =20 case ADDRESS_REG_REG: if (addr.shift =3D=3D 0) - asm_fprintf (f, "[%s,%s]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, %s]", reg_names [REGNO (addr.base)], reg_names [REGNO (addr.offset)]); else - asm_fprintf (f, "[%s,%s,lsl %u]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, %s, lsl %u]", reg_names [REGNO (addr.base)], reg_names [REGNO (addr.offset)], addr.shift); return; =20 case ADDRESS_REG_UXTW: if (addr.shift =3D=3D 0) - asm_fprintf (f, "[%s,w%d,uxtw]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, w%d, uxtw]", reg_names [REGNO (addr.base)], REGNO (addr.offset) - R0_REGNUM); else - asm_fprintf (f, "[%s,w%d,uxtw %u]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, w%d, uxtw %u]", reg_names [REGNO (addr.base)], REGNO (addr.offset) - R0_REGNUM, addr.shift); return; =20 case ADDRESS_REG_SXTW: if (addr.shift =3D=3D 0) - asm_fprintf (f, "[%s,w%d,sxtw]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, w%d, sxtw]", reg_names [REGNO (addr.base)], REGNO (addr.offset) - R0_REGNUM); else - asm_fprintf (f, "[%s,w%d,sxtw %u]", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, w%d, sxtw %u]", reg_names [REGNO (addr.base)], REGNO (addr.offset) - R0_REGNUM, addr.shift); return; =20 @@ -3865,27 +3865,27 @@ aarch64_print_operand_address (FILE *f, rtx x) switch (GET_CODE (x)) { case PRE_INC: - asm_fprintf (f, "[%s,%d]!", reg_names [REGNO (addr.base)],=20 + asm_fprintf (f, "[%s, %d]!", reg_names [REGNO (addr.base)],=20 GET_MODE_SIZE (aarch64_memory_reference_mode)); return; case POST_INC: - asm_fprintf (f, "[%s],%d", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s], %d", reg_names [REGNO (addr.base)], GET_MODE_SIZE (aarch64_memory_reference_mode)); return; case PRE_DEC: - asm_fprintf (f, "[%s,-%d]!", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, -%d]!", reg_names [REGNO (addr.base)], GET_MODE_SIZE (aarch64_memory_reference_mode)); return; case POST_DEC: - asm_fprintf (f, "[%s],-%d", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s], -%d", reg_names [REGNO (addr.base)], GET_MODE_SIZE (aarch64_memory_reference_mode)); return; case PRE_MODIFY: - asm_fprintf (f, "[%s,%wd]!", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s, %wd]!", reg_names [REGNO (addr.base)], INTVAL (addr.offset)); return; case POST_MODIFY: - asm_fprintf (f, "[%s],%wd", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s], %wd", reg_names [REGNO (addr.base)], INTVAL (addr.offset)); return; default: @@ -3894,7 +3894,7 @@ aarch64_print_operand_address (FILE *f, rtx x) break; =20 case ADDRESS_LO_SUM: - asm_fprintf (f, "[%s,#:lo12:", reg_names [REGNO (addr.base)]); + asm_fprintf (f, "[%s, #:lo12:", reg_names [REGNO (addr.base)]); output_addr_const (f, addr.offset); asm_fprintf (f, "]"); return;= --------------020008080708000604050504--