From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) by sourceware.org (Postfix) with ESMTPS id 2FD4C3858D33 for ; Thu, 23 May 2024 09:01:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2FD4C3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=zhaoxin.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2FD4C3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=203.110.167.99 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716454888; cv=none; b=RYhn8I2kOftc7mJJKNAF7zMB+c7QusR7sH2OxNoese9eJPalxuJCvQgi6UGhuZsK9yPnpEw8zK9Ht0gaFgXTwMzYglgw6L7qdUzzeLpNPPQ6Q1+ea8rsx1iJaLId7PJUl/wyz6DcA6wSRJbG86JyctzHy/YHiNWuMrTyzOWl8/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716454888; c=relaxed/simple; bh=+58qX67d7dA7XYiufmWlY6dsAFb/7+4I4oN4PAHiy38=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=cWPCMDhXyRE1w7BKvY2v4+0ZSTnj+Zow3BQfyfG0G/+ua0cb5dTFsk8Q4sZDNj8MXYZeDTz099q0lThHZOM7kFKIFSTg+AWd33qMl9uevJ5aZisPKRLeLLSpA+IhtPF61i1V2UlHWpXL3NQu9pHucfdMpkY4QW6BtVgE78aoRWs= ARC-Authentication-Results: i=1; server2.sourceware.org X-ASG-Debug-ID: 1716454880-1eb14e157508170001-Gfy7bY Received: from ZXSHMBX3.zhaoxin.com (ZXSHMBX3.zhaoxin.com [10.28.252.165]) by mx2.zhaoxin.com with ESMTP id jJxELoPGmCzXIBqO (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 23 May 2024 17:01:20 +0800 (CST) X-Barracuda-Envelope-From: Mayshao-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXBJMBX02.zhaoxin.com (10.29.252.6) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 23 May 2024 17:01:19 +0800 Received: from [10.30.150.6] (59.172.24.74) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 23 May 2024 17:01:19 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Message-ID: <531f6c23-4d14-486d-9924-46335031d684@zhaoxin.com> X-Barracuda-RBL-Trusted-Forwarder: 10.30.150.6 Date: Thu, 23 May 2024 17:00:54 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] invoke.texi: Clarify -march=lujiazui To: Jakub Jelinek , Uros Bizjak X-ASG-Orig-Subj: Re: [PATCH] invoke.texi: Clarify -march=lujiazui CC: References: Content-Language: en-US From: mayshao-oc In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [59.172.24.74] X-ClientProxiedBy: ZXSHCAS2.zhaoxin.com (10.28.252.162) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1716454880 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 2196 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.125230 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,BODY_8BITS,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Jakub: I think the modified lujiazui description is what actually happens,thanks. BR Mayshao > > > [这封邮件来自外部发件人 谨防风险] > > Hi! > > Yesterday I was searching which exact CPUs are affected by the PR114576 > wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived > at the goldmont, goldmont-plus, tremont and lujiazui CPUs (as -march= > cases which do enable -maes and don't enable -mavx). > But when double-checking that against the invoke.texi documentation, > that was true for the first 3, but lujiazui said it supported AVX. > I was really confused by that, until I found the > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604407.html > explanation. So, seems the CPUs do have AVX and F16C but -march=lujiazui > doesn't enable those and even activelly attempts to filter those out from > the announced CPUID features, in glibc as well as e.g. in libgcc. > > Thus, I think we should document what actually happens, otherwise > users could assume that > gcc -march=lujiazui predefines __AVX__ and __F16C__, which it doesn't. > > Tested on x86_64, ok for trunk? > > 2024-04-11 Jakub Jelinek > > * doc/invoke.texi (lujiazui): Clarify that while the CPUs do support > AVX and F16C, -march=lujiazui actually doesn't enable those. > > --- gcc/doc/invoke.texi.jj 2024-04-11 09:26:01.156865894 +0200 > +++ gcc/doc/invoke.texi 2024-04-11 10:47:53.457582922 +0200 > @@ -34696,8 +34696,10 @@ instruction set support. > > @item lujiazui > ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, > -SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, > -ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support. > +SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, > +ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUs > +do support AVX and F16C, these aren't enabled by @code{-march=lujiazui} > +for performance reasons. > > @item yongfeng > ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, > > Jakub >