* [PATCH] RISC-V:Add support for ZMMUL extension
@ 2022-02-14 2:25 shihua
2022-03-01 13:59 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: shihua @ 2022-02-14 2:25 UTC (permalink / raw)
To: gcc-patches
Cc: jim.wilson.gcc, kito.cheng, lazyparser, jiawei, philipp.tomsich,
LiaoShihua
From: LiaoShihua <shihua@iscas.ac.cn>
ZMMUL extension is Multiply only extension for RISC-V.It implements the multiplication subset of the M extension.
The encodings are identical to those of the corresponding M-extension instructions.
When You both use M extension add ZMMUL extension, it will warning "-mdiv cannot use when the ZMMUL extension is present"
gcc\ChangeLog:
* common/config/riscv/riscv-common.cc:Add support for ZMMUL extension
* config/riscv/riscv-opts.h (MASK_ZMMUL):Likewise
(TARGET_ZMMUL):Likewise
* config/riscv/riscv.cc (riscv_option_override):Likewise
* config/riscv/riscv.md:Likewise
* config/riscv/riscv.opt:Likewise
---
gcc/common/config/riscv/riscv-common.cc | 3 +++
gcc/config/riscv/riscv-opts.h | 3 +++
gcc/config/riscv/riscv.cc | 4 +++-
gcc/config/riscv/riscv.md | 28 ++++++++++++-------------
gcc/config/riscv/riscv.opt | 3 +++
5 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index a904893b9ed..fec6c25eb04 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zmmul", ISA_SPEC_CLASS_NONE, 0, 1},
+
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
@@ -1080,6 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
{"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
+ {"zmmul", &gcc_options::x_riscv_zmmul_subext, MASK_ZMMUL},
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 929e4e3a7c5..47e25628635 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -136,4 +136,7 @@ enum stack_protector_guard {
#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
+#define MASK_ZMMUL (1 << 0)
+#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0)
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6885b4bbad2..bbd5c288da9 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4974,8 +4974,10 @@ riscv_option_override (void)
/* The presence of the M extension implies that division instructions
are present, so include them unless explicitly disabled. */
- if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
+ if (!TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
target_flags |= MASK_DIV;
+ else if(TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
+ warning (0, "%<-mdiv%> cannot use when the %<ZMMUL%> extension is present");
else if (!TARGET_MUL && TARGET_DIV)
error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b3c5bce842a..6dee2fb681a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -756,7 +756,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
- "TARGET_MUL"
+ "TARGET_ZMMUL || TARGET_MUL"
{ return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -765,7 +765,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
(match_operand:DI 2 "register_operand" " r")))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
"mul\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -775,7 +775,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
(match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
- "TARGET_MUL"
+ "TARGET_ZMMUL || TARGET_MUL"
{
if (TARGET_64BIT && <MODE>mode == SImode)
{
@@ -820,7 +820,7 @@
(mult:GPR (match_operand:GPR 1 "register_operand" " r")
(match_operand:GPR 2 "register_operand" " r")))
(label_ref (match_operand 3 "" ""))]
- "TARGET_MUL"
+ "TARGET_ZMMUL || TARGET_MUL"
{
if (TARGET_64BIT && <MODE>mode == SImode)
{
@@ -866,7 +866,7 @@
(sign_extend:DI
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
"mulw\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -877,7 +877,7 @@
(match_operator:SI 3 "subreg_lowpart_operator"
[(mult:DI (match_operand:DI 1 "register_operand" " r")
(match_operand:DI 2 "register_operand" " r"))])))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
"mulw\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -895,7 +895,7 @@
[(set (match_operand:TI 0 "register_operand")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
(any_extend:TI (match_operand:DI 2 "register_operand"))))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
{
rtx low = gen_reg_rtx (DImode);
emit_insn (gen_muldi3 (low, operands[1], operands[2]));
@@ -917,7 +917,7 @@
(any_extend:TI
(match_operand:DI 2 "register_operand" " r")))
(const_int 64))))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
"mulh<u>\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -926,7 +926,7 @@
[(set (match_operand:TI 0 "register_operand")
(mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand"))
(sign_extend:TI (match_operand:DI 2 "register_operand"))))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
{
rtx low = gen_reg_rtx (DImode);
emit_insn (gen_muldi3 (low, operands[1], operands[2]));
@@ -948,7 +948,7 @@
(sign_extend:TI
(match_operand:DI 2 "register_operand" " r")))
(const_int 64))))]
- "TARGET_MUL && TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
"mulhsu\t%0,%2,%1"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -959,7 +959,7 @@
(match_operand:SI 1 "register_operand" " r"))
(any_extend:DI
(match_operand:SI 2 "register_operand" " r"))))]
- "TARGET_MUL && !TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
@@ -978,7 +978,7 @@
(any_extend:DI
(match_operand:SI 2 "register_operand" " r")))
(const_int 32))))]
- "TARGET_MUL && !TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
"mulh<u>\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -990,7 +990,7 @@
(match_operand:SI 1 "register_operand" " r"))
(sign_extend:DI
(match_operand:SI 2 "register_operand" " r"))))]
- "TARGET_MUL && !TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
@@ -1009,7 +1009,7 @@
(sign_extend:DI
(match_operand:SI 2 "register_operand" " r")))
(const_int 32))))]
- "TARGET_MUL && !TARGET_64BIT"
+ "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
"mulhsu\t%0,%2,%1"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 9fffc08220d..46f695b97d3 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,6 +209,9 @@ int riscv_vector_eew_flags
TargetVariable
int riscv_zvl_flags
+TargetVariable
+int riscv_zmmul_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
--
2.31.1.windows.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V:Add support for ZMMUL extension
2022-02-14 2:25 [PATCH] RISC-V:Add support for ZMMUL extension shihua
@ 2022-03-01 13:59 ` Kito Cheng
2022-03-01 14:07 ` 廖仕华
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2022-03-01 13:59 UTC (permalink / raw)
To: 廖仕华; +Cc: GCC Patches, Philipp Tomsich, jiawei
LGTM for GCC 13, I'll commit that once stage 1 is open again.
On Mon, Feb 14, 2022 at 10:26 AM <shihua@iscas.ac.cn> wrote:
>
> From: LiaoShihua <shihua@iscas.ac.cn>
>
> ZMMUL extension is Multiply only extension for RISC-V.It implements the multiplication subset of the M extension.
> The encodings are identical to those of the corresponding M-extension instructions.
> When You both use M extension add ZMMUL extension, it will warning "-mdiv cannot use when the ZMMUL extension is present"
>
> gcc\ChangeLog:
>
> * common/config/riscv/riscv-common.cc:Add support for ZMMUL extension
> * config/riscv/riscv-opts.h (MASK_ZMMUL):Likewise
> (TARGET_ZMMUL):Likewise
> * config/riscv/riscv.cc (riscv_option_override):Likewise
> * config/riscv/riscv.md:Likewise
> * config/riscv/riscv.opt:Likewise
> ---
> gcc/common/config/riscv/riscv-common.cc | 3 +++
> gcc/config/riscv/riscv-opts.h | 3 +++
> gcc/config/riscv/riscv.cc | 4 +++-
> gcc/config/riscv/riscv.md | 28 ++++++++++++-------------
> gcc/config/riscv/riscv.opt | 3 +++
> 5 files changed, 26 insertions(+), 15 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index a904893b9ed..fec6c25eb04 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
>
> + {"zmmul", ISA_SPEC_CLASS_NONE, 0, 1},
> +
> /* Terminate the list. */
> {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> };
> @@ -1080,6 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
> {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
>
> + {"zmmul", &gcc_options::x_riscv_zmmul_subext, MASK_ZMMUL},
>
> {NULL, NULL, 0}
> };
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 929e4e3a7c5..47e25628635 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -136,4 +136,7 @@ enum stack_protector_guard {
> #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
> #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
>
> +#define MASK_ZMMUL (1 << 0)
> +#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0)
> +
> #endif /* ! GCC_RISCV_OPTS_H */
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 6885b4bbad2..bbd5c288da9 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4974,8 +4974,10 @@ riscv_option_override (void)
>
> /* The presence of the M extension implies that division instructions
> are present, so include them unless explicitly disabled. */
> - if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> + if (!TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> target_flags |= MASK_DIV;
> + else if(TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> + warning (0, "%<-mdiv%> cannot use when the %<ZMMUL%> extension is present");
> else if (!TARGET_MUL && TARGET_DIV)
> error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index b3c5bce842a..6dee2fb681a 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -756,7 +756,7 @@
> [(set (match_operand:SI 0 "register_operand" "=r")
> (mult:SI (match_operand:SI 1 "register_operand" " r")
> (match_operand:SI 2 "register_operand" " r")))]
> - "TARGET_MUL"
> + "TARGET_ZMMUL || TARGET_MUL"
> { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -765,7 +765,7 @@
> [(set (match_operand:DI 0 "register_operand" "=r")
> (mult:DI (match_operand:DI 1 "register_operand" " r")
> (match_operand:DI 2 "register_operand" " r")))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mul\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "DI")])
> @@ -775,7 +775,7 @@
> (mult:GPR (match_operand:GPR 1 "register_operand" " r")
> (match_operand:GPR 2 "register_operand" " r")))
> (label_ref (match_operand 3 "" ""))]
> - "TARGET_MUL"
> + "TARGET_ZMMUL || TARGET_MUL"
> {
> if (TARGET_64BIT && <MODE>mode == SImode)
> {
> @@ -820,7 +820,7 @@
> (mult:GPR (match_operand:GPR 1 "register_operand" " r")
> (match_operand:GPR 2 "register_operand" " r")))
> (label_ref (match_operand 3 "" ""))]
> - "TARGET_MUL"
> + "TARGET_ZMMUL || TARGET_MUL"
> {
> if (TARGET_64BIT && <MODE>mode == SImode)
> {
> @@ -866,7 +866,7 @@
> (sign_extend:DI
> (mult:SI (match_operand:SI 1 "register_operand" " r")
> (match_operand:SI 2 "register_operand" " r"))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulw\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -877,7 +877,7 @@
> (match_operator:SI 3 "subreg_lowpart_operator"
> [(mult:DI (match_operand:DI 1 "register_operand" " r")
> (match_operand:DI 2 "register_operand" " r"))])))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulw\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -895,7 +895,7 @@
> [(set (match_operand:TI 0 "register_operand")
> (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
> (any_extend:TI (match_operand:DI 2 "register_operand"))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> {
> rtx low = gen_reg_rtx (DImode);
> emit_insn (gen_muldi3 (low, operands[1], operands[2]));
> @@ -917,7 +917,7 @@
> (any_extend:TI
> (match_operand:DI 2 "register_operand" " r")))
> (const_int 64))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulh<u>\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "DI")])
> @@ -926,7 +926,7 @@
> [(set (match_operand:TI 0 "register_operand")
> (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand"))
> (sign_extend:TI (match_operand:DI 2 "register_operand"))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> {
> rtx low = gen_reg_rtx (DImode);
> emit_insn (gen_muldi3 (low, operands[1], operands[2]));
> @@ -948,7 +948,7 @@
> (sign_extend:TI
> (match_operand:DI 2 "register_operand" " r")))
> (const_int 64))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulhsu\t%0,%2,%1"
> [(set_attr "type" "imul")
> (set_attr "mode" "DI")])
> @@ -959,7 +959,7 @@
> (match_operand:SI 1 "register_operand" " r"))
> (any_extend:DI
> (match_operand:SI 2 "register_operand" " r"))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> {
> rtx temp = gen_reg_rtx (SImode);
> emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
> @@ -978,7 +978,7 @@
> (any_extend:DI
> (match_operand:SI 2 "register_operand" " r")))
> (const_int 32))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> "mulh<u>\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -990,7 +990,7 @@
> (match_operand:SI 1 "register_operand" " r"))
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" " r"))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> {
> rtx temp = gen_reg_rtx (SImode);
> emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
> @@ -1009,7 +1009,7 @@
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" " r")))
> (const_int 32))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> "mulhsu\t%0,%2,%1"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 9fffc08220d..46f695b97d3 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags
> TargetVariable
> int riscv_zvl_flags
>
> +TargetVariable
> +int riscv_zmmul_subext
> +
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
> --
> 2.31.1.windows.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Re: [PATCH] RISC-V:Add support for ZMMUL extension
2022-03-01 13:59 ` Kito Cheng
@ 2022-03-01 14:07 ` 廖仕华
0 siblings, 0 replies; 3+ messages in thread
From: 廖仕华 @ 2022-03-01 14:07 UTC (permalink / raw)
To: Kito Cheng; +Cc: GCC Patches, Philipp Tomsich, jiawei
Thanks you, Kito!
After Zmmul finishes the public review and merge into riscv/riscv-isa-manuel, I will send a new patch if anything changes.
Liao Shihua
> -----原始邮件-----
> 发件人: "Kito Cheng" <kito.cheng@gmail.com>
> 发送时间: 2022-03-01 21:59:47 (星期二)
> 收件人: "廖仕华" <shihua@iscas.ac.cn>
> 抄送: "GCC Patches" <gcc-patches@gcc.gnu.org>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, jiawei <jiawei@iscas.ac.cn>
> 主题: Re: [PATCH] RISC-V:Add support for ZMMUL extension
>
> LGTM for GCC 13, I'll commit that once stage 1 is open again.
>
> On Mon, Feb 14, 2022 at 10:26 AM <shihua@iscas.ac.cn> wrote:
> >
> > From: LiaoShihua <shihua@iscas.ac.cn>
> >
> > ZMMUL extension is Multiply only extension for RISC-V.It implements the multiplication subset of the M extension.
> > The encodings are identical to those of the corresponding M-extension instructions.
> > When You both use M extension add ZMMUL extension, it will warning "-mdiv cannot use when the ZMMUL extension is present"
> >
> > gcc\ChangeLog:
> >
> > * common/config/riscv/riscv-common.cc:Add support for ZMMUL extension
> > * config/riscv/riscv-opts.h (MASK_ZMMUL):Likewise
> > (TARGET_ZMMUL):Likewise
> > * config/riscv/riscv.cc (riscv_option_override):Likewise
> > * config/riscv/riscv.md:Likewise
> > * config/riscv/riscv.opt:Likewise
> > ---
> > gcc/common/config/riscv/riscv-common.cc | 3 +++
> > gcc/config/riscv/riscv-opts.h | 3 +++
> > gcc/config/riscv/riscv.cc | 4 +++-
> > gcc/config/riscv/riscv.md | 28 ++++++++++++-------------
> > gcc/config/riscv/riscv.opt | 3 +++
> > 5 files changed, 26 insertions(+), 15 deletions(-)
> >
> > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> > index a904893b9ed..fec6c25eb04 100644
> > --- a/gcc/common/config/riscv/riscv-common.cc
> > +++ b/gcc/common/config/riscv/riscv-common.cc
> > @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> > {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
> > {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
> >
> > + {"zmmul", ISA_SPEC_CLASS_NONE, 0, 1},
> > +
> > /* Terminate the list. */
> > {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> > };
> > @@ -1080,6 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> > {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
> > {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
> >
> > + {"zmmul", &gcc_options::x_riscv_zmmul_subext, MASK_ZMMUL},
> >
> > {NULL, NULL, 0}
> > };
> > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> > index 929e4e3a7c5..47e25628635 100644
> > --- a/gcc/config/riscv/riscv-opts.h
> > +++ b/gcc/config/riscv/riscv-opts.h
> > @@ -136,4 +136,7 @@ enum stack_protector_guard {
> > #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
> > #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
> >
> > +#define MASK_ZMMUL (1 << 0)
> > +#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0)
> > +
> > #endif /* ! GCC_RISCV_OPTS_H */
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 6885b4bbad2..bbd5c288da9 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -4974,8 +4974,10 @@ riscv_option_override (void)
> >
> > /* The presence of the M extension implies that division instructions
> > are present, so include them unless explicitly disabled. */
> > - if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> > + if (!TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> > target_flags |= MASK_DIV;
> > + else if(TARGET_ZMMUL && TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> > + warning (0, "%<-mdiv%> cannot use when the %<zmmul%> extension is present");
> > else if (!TARGET_MUL && TARGET_DIV)
> > error ("%<-mdiv%> requires %<-march%> to subsume the %<m%> extension");
> >
> > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> > index b3c5bce842a..6dee2fb681a 100644
> > --- a/gcc/config/riscv/riscv.md
> > +++ b/gcc/config/riscv/riscv.md
> > @@ -756,7 +756,7 @@
> > [(set (match_operand:SI 0 "register_operand" "=r")
> > (mult:SI (match_operand:SI 1 "register_operand" " r")
> > (match_operand:SI 2 "register_operand" " r")))]
> > - "TARGET_MUL"
> > + "TARGET_ZMMUL || TARGET_MUL"
> > { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
> > [(set_attr "type" "imul")
> > (set_attr "mode" "SI")])
> > @@ -765,7 +765,7 @@
> > [(set (match_operand:DI 0 "register_operand" "=r")
> > (mult:DI (match_operand:DI 1 "register_operand" " r")
> > (match_operand:DI 2 "register_operand" " r")))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > "mul\t%0,%1,%2"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "DI")])
> > @@ -775,7 +775,7 @@
> > (mult:GPR (match_operand:GPR 1 "register_operand" " r")
> > (match_operand:GPR 2 "register_operand" " r")))
> > (label_ref (match_operand 3 "" ""))]
> > - "TARGET_MUL"
> > + "TARGET_ZMMUL || TARGET_MUL"
> > {
> > if (TARGET_64BIT && <mode>mode == SImode)
> > {
> > @@ -820,7 +820,7 @@
> > (mult:GPR (match_operand:GPR 1 "register_operand" " r")
> > (match_operand:GPR 2 "register_operand" " r")))
> > (label_ref (match_operand 3 "" ""))]
> > - "TARGET_MUL"
> > + "TARGET_ZMMUL || TARGET_MUL"
> > {
> > if (TARGET_64BIT && <mode>mode == SImode)
> > {
> > @@ -866,7 +866,7 @@
> > (sign_extend:DI
> > (mult:SI (match_operand:SI 1 "register_operand" " r")
> > (match_operand:SI 2 "register_operand" " r"))))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > "mulw\t%0,%1,%2"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "SI")])
> > @@ -877,7 +877,7 @@
> > (match_operator:SI 3 "subreg_lowpart_operator"
> > [(mult:DI (match_operand:DI 1 "register_operand" " r")
> > (match_operand:DI 2 "register_operand" " r"))])))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > "mulw\t%0,%1,%2"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "SI")])
> > @@ -895,7 +895,7 @@
> > [(set (match_operand:TI 0 "register_operand")
> > (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
> > (any_extend:TI (match_operand:DI 2 "register_operand"))))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > {
> > rtx low = gen_reg_rtx (DImode);
> > emit_insn (gen_muldi3 (low, operands[1], operands[2]));
> > @@ -917,7 +917,7 @@
> > (any_extend:TI
> > (match_operand:DI 2 "register_operand" " r")))
> > (const_int 64))))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > "mulh<u>\t%0,%1,%2"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "DI")])
> > @@ -926,7 +926,7 @@
> > [(set (match_operand:TI 0 "register_operand")
> > (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand"))
> > (sign_extend:TI (match_operand:DI 2 "register_operand"))))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > {
> > rtx low = gen_reg_rtx (DImode);
> > emit_insn (gen_muldi3 (low, operands[1], operands[2]));
> > @@ -948,7 +948,7 @@
> > (sign_extend:TI
> > (match_operand:DI 2 "register_operand" " r")))
> > (const_int 64))))]
> > - "TARGET_MUL && TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> > "mulhsu\t%0,%2,%1"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "DI")])
> > @@ -959,7 +959,7 @@
> > (match_operand:SI 1 "register_operand" " r"))
> > (any_extend:DI
> > (match_operand:SI 2 "register_operand" " r"))))]
> > - "TARGET_MUL && !TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> > {
> > rtx temp = gen_reg_rtx (SImode);
> > emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
> > @@ -978,7 +978,7 @@
> > (any_extend:DI
> > (match_operand:SI 2 "register_operand" " r")))
> > (const_int 32))))]
> > - "TARGET_MUL && !TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> > "mulh<u>\t%0,%1,%2"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "SI")])
> > @@ -990,7 +990,7 @@
> > (match_operand:SI 1 "register_operand" " r"))
> > (sign_extend:DI
> > (match_operand:SI 2 "register_operand" " r"))))]
> > - "TARGET_MUL && !TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> > {
> > rtx temp = gen_reg_rtx (SImode);
> > emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
> > @@ -1009,7 +1009,7 @@
> > (sign_extend:DI
> > (match_operand:SI 2 "register_operand" " r")))
> > (const_int 32))))]
> > - "TARGET_MUL && !TARGET_64BIT"
> > + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> > "mulhsu\t%0,%2,%1"
> > [(set_attr "type" "imul")
> > (set_attr "mode" "SI")])
> > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> > index 9fffc08220d..46f695b97d3 100644
> > --- a/gcc/config/riscv/riscv.opt
> > +++ b/gcc/config/riscv/riscv.opt
> > @@ -209,6 +209,9 @@ int riscv_vector_eew_flags
> > TargetVariable
> > int riscv_zvl_flags
> >
> > +TargetVariable
> > +int riscv_zmmul_subext
> > +
> > Enum
> > Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> > Supported ISA specs (for use with the -misa-spec= option):
> > --
> > 2.31.1.windows.1
> >
</u></u></mode></mode></m%></zmmul%></shihua@iscas.ac.cn></shihua@iscas.ac.cn></jiawei@iscas.ac.cn></philipp.tomsich@vrull.eu></gcc-patches@gcc.gnu.org></shihua@iscas.ac.cn></kito.cheng@gmail.com>
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2022-02-14 2:25 [PATCH] RISC-V:Add support for ZMMUL extension shihua
2022-03-01 13:59 ` Kito Cheng
2022-03-01 14:07 ` 廖仕华
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