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Fri, 17 Nov 2023 08:47:12 -0800 (PST) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id j3-20020a170902758300b001cc0d1af177sm1575317pll.229.2023.11.17.08.47.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Nov 2023 08:47:12 -0800 (PST) Message-ID: <534975f1-c062-49d5-a9e8-794260a0aba3@gmail.com> Date: Fri, 17 Nov 2023 09:47:07 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: RISC-V: Support XTheadVector extensions Content-Language: en-US To: "juzhe.zhong@rivai.ai" , gcc-patches Cc: "kito.cheng" , "kito.cheng" , "cooper.joshua" , Robin Dapp References: <086123810F5FEA3C+202311171939484236058@rivai.ai> From: Jeff Law In-Reply-To: <086123810F5FEA3C+202311171939484236058@rivai.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/17/23 04:39, juzhe.zhong@rivai.ai wrote: > 90% theadvector extension reusing current RVV 1.0 instructions patterns: > Just change ASM, For example: > > @@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh_scalar" > (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH) > (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] > "TARGET_VECTOR" > - "vmulh.vx\t%0,%3,%z4%p1" > + "%^vmulh.vx\t%0,%3,%z4%p1" > [(set_attr "type" "vimul") > (set_attr "mode" "")]) > > + if (letter == '^') > + { > + if (TARGET_XTHEADVECTOR) > + fputs ("th.", file); > + return; > + } I assume this hunk is meant for riscv_output_operand in riscv.cc. We may also need to add '^' to the punct_valid_p hook. But yes, this is the preferred way to go when all we need to do is prefix the instruction with "th.". > > Btw, stage 1 will close soon.  So I will review this patch on GCC-15 as > long as all other RISC-V maintainers agree. I *think* it's a gcc-15 issue. Philipp T. and I briefly spoke about this at the RVI summit a couple weeks back and he indicated the thead vector work was targeting gcc-15. Jeff