From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3171 invoked by alias); 23 Apr 2014 19:51:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 3161 invoked by uid 89); 23 Apr 2014 19:51:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Apr 2014 19:51:42 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 23 Apr 2014 20:51:38 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 23 Apr 2014 20:51:52 +0100 Message-ID: <535819C9.1020901@arm.com> Date: Wed, 23 Apr 2014 19:53:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [AArch64/ARM 3/3] Add execution tests of ARM REV intrinsics References: <53580E36.2060105@arm.com> In-Reply-To: <53580E36.2060105@arm.com> X-MC-Unique: 114042320513800401 Content-Type: multipart/mixed; boundary="------------040106070205070204050107" X-IsSubscribed: yes X-SW-Source: 2014-04/txt/msg01473.txt.bz2 This is a multi-part message in MIME format. --------------040106070205070204050107 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 2213 Final patch in series, adds new tests of the REV Neon Intrinsics for ARM. T= hese=20 tests subsume the autogenerated tests in gcc/testsuite/gcc.target/arm/neon = (that=20 only check assembler output) by also checking the execution results, reusin= g the=20 test bodies introduced into AArch64 in the first patch. Testsuite driver simd.exp from=20 http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01500.html, will ensure that's= =20 committed first. All passing on arm-none-eabi. gcc/testsuite/ChangeLog: 2014-04-23 Alan Lawrence gcc.target/arm/simd/vrev16p8_1.c: New file. gcc.target/arm/simd/vrev16qp8_1.c: New file. gcc.target/arm/simd/vrev16qs8_1.c: New file. gcc.target/arm/simd/vrev16qu8_1.c: New file. gcc.target/arm/simd/vrev16s8_1.c: New file. gcc.target/arm/simd/vrev16u8_1.c: New file. gcc.target/arm/simd/vrev32p16_1.c: New file. gcc.target/arm/simd/vrev32p8_1.c: New file. gcc.target/arm/simd/vrev32qp16_1.c: New file. gcc.target/arm/simd/vrev32qp8_1.c: New file. gcc.target/arm/simd/vrev32qs16_1.c: New file. gcc.target/arm/simd/vrev32qs8_1.c: New file. gcc.target/arm/simd/vrev32qu16_1.c: New file. gcc.target/arm/simd/vrev32qu8_1.c: New file. gcc.target/arm/simd/vrev32s16_1.c: New file. gcc.target/arm/simd/vrev32s8_1.c: New file. gcc.target/arm/simd/vrev32u16_1.c: New file. gcc.target/arm/simd/vrev32u8_1.c: New file. gcc.target/arm/simd/vrev64f32_1.c: New file. gcc.target/arm/simd/vrev64p16_1.c: New file. gcc.target/arm/simd/vrev64p8_1.c: New file. gcc.target/arm/simd/vrev64qf32_1.c: New file. gcc.target/arm/simd/vrev64qp16_1.c: New file. gcc.target/arm/simd/vrev64qp8_1.c: New file. gcc.target/arm/simd/vrev64qs16_1.c: New file. gcc.target/arm/simd/vrev64qs32_1.c: New file. gcc.target/arm/simd/vrev64qs8_1.c: New file. gcc.target/arm/simd/vrev64qu16_1.c: New file. gcc.target/arm/simd/vrev64qu32_1.c: New file. gcc.target/arm/simd/vrev64qu8_1.c: New file. gcc.target/arm/simd/vrev64s16_1.c: New file. gcc.target/arm/simd/vrev64s32_1.c: New file. gcc.target/arm/simd/vrev64s8_1.c: New file. gcc.target/arm/simd/vrev64u16_1.c: New file. gcc.target/arm/simd/vrev64u32_1.c: New file. gcc.target/arm/simd/vrev64u8_1.c: New file.= --------------040106070205070204050107 Content-Type: text/x-patch; name=vrev_arm_tests.diff Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="vrev_arm_tests.diff" Content-length: 24733 diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev16p8_1.c new file mode 100644 index 0000000..fddb32f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16p8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev16qp8_1.c new file mode 100644 index 0000000..b4634b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qp8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev16qs8_1.c new file mode 100644 index 0000000..691799b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qs8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev16qu8_1.c new file mode 100644 index 0000000..f6ab4ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qu8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev16s8_1.c new file mode 100644 index 0000000..0a03721 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16s8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev16u8_1.c new file mode 100644 index 0000000..7e5f548 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16u8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev32p16_1.c new file mode 100644 index 0000000..f3643fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32p16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev32p8_1.c new file mode 100644 index 0000000..d823e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32p8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev32qp16_1.c new file mode 100644 index 0000000..f8ba8a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qp16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev32qp8_1.c new file mode 100644 index 0000000..0ddf608 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qp8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev32qs16_1.c new file mode 100644 index 0000000..30d0314 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qs16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev32qs8_1.c new file mode 100644 index 0000000..03ddd2b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qs8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev32qu16_1.c new file mode 100644 index 0000000..7176543 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qu16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev32qu8_1.c new file mode 100644 index 0000000..403292c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qu8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev32s16_1.c new file mode 100644 index 0000000..e182ab9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32s16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev32s8_1.c new file mode 100644 index 0000000..a48c415 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32s8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev32u16_1.c new file mode 100644 index 0000000..076f8ab --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32u16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev32u8_1.c new file mode 100644 index 0000000..240d459 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32u8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64f32_1.c new file mode 100644 index 0000000..f5d3bca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64f32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64f32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64p16_1.c new file mode 100644 index 0000000..8c685c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64p16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev64p8_1.c new file mode 100644 index 0000000..67ac1e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64p8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev64qf32_1.c new file mode 100644 index 0000000..74130b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_f32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qf32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev64qp16_1.c new file mode 100644 index 0000000..71f3b4b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qp16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64qp8_1.c new file mode 100644 index 0000000..324a738 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qp8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev64qs16_1.c new file mode 100644 index 0000000..9a373ec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev64qs32_1.c new file mode 100644 index 0000000..0f10c6c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64qs8_1.c new file mode 100644 index 0000000..cf38014 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev64qu16_1.c new file mode 100644 index 0000000..010d6db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsui= te/gcc.target/arm/simd/vrev64qu32_1.c new file mode 100644 index 0000000..908769c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64qu8_1.c new file mode 100644 index 0000000..2fa07d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64s16_1.c new file mode 100644 index 0000000..f14319c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64s32_1.c new file mode 100644 index 0000000..ead5722 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev64s8_1.c new file mode 100644 index 0000000..29d684d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64u16_1.c new file mode 100644 index 0000000..feddacc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuit= e/gcc.target/arm/simd/vrev64u32_1.c new file mode 100644 index 0000000..92a81f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[= 0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite= /gcc.target/arm/simd/vrev64u8_1.c new file mode 100644 index 0000000..f904af5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0= -9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */= --------------040106070205070204050107--