[RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 1024 bytes --]

Hi,

Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for ARM. With
this, atomic test-case gcc.dg/atomic/c11-atomic-exec-5.c now PASS.

This implementation is based on SPARC and i386 implementations.

Regression tested on qemu-arm for arm-none-linux-gnueabi with no new
regression. Is this OK for trunk?

Thanks,
Kugan

gcc/
+2014-04-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
+	(arm_builtins) : Add ARM_BUILTIN_LDFPSCR and ARM_BUILTIN_STFPSCR.
+	(bdesc_2arg) : Add description for builtins __builtins_arm_stfpscr
+	and __builtins_arm_ldfpscr.
+	(arm_init_builtins) : Initialize builtins __builtins_arm_stfpscr and
+	__builtins_arm_ldfpscr.
+	(arm_expand_builtin) : Expand builtins __builtins_arm_stfpscr and
+	__builtins_arm_ldfpscr.
+	(arm_atomic_assign_expand_fenv): New function.
+	* config/arm/vfp.md (stfpscr): New pattern.
+	(ldfpscr) : Likewise.
+	* config/arm/unspecs.md (unspecv): Add VUNSPEC_LDFPSCR and
+	VUNSPEC_STFPSCR.
+



[-- Attachment #2: arm.txt --]
[-- Type: text/plain, Size: 7035 bytes --]

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0240cc7..4f0ed58 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -59,6 +59,7 @@
 #include "params.h"
 #include "opts.h"
 #include "dumpfile.h"
+#include "gimple-expr.h"
 
 /* Forward definitions of types.  */
 typedef struct minipool_node    Mnode;
@@ -93,6 +94,7 @@ static int thumb_far_jump_used_p (void);
 static bool thumb_force_lr_save (void);
 static unsigned arm_size_return_regs (void);
 static bool arm_assemble_integer (rtx, unsigned int, int);
+static void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
 static void arm_print_operand (FILE *, rtx, int);
 static void arm_print_operand_address (FILE *, rtx);
 static bool arm_print_operand_punct_valid_p (unsigned char code);
@@ -584,6 +586,9 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_MANGLE_TYPE
 #define TARGET_MANGLE_TYPE arm_mangle_type
 
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV arm_atomic_assign_expand_fenv
+
 #undef TARGET_BUILD_BUILTIN_VA_LIST
 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
 #undef TARGET_EXPAND_BUILTIN_VA_START
@@ -23212,6 +23217,9 @@ enum arm_builtins
   ARM_BUILTIN_CRC32CH,
   ARM_BUILTIN_CRC32CW,
 
+  ARM_BUILTIN_LDFPSCR,
+  ARM_BUILTIN_STFPSCR,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -24010,6 +24018,15 @@ static const struct builtin_description bdesc_2arg[] =
   IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
   IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
 
+
+#define FP_BUILTIN(L, U) \
+  {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
+   UNKNOWN, 0},
+
+  FP_BUILTIN (stfpscr, LDFPSCR)
+  FP_BUILTIN (ldfpscr, STFPSCR)
+#undef FP_BUILTIN
+
 #define CRC32_BUILTIN(L, U) \
   {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
    UNKNOWN, 0},
@@ -24524,6 +24541,21 @@ arm_init_builtins (void)
 
   if (TARGET_CRC32)
     arm_init_crc32_builtins ();
+
+  if (TARGET_VFP)
+    {
+      tree ftype_stfpscr
+	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
+      tree ftype_ldfpscr
+	= build_function_type_list (unsigned_type_node, NULL);
+
+      arm_builtin_decls[ARM_BUILTIN_LDFPSCR]
+	= add_builtin_function ("__builtin_arm_ldfscr", ftype_ldfpscr,
+				ARM_BUILTIN_LDFPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+      arm_builtin_decls[ARM_BUILTIN_STFPSCR]
+	= add_builtin_function ("__builtin_arm_stfscr", ftype_stfpscr,
+				ARM_BUILTIN_STFPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+    }
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -25251,6 +25283,25 @@ arm_expand_builtin (tree exp,
 
   switch (fcode)
     {
+    case ARM_BUILTIN_LDFPSCR:
+    case ARM_BUILTIN_STFPSCR:
+      if (fcode == ARM_BUILTIN_LDFPSCR)
+	{
+	  icode = CODE_FOR_ldfpscr;
+	  target = gen_reg_rtx (SImode);
+	  pat = GEN_FCN (icode) (target);
+	}
+      else
+	{
+	  target = NULL_RTX;
+	  icode = CODE_FOR_stfpscr;
+	  arg0 = CALL_EXPR_ARG (exp, 0);
+	  op0 = expand_normal (arg0);
+	  pat = GEN_FCN (icode) (op0);
+	}
+      emit_insn (pat);
+      return target;
+
     case ARM_BUILTIN_TEXTRMSB:
     case ARM_BUILTIN_TEXTRMUB:
     case ARM_BUILTIN_TEXTRMSH:
@@ -31116,4 +31167,70 @@ arm_asan_shadow_offset (void)
   return (unsigned HOST_WIDE_INT) 1 << 29;
 }
 
+static void
+arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+  if (!TARGET_VFP)
+    return;
+
+  const unsigned FE_INVALID = 1;
+  const unsigned FE_DIVBYZERO = 2;
+  const unsigned FE_OVERFLOW = 4;
+  const unsigned FE_UNDERFLOW = 8;
+  const unsigned FE_INEXACT = 16;
+  const unsigned HOST_WIDE_INT FE_ALL_EXCEPT = (FE_INVALID | FE_DIVBYZERO
+						| FE_OVERFLOW | FE_UNDERFLOW
+						| FE_INEXACT);
+  const unsigned HOST_WIDE_INT FE_EXCEPT_SHIFT = 8;
+
+  /* Genareate the equivalence of :
+       unsigned int fenv_var;
+       fenv_var = __builtin_arm_ldfpscr ();
+
+       unsigned int masked_fenv;
+       tmp1_var = fenv_var & ~ mask;
+
+       __builtin_arm_fpscr (&tmp1_var);  */
+
+  tree fenv_var = create_tmp_var (unsigned_type_node, NULL);
+  tree ldfpscr = arm_builtin_decls[ARM_BUILTIN_LDFPSCR];
+  tree stfpscr = arm_builtin_decls[ARM_BUILTIN_STFPSCR];
+  tree mask = build_int_cst (unsigned_type_node,
+			     ~((FE_ALL_EXCEPT << FE_EXCEPT_SHIFT)
+			       | FE_ALL_EXCEPT));
+  tree ld_fenv_stmt = build2 (MODIFY_EXPR, unsigned_type_node,
+			      fenv_var, build_call_expr (ldfpscr, 0));
+  tree masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
+  tree hold_fnclex = build_call_expr (stfpscr, 1, masked_fenv);
+  *hold = build2 (COMPOUND_EXPR, void_type_node,
+		  build2 (COMPOUND_EXPR, void_type_node, masked_fenv,
+			  ld_fenv_stmt), hold_fnclex);
+
+  /* Store the value of masked_fenv to clear the exceptions:
+     __builtin_arm_stfpscr (masked_fenv);  */
+
+  *clear = build_call_expr (stfpscr, 1, masked_fenv);
+
+  /* Generate the equivalent of :
+       unsigned int tmp2_var;
+       tmp_var = __builtin_arm_fpscr ();
+
+       __builtin_arm_stfpscr (fenv_var);
+
+       __atomic_feraiseexcept (tmp_var);  */
+
+  tree tmp_var = create_tmp_var (unsigned_type_node, NULL);
+  tree reload_fenv_stmt = build2 (MODIFY_EXPR, unsigned_type_node,
+				  tmp_var, build_call_expr (ldfpscr, 0));
+  tree restore_fnenv = build_call_expr (stfpscr, 1, fenv_var);
+  tree atomic_feraiseexcept
+    = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
+  tree update_call
+    = build_call_expr (atomic_feraiseexcept, 1,
+		       fold_convert (integer_type_node, tmp_var));
+  *update = build2 (COMPOUND_EXPR, void_type_node,
+		    build2 (COMPOUND_EXPR, void_type_node,
+			    reload_fenv_stmt, restore_fnenv), update_call);
+}
+
 #include "gt-arm.h"
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 8caa953..32652c6 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -143,6 +143,8 @@
   VUNSPEC_SLX		; Represent a store-register-release-exclusive.
   VUNSPEC_LDA		; Represent a store-register-acquire.
   VUNSPEC_STL		; Represent a store-register-release.
+  VUNSPEC_LDFPSCR	; load floating point status and control register.
+  VUNSPEC_STFPSCR	; store floating point status and control register.
 ])
 
 ;; Enumerators for NEON unspecs.
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index e1a48ee..a9e4b5b 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1322,6 +1322,22 @@
    (set_attr "conds" "unconditional")]
 )
 
+;; Write Floating-point Status Register.
+(define_insn "stfpscr"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_STFPSCR)]
+  "TARGET_VFP"
+  "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @STFPSCR"
+  [(set_attr "type" "mrs")])
+
+;; Read Floating-point Status Register.
+(define_insn "ldfpscr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec_volatile:SI [(const_int 0)] VUNSPEC_LDFPSCR))]
+  "TARGET_VFP"
+  "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @LDFPSCR"
+  [(set_attr "type" "mrs")])
+
+
 ;; Unimplemented insns:
 ;; fldm*
 ;; fstm*

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Ramana Radhakrishnan]

On 04/26/14 11:26, Kugan wrote:
> Hi,
>
> Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for ARM. With
> this, atomic test-case gcc.dg/atomic/c11-atomic-exec-5.c now PASS.
>
> This implementation is based on SPARC and i386 implementations.
>
> Regression tested on qemu-arm for arm-none-linux-gnueabi with no new
> regression. Is this OK for trunk?

Thanks for this patch. Can you please test this on hardware and make 
sure c11-atomic-exec-5.c works reliably ?

Testing on qemu is not enough for this patch, sorry :(.

Comments inline below.

>
> Thanks,
> Kugan
>
> gcc/
> +2014-04-27  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
> +	(arm_builtins) : Add ARM_BUILTIN_LDFPSCR and ARM_BUILTIN_STFPSCR.
> +	(bdesc_2arg) : Add description for builtins __builtins_arm_stfpscr
> +	and __builtins_arm_ldfpscr.

Rename ld and st as get and set intrinsics please like AArch64.

Add __builtin_arm_setfpscr and __builtin_get_fpscr .

> +	(arm_init_builtins) : Initialize builtins __builtins_arm_stfpscr and
> +	__builtins_arm_ldfpscr.

Likewise.

> +	(arm_expand_builtin) : Expand builtins __builtins_arm_stfpscr and
> +	__builtins_arm_ldfpscr.

Likewise.

> +	(arm_atomic_assign_expand_fenv): New function.

> +	* config/arm/vfp.md (stfpscr): New pattern.
> +	(ldfpscr) : Likewise.
> +	* config/arm/unspecs.md (unspecv): Add VUNSPEC_LDFPSCR and
> +	VUNSPEC_STFPSCR.
> +
>

Replace LD and ST with Get and Set in the builtin names please overall.

> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 0240cc7..4f0ed58 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -59,6 +59,7 @@
>  #include "params.h"
>  #include "opts.h"
>  #include "dumpfile.h"
> +#include "gimple-expr.h"
>
>  /* Forward definitions of types.  */
>  typedef struct minipool_node    Mnode;
> @@ -93,6 +94,7 @@ static int thumb_far_jump_used_p (void);
>  static bool thumb_force_lr_save (void);
>  static unsigned arm_size_return_regs (void);
>  static bool arm_assemble_integer (rtx, unsigned int, int);
> +static void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
>  static void arm_print_operand (FILE *, rtx, int);
>  static void arm_print_operand_address (FILE *, rtx);
>  static bool arm_print_operand_punct_valid_p (unsigned char code);
> @@ -584,6 +586,9 @@ static const struct attribute_spec arm_attribute_table[] =
>  #undef TARGET_MANGLE_TYPE
>  #define TARGET_MANGLE_TYPE arm_mangle_type
>
> +#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
> +#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV arm_atomic_assign_expand_fenv
> +
>  #undef TARGET_BUILD_BUILTIN_VA_LIST
>  #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
>  #undef TARGET_EXPAND_BUILTIN_VA_START
> @@ -23212,6 +23217,9 @@ enum arm_builtins
>    ARM_BUILTIN_CRC32CH,
>    ARM_BUILTIN_CRC32CW,
>
> +  ARM_BUILTIN_LDFPSCR,
> +  ARM_BUILTIN_STFPSCR,
> +

s/LD/GET
s/ST/SET

>  #undef CRYPTO1
>  #undef CRYPTO2
>  #undef CRYPTO3
> @@ -24010,6 +24018,15 @@ static const struct builtin_description bdesc_2arg[] =
>    IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
>    IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
>
> +
> +#define FP_BUILTIN(L, U) \
> +  {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
> +   UNKNOWN, 0},
> +
> +  FP_BUILTIN (stfpscr, LDFPSCR)
> +  FP_BUILTIN (ldfpscr, STFPSCR)
> +#undef FP_BUILTIN
> +
>  #define CRC32_BUILTIN(L, U) \
>    {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
>     UNKNOWN, 0},
> @@ -24524,6 +24541,21 @@ arm_init_builtins (void)
>
>    if (TARGET_CRC32)
>      arm_init_crc32_builtins ();
> +
> +  if (TARGET_VFP)
> +    {
> +      tree ftype_stfpscr
> +	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
> +      tree ftype_ldfpscr
> +	= build_function_type_list (unsigned_type_node, NULL);
> +
> +      arm_builtin_decls[ARM_BUILTIN_LDFPSCR]
> +	= add_builtin_function ("__builtin_arm_ldfscr", ftype_ldfpscr,
> +				ARM_BUILTIN_LDFPSCR, BUILT_IN_MD, NULL, NULL_TREE);
> +      arm_builtin_decls[ARM_BUILTIN_STFPSCR]
> +	= add_builtin_function ("__builtin_arm_stfscr", ftype_stfpscr,
> +				ARM_BUILTIN_STFPSCR, BUILT_IN_MD, NULL, NULL_TREE);
> +    }
>  }
>
>  /* Return the ARM builtin for CODE.  */
> @@ -25251,6 +25283,25 @@ arm_expand_builtin (tree exp,
>
>    switch (fcode)
>      {
> +    case ARM_BUILTIN_LDFPSCR:
> +    case ARM_BUILTIN_STFPSCR:
> +      if (fcode == ARM_BUILTIN_LDFPSCR)
> +	{
> +	  icode = CODE_FOR_ldfpscr;
> +	  target = gen_reg_rtx (SImode);
> +	  pat = GEN_FCN (icode) (target);
> +	}
> +      else
> +	{
> +	  target = NULL_RTX;
> +	  icode = CODE_FOR_stfpscr;
> +	  arg0 = CALL_EXPR_ARG (exp, 0);
> +	  op0 = expand_normal (arg0);
> +	  pat = GEN_FCN (icode) (op0);
> +	}
> +      emit_insn (pat);
> +      return target;
> +
>      case ARM_BUILTIN_TEXTRMSB:
>      case ARM_BUILTIN_TEXTRMUB:
>      case ARM_BUILTIN_TEXTRMSH:
> @@ -31116,4 +31167,70 @@ arm_asan_shadow_offset (void)
>    return (unsigned HOST_WIDE_INT) 1 << 29;
>  }
>
> +static void
> +arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
> +{
> +  if (!TARGET_VFP)
> +    return;
> +
> +  const unsigned FE_INVALID = 1;
> +  const unsigned FE_DIVBYZERO = 2;
> +  const unsigned FE_OVERFLOW = 4;
> +  const unsigned FE_UNDERFLOW = 8;
> +  const unsigned FE_INEXACT = 16;
> +  const unsigned HOST_WIDE_INT FE_ALL_EXCEPT = (FE_INVALID | FE_DIVBYZERO
> +						| FE_OVERFLOW | FE_UNDERFLOW
> +						| FE_INEXACT);
> +  const unsigned HOST_WIDE_INT FE_EXCEPT_SHIFT = 8;
> +
> +  /* Genareate the equivalence of :

s/Genareate/Generate.

> +       unsigned int fenv_var;
> +       fenv_var = __builtin_arm_ldfpscr ();
> +
> +       unsigned int masked_fenv;
> +       tmp1_var = fenv_var & ~ mask;
> +
> +       __builtin_arm_fpscr (&tmp1_var);  */

__builtin_arm_fpscr (&tmp1_var)? I'm not sure I follow . Fix comment here.

> +
> +  tree fenv_var = create_tmp_var (unsigned_type_node, NULL);
> +  tree ldfpscr = arm_builtin_decls[ARM_BUILTIN_LDFPSCR];
> +  tree stfpscr = arm_builtin_decls[ARM_BUILTIN_STFPSCR];
> +  tree mask = build_int_cst (unsigned_type_node,
> +			     ~((FE_ALL_EXCEPT << FE_EXCEPT_SHIFT)
> +			       | FE_ALL_EXCEPT));
> +  tree ld_fenv_stmt = build2 (MODIFY_EXPR, unsigned_type_node,
> +			      fenv_var, build_call_expr (ldfpscr, 0));
> +  tree masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
> +  tree hold_fnclex = build_call_expr (stfpscr, 1, masked_fenv);
> +  *hold = build2 (COMPOUND_EXPR, void_type_node,
> +		  build2 (COMPOUND_EXPR, void_type_node, masked_fenv,
> +			  ld_fenv_stmt), hold_fnclex);
> +
> +  /* Store the value of masked_fenv to clear the exceptions:
> +     __builtin_arm_stfpscr (masked_fenv);  */
> +
> +  *clear = build_call_expr (stfpscr, 1, masked_fenv);
> +
> +  /* Generate the equivalent of :
> +       unsigned int tmp2_var;

What is tmp2_var here ?

> +       tmp_var = __builtin_arm_fpscr ();


__builtin_arm_ldfpscr () ?

replace by __builtin_arm_getfpscr () ?


> +
> +       __builtin_arm_stfpscr (fenv_var);
> +
> +       __atomic_feraiseexcept (tmp_var);  */

Comments please in sync with code ?

> +
> +  tree tmp_var = create_tmp_var (unsigned_type_node, NULL);
> +  tree reload_fenv_stmt = build2 (MODIFY_EXPR, unsigned_type_node,
> +				  tmp_var, build_call_expr (ldfpscr, 0));
> +  tree restore_fnenv = build_call_expr (stfpscr, 1, fenv_var);
> +  tree atomic_feraiseexcept
> +    = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
> +  tree update_call
> +    = build_call_expr (atomic_feraiseexcept, 1,
> +		       fold_convert (integer_type_node, tmp_var));
> +  *update = build2 (COMPOUND_EXPR, void_type_node,
> +		    build2 (COMPOUND_EXPR, void_type_node,
> +			    reload_fenv_stmt, restore_fnenv), update_call);
> +}
> +
>  #include "gt-arm.h"
> diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
> index 8caa953..32652c6 100644
> --- a/gcc/config/arm/unspecs.md
> +++ b/gcc/config/arm/unspecs.md
> @@ -143,6 +143,8 @@
>    VUNSPEC_SLX		; Represent a store-register-release-exclusive.
>    VUNSPEC_LDA		; Represent a store-register-acquire.
>    VUNSPEC_STL		; Represent a store-register-release.
> +  VUNSPEC_LDFPSCR	; load floating point status and control register.
> +  VUNSPEC_STFPSCR	; store floating point status and control register.
>  ])
>
>  ;; Enumerators for NEON unspecs.
> diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
> index e1a48ee..a9e4b5b 100644
> --- a/gcc/config/arm/vfp.md
> +++ b/gcc/config/arm/vfp.md
> @@ -1322,6 +1322,22 @@
>     (set_attr "conds" "unconditional")]
>  )
>
> +;; Write Floating-point Status Register.
> +(define_insn "stfpscr"
> +  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_STFPSCR)]
> +  "TARGET_VFP"
> +  "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @STFPSCR"
> +  [(set_attr "type" "mrs")])
> +
> +;; Read Floating-point Status Register.
> +(define_insn "ldfpscr"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +        (unspec_volatile:SI [(const_int 0)] VUNSPEC_LDFPSCR))]
> +  "TARGET_VFP"
> +  "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @LDFPSCR"
> +  [(set_attr "type" "mrs")])
> +
> +
>  ;; Unimplemented insns:
>  ;; fldm*
>  ;; fstm*
>

Please respin.

Ramana
-- 
Ramana Radhakrishnan
Principal Engineer
ARM Ltd.

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 1709 bytes --]


On 28/04/14 20:29, Ramana Radhakrishnan wrote:
> On 04/26/14 11:26, Kugan wrote:
>> Hi,
>>
>> Attached patch implements TARGET_ATOMIC_ASSIGN_EXPAND_FENV for ARM. With
>> this, atomic test-case gcc.dg/atomic/c11-atomic-exec-5.c now PASS.
>>
>> This implementation is based on SPARC and i386 implementations.
>>
>> Regression tested on qemu-arm for arm-none-linux-gnueabi with no new
>> regression. Is this OK for trunk?
> 
> Thanks for this patch. Can you please test this on hardware and make
> sure c11-atomic-exec-5.c works reliably ?
> 
> Testing on qemu is not enough for this patch, sorry :(.

Thanks for the review. Here is the revised version that addresses the
review comments that is bootstrapped and regression tested on ARM
chromebook for armv7l-unknown-linux-gnueabihf with no new regression.

And c11-atomic-exec-5.c test-cases now PASS.

is this OK?

Thanks,
Kugan

gcc/
+2014-04-29  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
+	(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
+	(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
+	and __builtins_arm_get_fpscr.
+	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
+	__builtins_arm_get_fpscr.
+	(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
+	__builtins_arm_get_fpscr.
+	(arm_atomic_assign_expand_fenv): New function.
+	* config/arm/vfp.md (set_fpscr): New pattern.
+	(get_fpscr) : Likewise.
+	* config/arm/unspecs.md (unspecv): Add UNSPEC_GET_FPSCR and
+	UNSPEC_SET_FPSCR.
+	* doc/extend.texi (AARCH64 Built-in Functions) : Document
+	__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
+

[-- Attachment #2: arm_v2.txt --]
[-- Type: text/plain, Size: 8146 bytes --]

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0240cc7..3de27e6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -59,6 +59,7 @@
 #include "params.h"
 #include "opts.h"
 #include "dumpfile.h"
+#include "gimple-expr.h"
 
 /* Forward definitions of types.  */
 typedef struct minipool_node    Mnode;
@@ -93,6 +94,7 @@ static int thumb_far_jump_used_p (void);
 static bool thumb_force_lr_save (void);
 static unsigned arm_size_return_regs (void);
 static bool arm_assemble_integer (rtx, unsigned int, int);
+static void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
 static void arm_print_operand (FILE *, rtx, int);
 static void arm_print_operand_address (FILE *, rtx);
 static bool arm_print_operand_punct_valid_p (unsigned char code);
@@ -584,6 +586,9 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_MANGLE_TYPE
 #define TARGET_MANGLE_TYPE arm_mangle_type
 
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV arm_atomic_assign_expand_fenv
+
 #undef TARGET_BUILD_BUILTIN_VA_LIST
 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
 #undef TARGET_EXPAND_BUILTIN_VA_START
@@ -23212,6 +23217,9 @@ enum arm_builtins
   ARM_BUILTIN_CRC32CH,
   ARM_BUILTIN_CRC32CW,
 
+  ARM_BUILTIN_GET_FPSCR,
+  ARM_BUILTIN_SET_FPSCR,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -24010,6 +24018,15 @@ static const struct builtin_description bdesc_2arg[] =
   IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
   IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
 
+
+#define FP_BUILTIN(L, U) \
+  {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
+   UNKNOWN, 0},
+
+  FP_BUILTIN (set_fpscr, GET_FPSCR)
+  FP_BUILTIN (get_fpscr, SET_FPSCR)
+#undef FP_BUILTIN
+
 #define CRC32_BUILTIN(L, U) \
   {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
    UNKNOWN, 0},
@@ -24524,6 +24541,21 @@ arm_init_builtins (void)
 
   if (TARGET_CRC32)
     arm_init_crc32_builtins ();
+
+  if (TARGET_VFP)
+    {
+      tree ftype_set_fpscr
+	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
+      tree ftype_get_fpscr
+	= build_function_type_list (unsigned_type_node, NULL);
+
+      arm_builtin_decls[ARM_BUILTIN_GET_FPSCR]
+	= add_builtin_function ("__builtin_arm_ldfscr", ftype_get_fpscr,
+				ARM_BUILTIN_GET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+      arm_builtin_decls[ARM_BUILTIN_SET_FPSCR]
+	= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
+				ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+    }
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -25251,6 +25283,25 @@ arm_expand_builtin (tree exp,
 
   switch (fcode)
     {
+    case ARM_BUILTIN_GET_FPSCR:
+    case ARM_BUILTIN_SET_FPSCR:
+      if (fcode == ARM_BUILTIN_GET_FPSCR)
+	{
+	  icode = CODE_FOR_get_fpscr;
+	  target = gen_reg_rtx (SImode);
+	  pat = GEN_FCN (icode) (target);
+	}
+      else
+	{
+	  target = NULL_RTX;
+	  icode = CODE_FOR_set_fpscr;
+	  arg0 = CALL_EXPR_ARG (exp, 0);
+	  op0 = expand_normal (arg0);
+	  pat = GEN_FCN (icode) (op0);
+	}
+      emit_insn (pat);
+      return target;
+
     case ARM_BUILTIN_TEXTRMSB:
     case ARM_BUILTIN_TEXTRMUB:
     case ARM_BUILTIN_TEXTRMSH:
@@ -31116,4 +31167,70 @@ arm_asan_shadow_offset (void)
   return (unsigned HOST_WIDE_INT) 1 << 29;
 }
 
+static void
+arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+  const unsigned FE_INVALID = 1;
+  const unsigned FE_DIVBYZERO = 2;
+  const unsigned FE_OVERFLOW = 4;
+  const unsigned FE_UNDERFLOW = 8;
+  const unsigned FE_INEXACT = 16;
+  const unsigned HOST_WIDE_INT FE_ALL_EXCEPT = (FE_INVALID | FE_DIVBYZERO
+						| FE_OVERFLOW | FE_UNDERFLOW
+						| FE_INEXACT);
+  const unsigned HOST_WIDE_INT FE_EXCEPT_SHIFT = 8;
+  tree fenv_var, get_fpscr, set_fpscr, mask, ld_fenv, masked_fenv;
+  tree new_fenv_var, reload_fenv, restore_fnenv;
+  tree update_call, atomic_feraiseexcept, hold_fnclex;
+
+  if (!TARGET_VFP)
+    return;
+
+  /* Generate the equivalence of :
+       unsigned int fenv_var;
+       fenv_var = __builtin_arm_get_fpscr ();
+
+       unsigned int masked_fenv;
+       masked_fenv = fenv_var & mask;
+
+       __builtin_arm_set_fpscr (masked_fenv);  */
+
+  fenv_var = create_tmp_var (unsigned_type_node, NULL);
+  get_fpscr = arm_builtin_decls[ARM_BUILTIN_GET_FPSCR];
+  set_fpscr = arm_builtin_decls[ARM_BUILTIN_SET_FPSCR];
+  mask = build_int_cst (unsigned_type_node,
+			~((FE_ALL_EXCEPT << FE_EXCEPT_SHIFT) | FE_ALL_EXCEPT));
+  ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
+		    fenv_var, build_call_expr (get_fpscr, 0));
+  masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
+  hold_fnclex = build_call_expr (set_fpscr, 1, masked_fenv);
+  *hold = build2 (COMPOUND_EXPR, void_type_node,
+		  build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv),
+		  hold_fnclex);
+
+  /* Store the value of masked_fenv to clear the exceptions:
+     __builtin_arm_set_fpscr (masked_fenv);  */
+
+  *clear = build_call_expr (set_fpscr, 1, masked_fenv);
+
+  /* Generate the equivalent of :
+       unsigned int tmp2_var;
+       new_fenv_var = __builtin_arm_get_fpscr ();
+
+       __builtin_arm_set_fpscr (fenv_var);
+
+       __atomic_feraiseexcept (new_fenv_var);  */
+
+  new_fenv_var = create_tmp_var (unsigned_type_node, NULL);
+  reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var,
+			build_call_expr (get_fpscr, 0));
+  restore_fnenv = build_call_expr (set_fpscr, 1, fenv_var);
+  atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
+  update_call = build_call_expr (atomic_feraiseexcept, 1,
+				 fold_convert (integer_type_node, new_fenv_var));
+  *update = build2 (COMPOUND_EXPR, void_type_node,
+		    build2 (COMPOUND_EXPR, void_type_node,
+			    reload_fenv, restore_fnenv), update_call);
+}
+
 #include "gt-arm.h"
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 8caa953..147cb80 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -143,6 +143,8 @@
   VUNSPEC_SLX		; Represent a store-register-release-exclusive.
   VUNSPEC_LDA		; Represent a store-register-acquire.
   VUNSPEC_STL		; Represent a store-register-release.
+  VUNSPEC_GET_FPSCR	; Represent fetch of FPSCR content.
+  VUNSPEC_SET_FPSCR	; Represent assign of FPSCR content.
 ])
 
 ;; Enumerators for NEON unspecs.
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index e1a48ee..f4d6c65 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1322,6 +1322,22 @@
    (set_attr "conds" "unconditional")]
 )
 
+;; Write Floating-point Status Register.
+(define_insn "set_fpscr"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
+  "TARGET_VFP"
+  "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
+  [(set_attr "type" "mrs")])
+
+;; Read Floating-point Status Register.
+(define_insn "get_fpscr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
+  "TARGET_VFP"
+  "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
+  [(set_attr "type" "mrs")])
+
+
 ;; Unimplemented insns:
 ;; fldm*
 ;; fstm*
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 347a94a..9104331 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9114,6 +9114,7 @@ instructions, but allow the compiler to schedule those calls.
 * ARM iWMMXt Built-in Functions::
 * ARM NEON Intrinsics::
 * ARM ACLE Intrinsics::
+* ARM Floating Point Status and Control Intrinsics::
 * AVR Built-in Functions::
 * Blackfin Built-in Functions::
 * FR-V Built-in Functions::
@@ -9918,6 +9919,17 @@ the @option{-march=armv8-a+crc} switch is used:
 
 @include arm-acle-intrinsics.texi
 
+@node ARM Floating Point Status and Control Intrinsics
+@subsection ARM Floating Point Status and Control Intrinsics
+
+These built-in functions are available for the ARM family of
+processors with floating-point unit.
+
+@smallexample
+unsigned int __builtin_arm_get_fpscr ()
+void __builtin_arm_set_fpscr (unsigned int)
+@end smallexample
+
 @node AVR Built-in Functions
 @subsection AVR Built-in Functions
 

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Joseph S. Myers]

It doesn't seem a good idea to me for a host-side GCC file to use the FE_* 
names for the target's FE_* values; you'd run into problems if that file 
ever ends up including the host's <fenv.h>, directly or indirectly, on any 
host.  The same comment applies to the AArch64 patch as well.

Instead I suggest names such as ARM_FE_* that won't conflict with the 
host's system headers.

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 1367 bytes --]

On 02/05/14 10:15, Joseph S. Myers wrote:
> It doesn't seem a good idea to me for a host-side GCC file to use the FE_* 
> names for the target's FE_* values; you'd run into problems if that file 
> ever ends up including the host's <fenv.h>, directly or indirectly, on any 
> host.  The same comment applies to the AArch64 patch as well.
> 
> Instead I suggest names such as ARM_FE_* that won't conflict with the 
> host's system headers.
> 
Thanks for spotting it. Here is the updated patch that changes it to
ARM_FE_*.

Thanks,
Kugan


gcc/

+2014-05-02  Kugan Vivekanandarajah  <kuganv@linaro.org>
+
+	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
+	(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
+	(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
+	and __builtins_arm_get_fpscr.
+	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
+	__builtins_arm_get_fpscr.
+	(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
+	__builtins_arm_ldfpscr.
+	(arm_atomic_assign_expand_fenv): New function.
+	* config/arm/vfp.md (set_fpscr): New pattern.
+	(get_fpscr) : Likewise.
+	* config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
+	VUNSPEC_SET_FPSCR.
+	* doc/extend.texi (AARCH64 Built-in Functions) : Document
+	__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
+

[-- Attachment #2: arm_v3.txt --]
[-- Type: text/plain, Size: 8270 bytes --]

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0240cc7..b2d50f6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -59,6 +59,7 @@
 #include "params.h"
 #include "opts.h"
 #include "dumpfile.h"
+#include "gimple-expr.h"
 
 /* Forward definitions of types.  */
 typedef struct minipool_node    Mnode;
@@ -93,6 +94,7 @@ static int thumb_far_jump_used_p (void);
 static bool thumb_force_lr_save (void);
 static unsigned arm_size_return_regs (void);
 static bool arm_assemble_integer (rtx, unsigned int, int);
+static void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
 static void arm_print_operand (FILE *, rtx, int);
 static void arm_print_operand_address (FILE *, rtx);
 static bool arm_print_operand_punct_valid_p (unsigned char code);
@@ -584,6 +586,9 @@ static const struct attribute_spec arm_attribute_table[] =
 #undef TARGET_MANGLE_TYPE
 #define TARGET_MANGLE_TYPE arm_mangle_type
 
+#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
+#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV arm_atomic_assign_expand_fenv
+
 #undef TARGET_BUILD_BUILTIN_VA_LIST
 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
 #undef TARGET_EXPAND_BUILTIN_VA_START
@@ -23212,6 +23217,9 @@ enum arm_builtins
   ARM_BUILTIN_CRC32CH,
   ARM_BUILTIN_CRC32CW,
 
+  ARM_BUILTIN_GET_FPSCR,
+  ARM_BUILTIN_SET_FPSCR,
+
 #undef CRYPTO1
 #undef CRYPTO2
 #undef CRYPTO3
@@ -24010,6 +24018,15 @@ static const struct builtin_description bdesc_2arg[] =
   IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
   IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
 
+
+#define FP_BUILTIN(L, U) \
+  {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
+   UNKNOWN, 0},
+
+  FP_BUILTIN (set_fpscr, GET_FPSCR)
+  FP_BUILTIN (get_fpscr, SET_FPSCR)
+#undef FP_BUILTIN
+
 #define CRC32_BUILTIN(L, U) \
   {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
    UNKNOWN, 0},
@@ -24524,6 +24541,21 @@ arm_init_builtins (void)
 
   if (TARGET_CRC32)
     arm_init_crc32_builtins ();
+
+  if (TARGET_VFP)
+    {
+      tree ftype_set_fpscr
+	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
+      tree ftype_get_fpscr
+	= build_function_type_list (unsigned_type_node, NULL);
+
+      arm_builtin_decls[ARM_BUILTIN_GET_FPSCR]
+	= add_builtin_function ("__builtin_arm_ldfscr", ftype_get_fpscr,
+				ARM_BUILTIN_GET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+      arm_builtin_decls[ARM_BUILTIN_SET_FPSCR]
+	= add_builtin_function ("__builtin_arm_stfscr", ftype_set_fpscr,
+				ARM_BUILTIN_SET_FPSCR, BUILT_IN_MD, NULL, NULL_TREE);
+    }
 }
 
 /* Return the ARM builtin for CODE.  */
@@ -25251,6 +25283,25 @@ arm_expand_builtin (tree exp,
 
   switch (fcode)
     {
+    case ARM_BUILTIN_GET_FPSCR:
+    case ARM_BUILTIN_SET_FPSCR:
+      if (fcode == ARM_BUILTIN_GET_FPSCR)
+	{
+	  icode = CODE_FOR_get_fpscr;
+	  target = gen_reg_rtx (SImode);
+	  pat = GEN_FCN (icode) (target);
+	}
+      else
+	{
+	  target = NULL_RTX;
+	  icode = CODE_FOR_set_fpscr;
+	  arg0 = CALL_EXPR_ARG (exp, 0);
+	  op0 = expand_normal (arg0);
+	  pat = GEN_FCN (icode) (op0);
+	}
+      emit_insn (pat);
+      return target;
+
     case ARM_BUILTIN_TEXTRMSB:
     case ARM_BUILTIN_TEXTRMUB:
     case ARM_BUILTIN_TEXTRMSH:
@@ -31116,4 +31167,73 @@ arm_asan_shadow_offset (void)
   return (unsigned HOST_WIDE_INT) 1 << 29;
 }
 
+static void
+arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
+{
+  const unsigned ARM_FE_INVALID = 1;
+  const unsigned ARM_FE_DIVBYZERO = 2;
+  const unsigned ARM_FE_OVERFLOW = 4;
+  const unsigned ARM_FE_UNDERFLOW = 8;
+  const unsigned ARM_FE_INEXACT = 16;
+  const unsigned HOST_WIDE_INT ARM_FE_ALL_EXCEPT = (ARM_FE_INVALID
+						    | ARM_FE_DIVBYZERO
+						    | ARM_FE_OVERFLOW
+						    | ARM_FE_UNDERFLOW
+						    | ARM_FE_INEXACT);
+  const unsigned HOST_WIDE_INT ARM_FE_EXCEPT_SHIFT = 8;
+  tree fenv_var, get_fpscr, set_fpscr, mask, ld_fenv, masked_fenv;
+  tree new_fenv_var, reload_fenv, restore_fnenv;
+  tree update_call, atomic_feraiseexcept, hold_fnclex;
+
+  if (!TARGET_VFP)
+    return;
+
+  /* Generate the equivalence of :
+       unsigned int fenv_var;
+       fenv_var = __builtin_arm_get_fpscr ();
+
+       unsigned int masked_fenv;
+       masked_fenv = fenv_var & mask;
+
+       __builtin_arm_set_fpscr (masked_fenv);  */
+
+  fenv_var = create_tmp_var (unsigned_type_node, NULL);
+  get_fpscr = arm_builtin_decls[ARM_BUILTIN_GET_FPSCR];
+  set_fpscr = arm_builtin_decls[ARM_BUILTIN_SET_FPSCR];
+  mask = build_int_cst (unsigned_type_node,
+			~((ARM_FE_ALL_EXCEPT << ARM_FE_EXCEPT_SHIFT)
+			  | ARM_FE_ALL_EXCEPT));
+  ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
+		    fenv_var, build_call_expr (get_fpscr, 0));
+  masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
+  hold_fnclex = build_call_expr (set_fpscr, 1, masked_fenv);
+  *hold = build2 (COMPOUND_EXPR, void_type_node,
+		  build2 (COMPOUND_EXPR, void_type_node, masked_fenv, ld_fenv),
+		  hold_fnclex);
+
+  /* Store the value of masked_fenv to clear the exceptions:
+     __builtin_arm_set_fpscr (masked_fenv);  */
+
+  *clear = build_call_expr (set_fpscr, 1, masked_fenv);
+
+  /* Generate the equivalent of :
+       unsigned int new_fenv_var;
+       new_fenv_var = __builtin_arm_get_fpscr ();
+
+       __builtin_arm_set_fpscr (fenv_var);
+
+       __atomic_feraiseexcept (new_fenv_var);  */
+
+  new_fenv_var = create_tmp_var (unsigned_type_node, NULL);
+  reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var,
+			build_call_expr (get_fpscr, 0));
+  restore_fnenv = build_call_expr (set_fpscr, 1, fenv_var);
+  atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
+  update_call = build_call_expr (atomic_feraiseexcept, 1,
+				 fold_convert (integer_type_node, new_fenv_var));
+  *update = build2 (COMPOUND_EXPR, void_type_node,
+		    build2 (COMPOUND_EXPR, void_type_node,
+			    reload_fenv, restore_fnenv), update_call);
+}
+
 #include "gt-arm.h"
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 8caa953..147cb80 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -143,6 +143,8 @@
   VUNSPEC_SLX		; Represent a store-register-release-exclusive.
   VUNSPEC_LDA		; Represent a store-register-acquire.
   VUNSPEC_STL		; Represent a store-register-release.
+  VUNSPEC_GET_FPSCR	; Represent fetch of FPSCR content.
+  VUNSPEC_SET_FPSCR	; Represent assign of FPSCR content.
 ])
 
 ;; Enumerators for NEON unspecs.
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index e1a48ee..3c7744f 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1322,6 +1322,22 @@
    (set_attr "conds" "unconditional")]
 )
 
+;; Write Floating-point Status and Control Register.
+(define_insn "set_fpscr"
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
+  "TARGET_VFP"
+  "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
+  [(set_attr "type" "mrs")])
+
+;; Read Floating-point Status and Control Register.
+(define_insn "get_fpscr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
+  "TARGET_VFP"
+  "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
+  [(set_attr "type" "mrs")])
+
+
 ;; Unimplemented insns:
 ;; fldm*
 ;; fstm*
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 347a94a..9104331 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9114,6 +9114,7 @@ instructions, but allow the compiler to schedule those calls.
 * ARM iWMMXt Built-in Functions::
 * ARM NEON Intrinsics::
 * ARM ACLE Intrinsics::
+* ARM Floating Point Status and Control Intrinsics::
 * AVR Built-in Functions::
 * Blackfin Built-in Functions::
 * FR-V Built-in Functions::
@@ -9918,6 +9919,17 @@ the @option{-march=armv8-a+crc} switch is used:
 
 @include arm-acle-intrinsics.texi
 
+@node ARM Floating Point Status and Control Intrinsics
+@subsection ARM Floating Point Status and Control Intrinsics
+
+These built-in functions are available for the ARM family of
+processors with floating-point unit.
+
+@smallexample
+unsigned int __builtin_arm_get_fpscr ()
+void __builtin_arm_set_fpscr (unsigned int)
+@end smallexample
+
 @node AVR Built-in Functions
 @subsection AVR Built-in Functions
 

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

Ping ?

Thanks,
Kugan

On 02/05/14 19:04, Kugan wrote:
> On 02/05/14 10:15, Joseph S. Myers wrote:
>> It doesn't seem a good idea to me for a host-side GCC file to use the FE_* 
>> names for the target's FE_* values; you'd run into problems if that file 
>> ever ends up including the host's <fenv.h>, directly or indirectly, on any 
>> host.  The same comment applies to the AArch64 patch as well.
>>
>> Instead I suggest names such as ARM_FE_* that won't conflict with the 
>> host's system headers.
>>
> Thanks for spotting it. Here is the updated patch that changes it to
> ARM_FE_*.
> 
> Thanks,
> Kugan
> 
> 
> gcc/
> 
> +2014-05-02  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
> +	(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
> +	(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
> +	and __builtins_arm_get_fpscr.
> +	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
> +	__builtins_arm_get_fpscr.
> +	(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
> +	__builtins_arm_ldfpscr.
> +	(arm_atomic_assign_expand_fenv): New function.
> +	* config/arm/vfp.md (set_fpscr): New pattern.
> +	(get_fpscr) : Likewise.
> +	* config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
> +	VUNSPEC_SET_FPSCR.
> +	* doc/extend.texi (AARCH64 Built-in Functions) : Document
> +	__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
> +
> 

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

Ping^2 ?

Thanks,
Kugan

On 12/05/14 09:47, Kugan wrote:
> Ping ?
> 
> Thanks,
> Kugan
> 
> On 02/05/14 19:04, Kugan wrote:
>> On 02/05/14 10:15, Joseph S. Myers wrote:
>>> It doesn't seem a good idea to me for a host-side GCC file to use the FE_* 
>>> names for the target's FE_* values; you'd run into problems if that file 
>>> ever ends up including the host's <fenv.h>, directly or indirectly, on any 
>>> host.  The same comment applies to the AArch64 patch as well.
>>>
>>> Instead I suggest names such as ARM_FE_* that won't conflict with the 
>>> host's system headers.
>>>
>> Thanks for spotting it. Here is the updated patch that changes it to
>> ARM_FE_*.
>>
>> Thanks,
>> Kugan
>>
>>
>> gcc/
>>
>> +2014-05-02  Kugan Vivekanandarajah  <kuganv@linaro.org>
>> +
>> +	* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
>> +	(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
>> +	(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
>> +	and __builtins_arm_get_fpscr.
>> +	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
>> +	__builtins_arm_get_fpscr.
>> +	(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
>> +	__builtins_arm_ldfpscr.
>> +	(arm_atomic_assign_expand_fenv): New function.
>> +	* config/arm/vfp.md (set_fpscr): New pattern.
>> +	(get_fpscr) : Likewise.
>> +	* config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
>> +	VUNSPEC_SET_FPSCR.
>> +	* doc/extend.texi (AARCH64 Built-in Functions) : Document
>> +	__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
>> +
>>
> 

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Ramana Radhakrishnan]

>+  if (!TARGET_VFP)
>+    return;
>+
>+  /* Generate the equivalence of :

s/equivalence/equivalent.

Ok with that change and if no regressions.

Ramana

On Mon, May 26, 2014 at 9:01 AM, Kugan
<kugan.vivekanandarajah@linaro.org> wrote:
> Ping^2 ?
>
> Thanks,
> Kugan
>
> On 12/05/14 09:47, Kugan wrote:
>> Ping ?
>>
>> Thanks,
>> Kugan
>>
>> On 02/05/14 19:04, Kugan wrote:
>>> On 02/05/14 10:15, Joseph S. Myers wrote:
>>>> It doesn't seem a good idea to me for a host-side GCC file to use the FE_*
>>>> names for the target's FE_* values; you'd run into problems if that file
>>>> ever ends up including the host's <fenv.h>, directly or indirectly, on any
>>>> host.  The same comment applies to the AArch64 patch as well.
>>>>
>>>> Instead I suggest names such as ARM_FE_* that won't conflict with the
>>>> host's system headers.
>>>>
>>> Thanks for spotting it. Here is the updated patch that changes it to
>>> ARM_FE_*.
>>>
>>> Thanks,
>>> Kugan
>>>
>>>
>>> gcc/
>>>
>>> +2014-05-02  Kugan Vivekanandarajah  <kuganv@linaro.org>
>>> +
>>> +    * config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
>>> +    (arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
>>> +    (bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
>>> +    and __builtins_arm_get_fpscr.
>>> +    (arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
>>> +    __builtins_arm_get_fpscr.
>>> +    (arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
>>> +    __builtins_arm_ldfpscr.
>>> +    (arm_atomic_assign_expand_fenv): New function.
>>> +    * config/arm/vfp.md (set_fpscr): New pattern.
>>> +    (get_fpscr) : Likewise.
>>> +    * config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
>>> +    VUNSPEC_SET_FPSCR.
>>> +    * doc/extend.texi (AARCH64 Built-in Functions) : Document
>>> +    __builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
>>> +
>>>
>>

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 979 bytes --]

On 30/05/14 18:35, Ramana Radhakrishnan wrote:
>> +  if (!TARGET_VFP)
>> +    return;
>> +
>> +  /* Generate the equivalence of :
> 
> s/equivalence/equivalent.
> 
> Ok with that change and if no regressions.

Hi Ramana,

Sorry, I missed the thumb1 part. There are no mrc/mcr  versions of these
instructions in thumb1. So these should be conditional on not being
ARM_THUMB1.

Is this OK. Regression tested with no new refression on qemu for
arm-none-linux-gnueabi -march=armv7-a and on arm-none-linux-gnueabi
--with-mode=thumb and -march=armv5t.

Is this OK?

Thanks,
Kugan

gcc/

2014-06-10  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* config/arm/arm.c (arm_atomic_assign_expand_fenv): call
	default_atomic_assign_expand_fenv for TARGET_THUMB1.
	(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
	__builtins_arm_get_fpscr only when !TARGET_THUMB1.
	* config/arm/vfp.md (set_fpscr): Make pattern conditional on
	!TARGERT_THUMB1.
	(get_fpscr) : Likewise.

[-- Attachment #2: p.txt --]
[-- Type: text/plain, Size: 1583 bytes --]

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f8575b9..c9f02df 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -24760,7 +24760,7 @@ arm_init_builtins (void)
   if (TARGET_CRC32)
     arm_init_crc32_builtins ();
 
-  if (TARGET_VFP)
+  if (TARGET_VFP && !TARGET_THUMB1)
     {
       tree ftype_set_fpscr
 	= build_function_type_list (void_type_node, unsigned_type_node, NULL);
@@ -31452,8 +31452,8 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
   tree new_fenv_var, reload_fenv, restore_fnenv;
   tree update_call, atomic_feraiseexcept, hold_fnclex;
 
-  if (!TARGET_VFP)
-    return;
+  if (!TARGET_VFP || TARGET_THUMB1)
+    return default_atomic_assign_expand_fenv (hold, clear, update);
 
   /* Generate the equivalent of :
        unsigned int fenv_var;
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index a8b27bc..44d2f38 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1325,7 +1325,7 @@
 ;; Write Floating-point Status and Control Register.
 (define_insn "set_fpscr"
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
-  "TARGET_VFP"
+  "TARGET_VFP && !TARGET_THUMB1"
   "mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
   [(set_attr "type" "mrs")])
 
@@ -1333,7 +1333,7 @@
 (define_insn "get_fpscr"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
-  "TARGET_VFP"
+  "TARGET_VFP && !TARGET_THUMB1"
   "mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
   [(set_attr "type" "mrs")])
 

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Ramana Radhakrishnan]

On Tue, Jun 10, 2014 at 12:25 AM, Kugan
<kugan.vivekanandarajah@linaro.org> wrote:
> On 30/05/14 18:35, Ramana Radhakrishnan wrote:
>>> +  if (!TARGET_VFP)
>>> +    return;
>>> +
>>> +  /* Generate the equivalence of :
>>
>> s/equivalence/equivalent.
>>
>> Ok with that change and if no regressions.
>
> Hi Ramana,
>
> Sorry, I missed the thumb1 part. There are no mrc/mcr  versions of these
> instructions in thumb1. So these should be conditional on not being
> ARM_THUMB1.
>

No, this has nothing to do with TARGET_THUMB1 -  the real condition
should be TARGET_VFP && TARGET_HARD_FLOAT. These instructions only
work if TARGET_HARD_FLOAT is true. Thumb1 + VFP instructions is not
possible, similarly if generating code for -mfloat-abi=soft you don't
want these instructions being generated.

Ok if that works.

Ramana


> Is this OK. Regression tested with no new refression on qemu for
> arm-none-linux-gnueabi -march=armv7-a and on arm-none-linux-gnueabi
> --with-mode=thumb and -march=armv5t.
>
> Is this OK?
>
> Thanks,
> Kugan
>
> gcc/
>
> 2014-06-10  Kugan Vivekanandarajah  <kuganv@linaro.org>
>
>         * config/arm/arm.c (arm_atomic_assign_expand_fenv): call
>         default_atomic_assign_expand_fenv for TARGET_THUMB1.
>         (arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
>         __builtins_arm_get_fpscr only when !TARGET_THUMB1.
>         * config/arm/vfp.md (set_fpscr): Make pattern conditional on
>         !TARGERT_THUMB1.
>         (get_fpscr) : Likewise.

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Jay Foad]

On 2 May 2014 10:04, Kugan <kugan.vivekanandarajah@linaro.org> wrote:
> Thanks for spotting it. Here is the updated patch that changes it to
> ARM_FE_*.

> +2014-05-02  Kugan Vivekanandarajah  <kuganv@linaro.org>
> +
> +       * config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
> +       (arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
> +       (bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
> +       and __builtins_arm_get_fpscr.

s/__builtins/__builtin/g

> +       (arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
> +       __builtins_arm_get_fpscr.

s/__builtins/__builtin/g

This doesn't match the code, which initializes builtins "...ldfscr"
and "...stfscr" (with no "p" in "fscr").

> +       (arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
> +       __builtins_arm_ldfpscr.

s/__builtins/__builtin/g

Did you mean "and __builtin_arm_get_fpscr"?

> +#define FP_BUILTIN(L, U) \
> +  {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
> +   UNKNOWN, 0},
> +
> +  FP_BUILTIN (set_fpscr, GET_FPSCR)
> +  FP_BUILTIN (get_fpscr, SET_FPSCR)
> +#undef FP_BUILTIN

This looks like a typo: you have mapped set->GET and get->SET.

Jay.

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Ramana Radhakrishnan]

On Sat, Jul 12, 2014 at 11:40 PM, Kugan
<kugan.vivekanandarajah@linaro.org> wrote:
>>
>> -  if (!TARGET_VFP)
>> -    return;
>> +  if (!TARGET_VFP || TARGET_THUMB1)
>> +    return default_atomic_assign_expand_fenv (hold, clear, update);
>>
>> You don't need to call default function here. It is empty, the
>> documentation says:
>>
>> "The default implementation leaves all three expressions as @code{NULL_TREE}."
>>
>> Also, the function is declared as void, so returning something looks
>> strange to me.
>
> Thanks for the comment. Here is a patch to change this. There was also a
> comment from Jay with respect to a cut and paste error that might
> confuse the readers. I am fixing that as well.
>
> regression tested on qemu for arm-none-linux-gnueabi with no new
> regressions.
>
> Please let me know if this is OK?

Sigh, sorry for missing this earlier. This is OK if no regressions

Ramana

>
> Thanks,
> Kugan
>
> gcc/
> 2014-057-12  Kugan Vivekanandarajah  <kuganv@linaro.org>
>
>         * config/arm/arm.c (bdesc_2arg): Fix typo.
>         (arm_atomic_assign_expand_fenv): Remove The default implementation.

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Kugan]

[-- Attachment #1: Type: text/plain, Size: 908 bytes --]

> 
> -  if (!TARGET_VFP)
> -    return;
> +  if (!TARGET_VFP || TARGET_THUMB1)
> +    return default_atomic_assign_expand_fenv (hold, clear, update);
> 
> You don't need to call default function here. It is empty, the
> documentation says:
> 
> "The default implementation leaves all three expressions as @code{NULL_TREE}."
> 
> Also, the function is declared as void, so returning something looks
> strange to me.

Thanks for the comment. Here is a patch to change this. There was also a
comment from Jay with respect to a cut and paste error that might
confuse the readers. I am fixing that as well.

regression tested on qemu for arm-none-linux-gnueabi with no new
regressions.

Please let me know if this is OK?

Thanks,
Kugan

gcc/
2014-057-12  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* config/arm/arm.c (bdesc_2arg): Fix typo.
	(arm_atomic_assign_expand_fenv): Remove The default implementation.

[-- Attachment #2: fenv.txt --]
[-- Type: text/plain, Size: 843 bytes --]

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 78cae73..b84594d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -24366,8 +24366,8 @@ static const struct builtin_description bdesc_2arg[] =
   {0, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
    UNKNOWN, 0},
 
-  FP_BUILTIN (set_fpscr, GET_FPSCR)
-  FP_BUILTIN (get_fpscr, SET_FPSCR)
+  FP_BUILTIN (get_fpscr, GET_FPSCR)
+  FP_BUILTIN (set_fpscr, SET_FPSCR)
 #undef FP_BUILTIN
 
 #define CRC32_BUILTIN(L, U) \
@@ -31582,7 +31582,7 @@ arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
   tree update_call, atomic_feraiseexcept, hold_fnclex;
 
   if (!TARGET_VFP || !TARGET_HARD_FLOAT)
-    return default_atomic_assign_expand_fenv (hold, clear, update);
+    return;
 
   /* Generate the equivalent of :
        unsigned int fenv_var;

Re: [RFC][ARM] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook

[Uros Bizjak]

Hello!

> 2014-06-10  Kugan Vivekanandarajah  <kuganv@linaro.org>
>
> * config/arm/arm.c (arm_atomic_assign_expand_fenv): call
> default_atomic_assign_expand_fenv for TARGET_THUMB1.
> (arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
> __builtins_arm_get_fpscr only when !TARGET_THUMB1.
> * config/arm/vfp.md (set_fpscr): Make pattern conditional on
> !TARGERT_THUMB1.
> (get_fpscr) : Likewise.

-  if (!TARGET_VFP)
-    return;
+  if (!TARGET_VFP || TARGET_THUMB1)
+    return default_atomic_assign_expand_fenv (hold, clear, update);

You don't need to call default function here. It is empty, the
documentation says:

"The default implementation leaves all three expressions as @code{NULL_TREE}."

Also, the function is declared as void, so returning something looks
strange to me.

Uros.