From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16009 invoked by alias); 13 May 2014 20:09:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 15991 invoked by uid 89); 13 May 2014 20:09:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 May 2014 20:09:02 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1WkJ0S-0005oy-IZ from Sandra_Loosemore@mentor.com ; Tue, 13 May 2014 13:08:56 -0700 Received: from SVR-ORW-FEM-05.mgc.mentorg.com ([147.34.97.43]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 13 May 2014 13:08:56 -0700 Received: from [IPv6:::1] (147.34.91.1) by svr-orw-fem-05.mgc.mentorg.com (147.34.97.43) with Microsoft SMTP Server id 14.2.247.3; Tue, 13 May 2014 13:07:27 -0700 Message-ID: <53727BC3.3060600@codesourcery.com> Date: Tue, 13 May 2014 20:09:00 -0000 From: Sandra Loosemore User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130329 Thunderbird/17.0.5 MIME-Version: 1.0 To: GCC Patches CC: Richard Sandiford Subject: [patch,mips] avoid invalid register for JALR Content-Type: multipart/mixed; boundary="------------070901030603090209090202" X-SW-Source: 2014-05/txt/msg01015.txt.bz2 --------------070901030603090209090202 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1332 When I was trying to benchmark another patch (which I'll be sending along shortly) with CSiBE for -mabi=64, I ran into an assembler error like this: /tmp/ccJv2faG.s: Assembler messages: /tmp/ccJv2faG.s:1605: Error: a destination register must be supplied `jalr $31' Indeed, GCC is generating invalid code here; the single-operand JALR instruction doesn't permit the use of $31 because it is already the implicit destination register. The attached patch introduces a new register class JALR_REGS to represent the valid set of registers for this instruction, and modifies the "c" register constraint to use it. I had some difficulty in regression-testing this patch because of unrelated problems on trunk in the past week -- at first I was getting ICEs due to a null pointer dereference in tree code, then when I tried again a couple days later trunk was not even building. So I ended up testing this patch on a more stable 4.9.0 checkout modified to support Mentor's extended set of mips-sde-elf multilibs instead. OK to commit? -Sandra 2014-05-13 Sandra Loosemore gcc/ * config/mips/mips.h (enum reg_class): Add JALR_REGS. (REG_CLASS_NAMES): Add initializer for JALR_REGS. (REG_CLASS_CONTENTS): Likewise. * config/mips/constraints.md ("c"): Use JALR_REGS instead of GR_REGS. --------------070901030603090209090202 Content-Type: text/x-patch; name="mips-jalr.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="mips-jalr.patch" Content-length: 2006 Index: gcc/config/mips/mips.h =================================================================== --- gcc/config/mips/mips.h (revision 210372) +++ gcc/config/mips/mips.h (working copy) @@ -1840,6 +1840,7 @@ enum reg_class PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ V1_REG, /* Register $v1 ($3) used for TLS access. */ LEA_REGS, /* Every GPR except $25 */ + JALR_REGS, /* integer registers except $31 */ GR_REGS, /* integer registers */ FP_REGS, /* floating point registers */ MD0_REG, /* first multiply/divide register */ @@ -1878,6 +1879,7 @@ enum reg_class "PIC_FN_ADDR_REG", \ "V1_REG", \ "LEA_REGS", \ + "JALR_REGS", \ "GR_REGS", \ "FP_REGS", \ "MD0_REG", \ @@ -1919,6 +1921,7 @@ enum reg_class { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ + { 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ Index: gcc/config/mips/constraints.md =================================================================== --- gcc/config/mips/constraints.md (revision 210372) +++ gcc/config/mips/constraints.md (working copy) @@ -50,7 +50,7 @@ ;; for details. (define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG - : GR_REGS" + : JALR_REGS" "A register suitable for use in an indirect jump. This will always be @code{$25} for @option{-mabicalls}.") --------------070901030603090209090202--