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* [patch,mips] avoid invalid register for JALR
@ 2014-05-13 20:09 Sandra Loosemore
  2014-05-13 21:41 ` Richard Sandiford
  0 siblings, 1 reply; 4+ messages in thread
From: Sandra Loosemore @ 2014-05-13 20:09 UTC (permalink / raw)
  To: GCC Patches; +Cc: Richard Sandiford

[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]

When I was trying to benchmark another patch (which I'll be sending 
along shortly) with CSiBE for -mabi=64, I ran into an assembler error 
like this:

/tmp/ccJv2faG.s: Assembler messages:
/tmp/ccJv2faG.s:1605: Error: a destination register must be supplied
`jalr $31'

Indeed, GCC is generating invalid code here; the single-operand JALR 
instruction doesn't permit the use of $31 because it is already the 
implicit destination register.  The attached patch introduces a new 
register class JALR_REGS to represent the valid set of registers for 
this instruction, and modifies the "c" register constraint to use it.

I had some difficulty in regression-testing this patch because of 
unrelated problems on trunk in the past week -- at first I was getting 
ICEs due to a null pointer dereference in tree code, then when I tried 
again a couple days later trunk was not even building.  So I ended up 
testing this patch on a more stable 4.9.0 checkout modified to support 
Mentor's extended set of mips-sde-elf multilibs instead.

OK to commit?

-Sandra


2014-05-13  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* config/mips/mips.h (enum reg_class): Add JALR_REGS.
	(REG_CLASS_NAMES): Add initializer for JALR_REGS.
	(REG_CLASS_CONTENTS): Likewise.
	* config/mips/constraints.md ("c"): Use JALR_REGS
	instead of GR_REGS.



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Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h	(revision 210372)
+++ gcc/config/mips/mips.h	(working copy)
@@ -1840,6 +1840,7 @@ enum reg_class
   PIC_FN_ADDR_REG,		/* SVR4 PIC function address register */
   V1_REG,			/* Register $v1 ($3) used for TLS access.  */
   LEA_REGS,			/* Every GPR except $25 */
+  JALR_REGS,			/* integer registers except $31 */	
   GR_REGS,			/* integer registers */
   FP_REGS,			/* floating point registers */
   MD0_REG,			/* first multiply/divide register */
@@ -1878,6 +1879,7 @@ enum reg_class
   "PIC_FN_ADDR_REG",							\
   "V1_REG",								\
   "LEA_REGS",								\
+  "JALR_REGS",								\
   "GR_REGS",								\
   "FP_REGS",								\
   "MD0_REG",								\
@@ -1919,6 +1921,7 @@ enum reg_class
   { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* PIC_FN_ADDR_REG */	\
   { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* V1_REG */		\
   { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* LEA_REGS */		\
+  { 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* JALR_REGS */		\
   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* GR_REGS */		\
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* FP_REGS */		\
   { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* MD0_REG */		\
Index: gcc/config/mips/constraints.md
===================================================================
--- gcc/config/mips/constraints.md	(revision 210372)
+++ gcc/config/mips/constraints.md	(working copy)
@@ -50,7 +50,7 @@
 ;; for details.
 (define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
 				 : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
-				 : GR_REGS"
+				 : JALR_REGS"
   "A register suitable for use in an indirect jump.  This will always be
    @code{$25} for @option{-mabicalls}.")
 

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2014-05-16 16:25 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-05-13 20:09 [patch,mips] avoid invalid register for JALR Sandra Loosemore
2014-05-13 21:41 ` Richard Sandiford
2014-05-13 23:56   ` Sandra Loosemore
2014-05-16 16:25     ` Maciej W. Rozycki

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