[AArch64] Implement some vca*_f[32,64] intrinsics

[AArch64] Implement some vca*_f[32,64] intrinsics

[Kyrill Tkachov]

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Hi all,

This patch implements some absolute compare intrinsics in arm_neon.h.

Execution tests are added.
Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux

Ok for trunk?

2014-06-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
     (vcagt_f64): Likewise.
     (vcale_f64): Likewise.
     (vcaled_f64): Likewise.
     (vcales_f32): Likewise.
     (vcalt_f64): Likewise.
     (vcaltd_f64): Likewise.
     (vcalts_f32): Likewise.

2014-06-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * gcc.target/aarch64/simd/vcage_f64.c: New test.
     * gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
     * gcc.target/aarch64/simd/vcale_f64.c: Likewise.
     * gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
     * gcc.target/aarch64/simd/vcales_f32.c: Likewise.
     * gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
     * gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
     * gcc.target/aarch64/simd/vcalts_f32.c: Likewise.

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commit f87169afe8bd853b4aa5ab3ed5e270de0cb95461
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Jun 19 09:37:54 2014 +0100

    [AArch64] Implement vc* intrinsics

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 0ff6996..8fa469a 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -13823,6 +13823,12 @@ vaesimcq_u8 (uint8x16_t data)
 
 /* vcage  */
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcage_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) >= vabs_f64 (__b);
+}
+
 __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
 vcages_f32 (float32_t __a, float32_t __b)
 {
@@ -13867,6 +13873,12 @@ vcagt_f32 (float32x2_t __a, float32x2_t __b)
   return vabs_f32 (__a) > vabs_f32 (__b);
 }
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcagt_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) > vabs_f64 (__b);
+}
+
 __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
 vcagtq_f32 (float32x4_t __a, float32x4_t __b)
 {
@@ -13893,6 +13905,24 @@ vcale_f32 (float32x2_t __a, float32x2_t __b)
   return vabs_f32 (__a) <= vabs_f32 (__b);
 }
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcale_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) <= vabs_f64 (__b);
+}
+
+__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+vcaled_f64 (float64_t __a, float64_t __b)
+{
+  return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
+}
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+vcales_f32 (float32_t __a, float32_t __b)
+{
+  return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
+}
+
 __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
 vcaleq_f32 (float32x4_t __a, float32x4_t __b)
 {
@@ -13913,6 +13943,18 @@ vcalt_f32 (float32x2_t __a, float32x2_t __b)
   return vabs_f32 (__a) < vabs_f32 (__b);
 }
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcalt_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) < vabs_f64 (__b);
+}
+
+__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+vcaltd_f64 (float64_t __a, float64_t __b)
+{
+  return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
+}
+
 __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
 vcaltq_f32 (float32x4_t __a, float32x4_t __b)
 {
@@ -13925,6 +13967,12 @@ vcaltq_f64 (float64x2_t __a, float64x2_t __b)
   return vabsq_f64 (__a) < vabsq_f64 (__b);
 }
 
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+vcalts_f32 (float32_t __a, float32_t __b)
+{
+  return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
+}
+
 /* vceq - vector.  */
 
 __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c
new file mode 100644
index 0000000..67dc8ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c
@@ -0,0 +1,42 @@
+/* Test the vcage_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) >= __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcage_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c
new file mode 100644
index 0000000..8027716
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c
@@ -0,0 +1,42 @@
+/* Test the vcagt_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) > __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcagt_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %ld, got %ld\n",in[i], in[j], expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c
new file mode 100644
index 0000000..122d4ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c
@@ -0,0 +1,42 @@
+/* Test the vcale_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcale_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
new file mode 100644
index 0000000..90baea3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
@@ -0,0 +1,40 @@
+/* Test the vcaled_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcaled_f64 (in[i], in[j]);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c b/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
new file mode 100644
index 0000000..356e8f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
@@ -0,0 +1,40 @@
+/* Test the vcales_f32 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint32_t expected;
+  uint32_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcales_f32 (in[i], in[j]);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %d, got %d\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c
new file mode 100644
index 0000000..886fe4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c
@@ -0,0 +1,42 @@
+/* Test the vcalt_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcalt_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
new file mode 100644
index 0000000..bb4087f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
@@ -0,0 +1,40 @@
+/* Test the vcaltd_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcaltd_f64 (in[i], in[j]);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c b/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
new file mode 100644
index 0000000..b26d072
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
@@ -0,0 +1,40 @@
+/* Test the vcalts_f32 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint32_t expected;
+  uint32_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcalts_f32 (in[i], in[j]);
+
+        if (actual != expected)
+          {
+            fprintf (stderr, "Expected: %d, got %d\n", expected, actual);
+            abort ();
+          }
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

[Kyrill Tkachov]

Ping.
https://gcc.gnu.org/ml/gcc-patches/2014-06/msg01771.html

Kyrill


On 23/06/14 15:30, Kyrill Tkachov wrote:
> Hi all,
>
> This patch implements some absolute compare intrinsics in arm_neon.h.
>
> Execution tests are added.
> Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux
>
> Ok for trunk?
>
> 2014-06-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>       * config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
>       (vcagt_f64): Likewise.
>       (vcale_f64): Likewise.
>       (vcaled_f64): Likewise.
>       (vcales_f32): Likewise.
>       (vcalt_f64): Likewise.
>       (vcaltd_f64): Likewise.
>       (vcalts_f32): Likewise.
>
> 2014-06-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>       * gcc.target/aarch64/simd/vcage_f64.c: New test.
>       * gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
>       * gcc.target/aarch64/simd/vcale_f64.c: Likewise.
>       * gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
>       * gcc.target/aarch64/simd/vcales_f32.c: Likewise.
>       * gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
>       * gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
>       * gcc.target/aarch64/simd/vcalts_f32.c: Likewise.

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

[Marcus Shawcroft]

On 23 June 2014 15:30, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
> Hi all,
>
> This patch implements some absolute compare intrinsics in arm_neon.h.
>
> Execution tests are added.
> Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux


+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+

Drop the dependence on stdio.h please.

+            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);

No need to print the expected value, abort( i alone is fine.  Dropping
the printf will make the #include above go away.

Ok with those changes.

/Marcus

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

[Christophe Lyon]

Hi,

It seems some of the scan-assembler directives fail:
http://cbuild.validation.linaro.org/build/cross-validation/gcc/trunk/212196/aarch64-none-elf/diff-gcc-rh50-aarch64-none-elf-default-default-default.txt

Christophe.


On 1 July 2014 14:13, Marcus Shawcroft <marcus.shawcroft@gmail.com> wrote:
> On 23 June 2014 15:30, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
>> Hi all,
>>
>> This patch implements some absolute compare intrinsics in arm_neon.h.
>>
>> Execution tests are added.
>> Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux
>
>
> +/* { dg-do run } */
> +/* { dg-options "-save-temps -O3" } */
> +
> +#include "arm_neon.h"
> +#include <stdio.h>
> +
>
> Drop the dependence on stdio.h please.
>
> +            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
>
> No need to print the expected value, abort( i alone is fine.  Dropping
> the printf will make the #include above go away.
>
> Ok with those changes.
>
> /Marcus

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

[Kyrill Tkachov]

On 02/07/14 08:59, Christophe Lyon wrote:
> Hi,
>
> It seems some of the scan-assembler directives fail:
> http://cbuild.validation.linaro.org/build/cross-validation/gcc/trunk/212196/aarch64-none-elf/diff-gcc-rh50-aarch64-none-elf-default-default-default.txt
Hi Christophe

Yes, turns out removing the printf at the end lets gcc fold away parts 
of the test.
It's just a testism, will send a patch out soon.

Thanks,
Kyrill

>
> Christophe.
>
>
> On 1 July 2014 14:13, Marcus Shawcroft <marcus.shawcroft@gmail.com> wrote:
>> On 23 June 2014 15:30, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
>>> Hi all,
>>>
>>> This patch implements some absolute compare intrinsics in arm_neon.h.
>>>
>>> Execution tests are added.
>>> Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux
>>
>> +/* { dg-do run } */
>> +/* { dg-options "-save-temps -O3" } */
>> +
>> +#include "arm_neon.h"
>> +#include <stdio.h>
>> +
>>
>> Drop the dependence on stdio.h please.
>>
>> +            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
>>
>> No need to print the expected value, abort( i alone is fine.  Dropping
>> the printf will make the #include above go away.
>>
>> Ok with those changes.
>>
>> /Marcus

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

[Kyrill Tkachov]

[-- Attachment #1: Type: text/plain, Size: 1553 bytes --]


On 02/07/14 08:59, Christophe Lyon wrote:
> Hi,
>
> It seems some of the scan-assembler directives fail:
> http://cbuild.validation.linaro.org/build/cross-validation/gcc/trunk/212196/aarch64-none-elf/diff-gcc-rh50-aarch64-none-elf-default-default-default.txt
>
> Christophe.

This patch should fix the tests by marking the appropriate variable 
volatile.
Sorry for the delay and breakage.
Ok for trunk?

Thanks,
Kyrill

2014-07-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * gcc.target/aarch64/simd/vcaled_f64.c: Mark expected value volatile.
     * gcc.target/aarch64/simd/vcales_f32.c: Likewise.
     * gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
     * gcc.target/aarch64/simd/vcalts_f32.c: Likewise.

>
> On 1 July 2014 14:13, Marcus Shawcroft <marcus.shawcroft@gmail.com> wrote:
>> On 23 June 2014 15:30, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
>>> Hi all,
>>>
>>> This patch implements some absolute compare intrinsics in arm_neon.h.
>>>
>>> Execution tests are added.
>>> Tested aarch64-none-elf, aarch64_be-none-elf, bootstrapped on aarch64 linux
>>
>> +/* { dg-do run } */
>> +/* { dg-options "-save-temps -O3" } */
>> +
>> +#include "arm_neon.h"
>> +#include <stdio.h>
>> +
>>
>> Drop the dependence on stdio.h please.
>>
>> +            fprintf (stderr, "Expected: %ld, got %ld\n", expected, actual);
>>
>> No need to print the expected value, abort( i alone is fine.  Dropping
>> the printf will make the #include above go away.
>>
>> Ok with those changes.
>>
>> /Marcus

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: aarch64-vca-tests.patch --]
[-- Type: text/x-patch; name=aarch64-vca-tests.patch, Size: 1882 bytes --]

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
index 9ea31d6..5cb69fe 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
@@ -14,7 +14,7 @@ volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
 int
 main (void)
 {
-  uint64_t expected;
+  volatile uint64_t expected;
   uint64_t actual;
 
   int i, j;
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c b/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
index a69a096..cc87a63 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
@@ -14,7 +14,7 @@ volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
 int
 main (void)
 {
-  uint32_t expected;
+  volatile uint32_t expected;
   uint32_t actual;
 
   int i, j;
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
index fcdd75b..6ae9d8a 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
@@ -14,7 +14,7 @@ volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
 int
 main (void)
 {
-  uint64_t expected;
+  volatile uint64_t expected;
   uint64_t actual;
 
   int i, j;
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c b/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
index 0799dd7..88d3eb3 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
@@ -14,7 +14,7 @@ volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
 int
 main (void)
 {
-  uint32_t expected;
+  volatile uint32_t expected;
   uint32_t actual;
 
   int i, j;

Re: [AArch64] Implement some vca*_f[32,64] intrinsics

[Marcus Shawcroft]

On 10 July 2014 08:56, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
>
> On 02/07/14 08:59, Christophe Lyon wrote:
>>
>> Hi,
>>
>> It seems some of the scan-assembler directives fail:
>>
>> http://cbuild.validation.linaro.org/build/cross-validation/gcc/trunk/212196/aarch64-none-elf/diff-gcc-rh50-aarch64-none-elf-default-default-default.txt
>>
>> Christophe.
>
>
> This patch should fix the tests by marking the appropriate variable
> volatile.
> Sorry for the delay and breakage.
> Ok for trunk?

OK /Marcus