From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10282 invoked by alias); 30 Jun 2014 15:21:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 10270 invoked by uid 89); 30 Jun 2014 15:21:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,T_MANY_HDRS_LCASE,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mailout1.w1.samsung.com Received: from mailout1.w1.samsung.com (HELO mailout1.w1.samsung.com) (210.118.77.11) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (DES-CBC3-SHA encrypted) ESMTPS; Mon, 30 Jun 2014 15:21:53 +0000 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N7Z006VGMO8RX90@mailout1.w1.samsung.com> for gcc-patches@gcc.gnu.org; Mon, 30 Jun 2014 16:21:44 +0100 (BST) Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 31.9C.19257.C8081B35; Mon, 30 Jun 2014 16:21:48 +0100 (BST) Received: from [106.109.129.103] by eusync4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N7Z000SDMOBLL10@eusync4.samsung.com>; Mon, 30 Jun 2014 16:21:48 +0100 (BST) Message-id: <53B1808D.3070704@samsung.com> Date: Mon, 30 Jun 2014 15:21:00 -0000 From: Marat Zakirov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-version: 1.0 To: "gcc-patches@gcc.gnu.org" Cc: Ramana Radhakrishnan , Richard Earnshaw , Kyrill Tkachov , Slava Garbuzov , Yuri Gribov , marat61@gmail.com Subject: [PING][PATCH] Fix for PR 61561 Content-type: multipart/mixed; boundary=------------020104060909070906030400 X-SW-Source: 2014-06/txt/msg02410.txt.bz2 This is a multi-part message in MIME format. --------------020104060909070906030400 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1500 This is a reminder message on fix for PR 61561 which is ICE while compiling something which is valid* 'C' code. (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561). Ramana, Richard, I am very appreciated for your attention and error indication, your work made my patch simple and tiny. And I hope that this patch will save somebody's time. Additional info about the issue: By adding constrain 'k' we want to make gcc work properly with stack register in HI and QI mode. This is need because CSE an RTL phase in some cases propagates sp register directly to HI/QI memory set. Next reload an RTL phase trying to build HI/QI move sp into some general purpose register which is fail due to pattern absence. You may ask who needs part of sp register? Nevertheless it is legitimate operation and there is simple example of practical usage. Imagine you put some local variable 'a' into hash table which has < 256 bunches. In this case 'operator []' of some hash class may take QI from sp register which is directly pointing on 'a'. Patch was reg. tested on --build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu --target=arm-v7a15v5r2-linux-gnueabi for c,c++,fortran languages w/o bootstrap. * According to 'C' Standard [ISO/IEC 9899:2011] 6.3.2.3 "Any pointer type may be converted to an integer type. Except as previously specified, the result is implementation-defined". As we know 'char' and 'short' (also called 'short int') are both integers. Thank for your attention. Marat. --------------020104060909070906030400 Content-Type: text/x-patch; name="arm.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="arm.diff" Content-length: 1916 gcc/ChangeLog: 2014-06-30 Marat Zakirov PR target/61561 * config/arm/arm.md (*movhi_insn_arch4): Handle stack pointer. (*movhi_bytes): Likewise. (*arm_movqi_insn): Likewise. gcc/testsuite/ChangeLog: 2014-06-30 Marat Zakirov PR target/61561 * gcc.dg/pr61561.c: New test. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 42c12c8..99290dc 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6291,7 +6291,7 @@ ;; Pattern to recognize insn generated default case above (define_insn "*movhi_insn_arch4" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") - (match_operand:HI 1 "general_operand" "rI,K,r,mi"))] + (match_operand:HI 1 "general_operand" "rIk,K,r,mi"))] "TARGET_ARM && arm_arch4 && (register_operand (operands[0], HImode) @@ -6315,7 +6315,7 @@ (define_insn "*movhi_bytes" [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") - (match_operand:HI 1 "arm_rhs_operand" "I,r,K"))] + (match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))] "TARGET_ARM" "@ mov%?\\t%0, %1\\t%@ movhi @@ -6430,7 +6430,7 @@ (define_insn "*arm_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,r,l,Uu,r,m") - (match_operand:QI 1 "general_operand" "r,r,I,Py,K,Uu,l,m,r"))] + (match_operand:QI 1 "general_operand" "rk,rk,I,Py,K,Uu,l,m,r"))] "TARGET_32BIT && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" diff --git a/gcc/testsuite/gcc.dg/pr61561.c b/gcc/testsuite/gcc.dg/pr61561.c new file mode 100644 index 0000000..0f4b716 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr61561.c @@ -0,0 +1,15 @@ +/* PR c/61561. */ +/* { dg-do assemble } */ +/* { dg-options " -w -O2" } */ + +int dummy (int a); + +char a; +short b; + +void mmm (void) +{ + char dyn[dummy (3)]; + a = (char)&dyn[0]; + b = (short)&dyn[0]; +} --------------020104060909070906030400--