From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24774 invoked by alias); 8 Jul 2014 08:56:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 24752 invoked by uid 89); 8 Jul 2014 08:56:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: collaborate-mta1.arm.com Received: from fw-tnat.austin.arm.com (HELO collaborate-mta1.arm.com) (217.140.110.23) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 08 Jul 2014 08:56:43 +0000 Received: from [10.1.209.178] (e106919-lin.cambridge.arm.com [10.1.209.178]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id BB7DA13F884; Tue, 8 Jul 2014 03:56:34 -0500 (CDT) Message-ID: <53BBB241.4040200@arm.com> Date: Tue, 08 Jul 2014 08:56:00 -0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Bin Cheng CC: Richard Earnshaw , gcc-patches Subject: Re: [PATCH ARM] Improve ARM memset inlining References: <003301cf641f$36733f40$a359bdc0$@arm.com> <5363A4CF.9050904@arm.com> <003f01cf6832$9cf921a0$d6eb64e0$@arm.com> <004401cf68e7$fff1bb40$ffd531c0$@arm.com> <000301cf9781$fd11c7d0$f7355770$@arm.com> In-Reply-To: <000301cf9781$fd11c7d0$f7355770$@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2014-07/txt/msg00523.txt.bz2 > > Hi Ramana, > This is the rebased patch, there is no conflict against latest trunk. I am still doing some tests. Is it OK if tests are fine? > Also, it depends on patch at https://gcc.gnu.org/ml/gcc-patches/2014-04/msg01923.html, I will update that patch two. > > Thanks, > bin > Index: gcc/config/arm/arm.c > =================================================================== > --- gcc/config/arm/arm.c (revision 212295) > +++ gcc/config/arm/arm.c (working copy) > @@ -1588,34 +1588,38 @@ const struct tune_params arm_slowmul_tune = > { > arm_slowmul_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 3, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 3, /* Constant limit. */ > + 5, /* Max cond insns. */ Please make sure alignment is maintained with comments as today. I'm not sure why I see the following diffs in your patch since you don't really should be touching those lines, that applies to all the cost tables. I haven't called out all the places where you appear to have unrelated formatting changes in detail, but have done so in one cost table. Please re-create a patch that doesn't have these hunks. > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ Likewise. > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ Likewise. > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_fastmul_tune = > { > arm_fastmul_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > /* StrongARM has early execution of branches, so a sequence that is worth > @@ -1625,17 +1629,19 @@ const struct tune_params arm_strongarm_tune = > { > arm_fastmul_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 3, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 3, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_xscale_tune = > @@ -1643,50 +1649,56 @@ const struct tune_params arm_xscale_tune = > arm_xscale_rtx_costs, > NULL, > xscale_sched_adjust_cost, > - 2, /* Constant limit. */ > - 3, /* Max cond insns. */ > + 2, /* Constant limit. */ > + 3, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_9e_tune = > { > arm_9e_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_v6t2_tune = > { > arm_9e_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > /* Generic Cortex tuning. Use more specific tunings if appropriate. */ > @@ -1694,34 +1706,38 @@ const struct tune_params arm_cortex_tune = > { > arm_9e_rtx_costs, > &generic_extra_costs, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a8_tune = > { > arm_9e_rtx_costs, > &cortexa8_extra_costs, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + true, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a7_tune = > @@ -1729,67 +1745,75 @@ const struct tune_params arm_cortex_a7_tune = > arm_9e_rtx_costs, > &cortexa7_extra_costs, > NULL, > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + true, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a15_tune = > { > arm_9e_rtx_costs, > &cortexa15_extra_costs, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 2, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 2, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - true, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - true, true /* Prefer 32-bit encodings. */ > + true, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + true, true, /* Prefer 32-bit encodings. */ > + true, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a53_tune = > { > arm_9e_rtx_costs, > &cortexa53_extra_costs, > - NULL, /* Scheduler cost adjustment. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Scheduler cost adjustment. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a57_tune = > { > arm_9e_rtx_costs, > &cortexa57_extra_costs, > - NULL, /* Scheduler cost adjustment. */ > - 1, /* Constant limit. */ > - 2, /* Max cond insns. */ > + NULL, /* Scheduler cost adjustment. */ > + 1, /* Constant limit. */ > + 2, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - true, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - true, true /* Prefer 32-bit encodings. */ > + true, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + true, true, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > /* Branches can be dual-issued on Cortex-A5, so conditional execution is > @@ -1799,17 +1823,19 @@ const struct tune_params arm_cortex_a5_tune = > { > arm_9e_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 1, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 1, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_cortex_a5_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {false, false}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {false, false}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + true, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a9_tune = > @@ -1817,16 +1843,18 @@ const struct tune_params arm_cortex_a9_tune = > arm_9e_rtx_costs, > &cortexa9_extra_costs, > cortex_a9_sched_adjust_cost, > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_BENEFICIAL(4,32,32), > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_cortex_a12_tune = > @@ -1834,16 +1862,18 @@ const struct tune_params arm_cortex_a12_tune = > arm_9e_rtx_costs, > &cortexa12_extra_costs, > NULL, > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_BENEFICIAL(4,32,32), > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - true, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + true, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + true, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single > @@ -1857,17 +1887,19 @@ const struct tune_params arm_v7m_tune = > { > arm_9e_rtx_costs, > &v7m_extra_costs, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 2, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 2, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ > arm_cortex_m_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {false, false}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {false, false}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than > @@ -1876,17 +1908,19 @@ const struct tune_params arm_v6m_tune = > { > arm_9e_rtx_costs, > NULL, > - NULL, /* Sched adj cost. */ > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + NULL, /* Sched adj cost. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - false, /* Prefer constant pool. */ > + false, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {false, false}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {false, false}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > const struct tune_params arm_fa726te_tune = > @@ -1894,16 +1928,18 @@ const struct tune_params arm_fa726te_tune = > arm_9e_rtx_costs, > NULL, > fa726te_sched_adjust_cost, > - 1, /* Constant limit. */ > - 5, /* Max cond insns. */ > + 1, /* Constant limit. */ > + 5, /* Max cond insns. */ > ARM_PREFETCH_NOT_BENEFICIAL, > - true, /* Prefer constant pool. */ > + true, /* Prefer constant pool. */ > arm_default_branch_cost, > - false, /* Prefer LDRD/STRD. */ > - {true, true}, /* Prefer non short circuit. */ > - &arm_default_vec_cost, /* Vectorizer costs. */ > - false, /* Prefer Neon for 64-bits bitops. */ > - false, false /* Prefer 32-bit encodings. */ > + false, /* Prefer LDRD/STRD. */ > + {true, true}, /* Prefer non short circuit. */ > + &arm_default_vec_cost, /* Vectorizer costs. */ > + false, /* Prefer Neon for 64-bits bitops. */ > + false, false, /* Prefer 32-bit encodings. */ > + false, /* Prefer Neon for stringops. */ > + 8 /* Maximum insns to inline memset. */ > }; > > Thanks, > bin >