[PATCH][ARM][5/7] Convert FP mnemonics to UAL | sqrt and FP compare patterns

[PATCH][ARM][5/7] Convert FP mnemonics to UAL | sqrt and FP compare patterns

[Kyrill Tkachov]

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Hi all,

The sqrt and floating point compare patterns.
For the case when we compare with floating-point 0 the ARM ARM uses the 
syntax 'vcmp {s,d}<n>, #0.0'
but current gas has a bug and doesn't accept that form, only 'vcmp 
{s,d}<n>, #0'

There is a gas patch in review on the binutils mailing list but in the 
meantime we output #0
Testing binutils didn't complain.

Ok for trunk?

Thanks,
Kyrill

2014-08-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/vfp.md (*sqrtsf2_vfp): Use UAL assembly syntax.
     (*sqrtdf2_vfp): Likewise.
     (*cmpsf_vfp): Likewise.
     (*cmpsf_trap_vfp): Likewise.
     (*cmpdf_vfp): Likewise.
     (*cmpdf_trap_vfp): Likewise.

2014-08-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * gcc.target/arm/vfp-1.c: Updated expected assembly.

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commit ce05645f530212265b5792b8881f4fd4ef60c7bc
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Jul 17 10:05:17 2014 +0100

    [ARM][5/n] Convert FP mnemonics to UAL | sqrt and FP compare patterns

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index d872a6e..1dc1cc2 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1082,7 +1082,7 @@ (define_insn "*sqrtsf2_vfp"
   [(set (match_operand:SF	   0 "s_register_operand" "=&t,t")
 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
-  "fsqrts%?\\t%0, %1"
+  "vsqrt%?.f32\\t%0, %1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "arch" "*,armv6_or_vfpv3")
@@ -1093,7 +1093,7 @@ (define_insn "*sqrtdf2_vfp"
   [(set (match_operand:DF	   0 "s_register_operand" "=&w,w")
 	(sqrt:DF (match_operand:DF 1 "s_register_operand" "w,w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
-  "fsqrtd%?\\t%P0, %P1"
+  "vsqrt%?.f64\\t%P0, %P1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "arch" "*,armv6_or_vfpv3")
@@ -1175,14 +1175,17 @@ (define_insn_and_split "*cmpdf_trap_split_vfp"
 
 ;; Comparison patterns
 
+;; In the compare with FP zero case the ARM Architecture Reference Manual
+;; specifies the immediate to be #0.0.  However, some buggy assemblers only
+;; accept #0.  We don't want to autodetect broken assemblers, so output #0.
 (define_insn "*cmpsf_vfp"
   [(set (reg:CCFP VFPCC_REGNUM)
 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
 		      (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
   "@
-   fcmps%?\\t%0, %1
-   fcmpzs%?\\t%0"
+   vcmp%?.f32\\t%0, %1
+   vcmp%?.f32\\t%0, #0"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "type" "fcmps")]
@@ -1194,8 +1197,8 @@ (define_insn "*cmpsf_trap_vfp"
 		       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
   "@
-   fcmpes%?\\t%0, %1
-   fcmpezs%?\\t%0"
+   vcmpe%?.f32\\t%0, %1
+   vcmpe%?.f32\\t%0, #0"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "type" "fcmps")]
@@ -1207,8 +1210,8 @@ (define_insn "*cmpdf_vfp"
 		      (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
   "@
-   fcmpd%?\\t%P0, %P1
-   fcmpzd%?\\t%P0"
+   vcmp%?.f64\\t%P0, %P1
+   vcmp%?.f64\\t%P0, #0"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "type" "fcmpd")]
@@ -1220,8 +1223,8 @@ (define_insn "*cmpdf_trap_vfp"
 		       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
   "@
-   fcmped%?\\t%P0, %P1
-   fcmpezd%?\\t%P0"
+   vcmpe%?.f64\\t%P0, %P1
+   vcmpe%?.f64\\t%P0, #0"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
    (set_attr "type" "fcmpd")]
diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc/testsuite/gcc.target/arm/vfp-1.c
index 1a970a7..8ceef2b 100644
--- a/gcc/testsuite/gcc.target/arm/vfp-1.c
+++ b/gcc/testsuite/gcc.target/arm/vfp-1.c
@@ -44,7 +44,7 @@ void test_sf() {
   /* { dg-final { scan-assembler "vnmla.f32" } } */
   f1 = -f2 * f3 - f1;
   /* sqrtsf2_vfp */
-  /* { dg-final { scan-assembler "fsqrts" } } */
+  /* { dg-final { scan-assembler "vsqrt.f32" } } */
   f1 = sqrtf (f1);
 }
 
@@ -85,7 +85,7 @@ void test_df() {
   /* { dg-final { scan-assembler "vnmla.f64" } } */
   d1 = -d2 * d3 - d1;
   /* sqrtdf2_vfp */
-  /* { dg-final { scan-assembler "fsqrtd" } } */
+  /* { dg-final { scan-assembler "vsqrt.f64" } } */
   d1 = sqrt (d1);
 }
 

Re: [PATCH][ARM][5/7] Convert FP mnemonics to UAL | sqrt and FP compare patterns

[Ramana Radhakrishnan]

On Tue, Aug 19, 2014 at 4:04 PM, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
> Hi all,
>
> The sqrt and floating point compare patterns.
> For the case when we compare with floating-point 0 the ARM ARM uses the
> syntax 'vcmp {s,d}<n>, #0.0'
> but current gas has a bug and doesn't accept that form, only 'vcmp {s,d}<n>,
> #0'
>
> There is a gas patch in review on the binutils mailing list but in the
> meantime we output #0
> Testing binutils didn't complain.

Ok (I think we'll just have to live with #0 for a long time).

Ramana

>
> Ok for trunk?
>
> Thanks,
> Kyrill
>
> 2014-08-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>     * config/arm/vfp.md (*sqrtsf2_vfp): Use UAL assembly syntax.
>     (*sqrtdf2_vfp): Likewise.
>     (*cmpsf_vfp): Likewise.
>     (*cmpsf_trap_vfp): Likewise.
>     (*cmpdf_vfp): Likewise.
>     (*cmpdf_trap_vfp): Likewise.
>
> 2014-08-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>     * gcc.target/arm/vfp-1.c: Updated expected assembly.