From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 324A13858D38 for ; Mon, 11 Sep 2023 15:59:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 324A13858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353722.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38BFdHKt004001 for ; Mon, 11 Sep 2023 15:59:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=mmS8XIHEurukKHgzBV86zy9FJY22h35lO/DVLPixtHA=; b=L0BHx+Dcl0+2Qi2toHysPWRxo4rIEnssaDWJA2COzmXTuTMAJO5xJdBnTnFZsBWnvnsA 7i0V2wkMSUUbowoipSXYTanW6EafiIt4WWeWDfY0NH+m6sZ1IV4+KepdC7uVEXqSLx4j lturIkhLdHbhet8rKy3i9pXP8XNJeWPkmL11ErMCPx+ok8CWtnue3deT0eODmLp+mWXe OoP1H6wX5g2f53KqWFm8UmF3U7rgwAY6LIUQTIMGWZHvJX/ZnRkCHLaMnQ9u9vKv3GSa cfbP7nbcEW9FjSM5+r6YJfsJbjDC9uXttGfDV6HwuMu90UpqmR5vmr5d5XecDoWV0Ax4 Vw== Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3t250ca87t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 11 Sep 2023 15:59:15 +0000 Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 38BF1H7l022728 for ; Mon, 11 Sep 2023 15:59:14 GMT Received: from smtprelay03.fra02v.mail.ibm.com ([9.218.2.224]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3t141nbu3f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 11 Sep 2023 15:59:14 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay03.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 38BFxBou59244898 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 11 Sep 2023 15:59:11 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6CE332004B; Mon, 11 Sep 2023 15:59:11 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A28720040; Mon, 11 Sep 2023 15:59:11 +0000 (GMT) Received: from [9.179.13.65] (unknown [9.179.13.65]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 11 Sep 2023 15:59:11 +0000 (GMT) Message-ID: <53c077b8-12b6-948c-86f7-2bad984a25b3@linux.ibm.com> Date: Mon, 11 Sep 2023 17:59:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] s390: Fix builtins vec_rli and verll Content-Language: en-US To: Stefan Schulze Frielinghaus Cc: gcc-patches@gcc.gnu.org References: <20230821155610.2553-2-stefansf@linux.ibm.com> <661108c1-ea3e-c376-2319-a19ff7dcc40f@linux.ibm.com> From: Andreas Krebbel In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: nED68Ln_um6NAHPG_s_j22k8rHBDT9k0 X-Proofpoint-ORIG-GUID: nED68Ln_um6NAHPG_s_j22k8rHBDT9k0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-11_10,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309110143 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,NICE_REPLY_A,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 9/11/23 08:56, Stefan Schulze Frielinghaus wrote: > On Mon, Aug 28, 2023 at 11:33:37AM +0200, Andreas Krebbel wrote: >> Hi Stefan, >> >> do you really need to introduce a new flag for U64 given that the type of the builtin is unsigned long? > > In function s390_const_operand_ok the immediate is checked whether it is > valide w.r.t. the flag: > > tree_to_uhwi (arg) > ((HOST_WIDE_INT_1U << (bitwidth - 1) << 1) - 1) > > Here bitwidth is derived from the flag. I see, it is about enabling the constant check at all. Ok, thanks! Andreas > > Cheers, > Stefan > >> >> Andreas >> >> On 8/21/23 17:56, Stefan Schulze Frielinghaus wrote: >>> The second argument of these builtins is an unsigned immediate. For >>> vec_rli the API allows immediates up to 64 bits whereas the instruction >>> verll only allows immediates up to 32 bits. Since the shift count >>> equals the immediate modulo vector element size, truncating those >>> immediates is fine. >>> >>> Bootstrapped and regtested on s390. Ok for mainline? >>> >>> gcc/ChangeLog: >>> >>> * config/s390/s390-builtins.def (O_U64): New. >>> (O1_U64): Ditto. >>> (O2_U64): Ditto. >>> (O3_U64): Ditto. >>> (O4_U64): Ditto. >>> (O_M12): Change bit position. >>> (O_S2): Ditto. >>> (O_S3): Ditto. >>> (O_S4): Ditto. >>> (O_S5): Ditto. >>> (O_S8): Ditto. >>> (O_S12): Ditto. >>> (O_S16): Ditto. >>> (O_S32): Ditto. >>> (O_ELEM): Ditto. >>> (O_LIT): Ditto. >>> (OB_DEF_VAR): Add operand constraints. >>> (B_DEF): Ditto. >>> * config/s390/s390.cc (s390_const_operand_ok): Honour 64 bit >>> operands. >>> --- >>> gcc/config/s390/s390-builtins.def | 60 ++++++++++++++++++------------- >>> gcc/config/s390/s390.cc | 6 ++-- >>> 2 files changed, 39 insertions(+), 27 deletions(-) >>> >>> diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def >>> index a16983b18bd..c829f445a11 100644 >>> --- a/gcc/config/s390/s390-builtins.def >>> +++ b/gcc/config/s390/s390-builtins.def >>> @@ -28,6 +28,7 @@ >>> #undef O_U12 >>> #undef O_U16 >>> #undef O_U32 >>> +#undef O_U64 >>> >>> #undef O_M12 >>> >>> @@ -88,6 +89,11 @@ >>> #undef O3_U32 >>> #undef O4_U32 >>> >>> +#undef O1_U64 >>> +#undef O2_U64 >>> +#undef O3_U64 >>> +#undef O4_U64 >>> + >>> #undef O1_M12 >>> #undef O2_M12 >>> #undef O3_M12 >>> @@ -157,20 +163,21 @@ >>> #define O_U12 7 /* unsigned 16 bit literal */ >>> #define O_U16 8 /* unsigned 16 bit literal */ >>> #define O_U32 9 /* unsigned 32 bit literal */ >>> +#define O_U64 10 /* unsigned 64 bit literal */ >>> >>> -#define O_M12 10 /* matches bitmask of 12 */ >>> +#define O_M12 11 /* matches bitmask of 12 */ >>> >>> -#define O_S2 11 /* signed 2 bit literal */ >>> -#define O_S3 12 /* signed 3 bit literal */ >>> -#define O_S4 13 /* signed 4 bit literal */ >>> -#define O_S5 14 /* signed 5 bit literal */ >>> -#define O_S8 15 /* signed 8 bit literal */ >>> -#define O_S12 16 /* signed 12 bit literal */ >>> -#define O_S16 17 /* signed 16 bit literal */ >>> -#define O_S32 18 /* signed 32 bit literal */ >>> +#define O_S2 12 /* signed 2 bit literal */ >>> +#define O_S3 13 /* signed 3 bit literal */ >>> +#define O_S4 14 /* signed 4 bit literal */ >>> +#define O_S5 15 /* signed 5 bit literal */ >>> +#define O_S8 16 /* signed 8 bit literal */ >>> +#define O_S12 17 /* signed 12 bit literal */ >>> +#define O_S16 18 /* signed 16 bit literal */ >>> +#define O_S32 19 /* signed 32 bit literal */ >>> >>> -#define O_ELEM 19 /* Element selector requiring modulo arithmetic. */ >>> -#define O_LIT 20 /* Operand must be a literal fitting the target type. */ >>> +#define O_ELEM 20 /* Element selector requiring modulo arithmetic. */ >>> +#define O_LIT 21 /* Operand must be a literal fitting the target type. */ >>> >>> #define O_SHIFT 5 >>> >>> @@ -223,6 +230,11 @@ >>> #define O3_U32 (O_U32 << (2 * O_SHIFT)) >>> #define O4_U32 (O_U32 << (3 * O_SHIFT)) >>> >>> +#define O1_U64 O_U64 >>> +#define O2_U64 (O_U64 << O_SHIFT) >>> +#define O3_U64 (O_U64 << (2 * O_SHIFT)) >>> +#define O4_U64 (O_U64 << (3 * O_SHIFT)) >>> + >>> #define O1_M12 O_M12 >>> #define O2_M12 (O_M12 << O_SHIFT) >>> #define O3_M12 (O_M12 << (2 * O_SHIFT)) >>> @@ -1989,19 +2001,19 @@ B_DEF (s390_verllvf, vrotlv4si3, 0, >>> B_DEF (s390_verllvg, vrotlv2di3, 0, B_VX, 0, BT_FN_UV2DI_UV2DI_UV2DI) >>> >>> OB_DEF (s390_vec_rli, s390_vec_rli_u8, s390_vec_rli_s64, B_VX, BT_FN_OV4SI_OV4SI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_u8, s390_verllb, 0, 0, BT_OV_UV16QI_UV16QI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_s8, s390_verllb, 0, 0, BT_OV_V16QI_V16QI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_u16, s390_verllh, 0, 0, BT_OV_UV8HI_UV8HI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_s16, s390_verllh, 0, 0, BT_OV_V8HI_V8HI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_u32, s390_verllf, 0, 0, BT_OV_UV4SI_UV4SI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_s32, s390_verllf, 0, 0, BT_OV_V4SI_V4SI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_u64, s390_verllg, 0, 0, BT_OV_UV2DI_UV2DI_ULONG) >>> -OB_DEF_VAR (s390_vec_rli_s64, s390_verllg, 0, 0, BT_OV_V2DI_V2DI_ULONG) >>> - >>> -B_DEF (s390_verllb, rotlv16qi3, 0, B_VX, 0, BT_FN_UV16QI_UV16QI_UINT) >>> -B_DEF (s390_verllh, rotlv8hi3, 0, B_VX, 0, BT_FN_UV8HI_UV8HI_UINT) >>> -B_DEF (s390_verllf, rotlv4si3, 0, B_VX, 0, BT_FN_UV4SI_UV4SI_UINT) >>> -B_DEF (s390_verllg, rotlv2di3, 0, B_VX, 0, BT_FN_UV2DI_UV2DI_UINT) >>> +OB_DEF_VAR (s390_vec_rli_u8, s390_verllb, 0, O2_U64, BT_OV_UV16QI_UV16QI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_s8, s390_verllb, 0, O2_U64, BT_OV_V16QI_V16QI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_u16, s390_verllh, 0, O2_U64, BT_OV_UV8HI_UV8HI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_s16, s390_verllh, 0, O2_U64, BT_OV_V8HI_V8HI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_u32, s390_verllf, 0, O2_U64, BT_OV_UV4SI_UV4SI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_s32, s390_verllf, 0, O2_U64, BT_OV_V4SI_V4SI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_u64, s390_verllg, 0, O2_U64, BT_OV_UV2DI_UV2DI_ULONG) >>> +OB_DEF_VAR (s390_vec_rli_s64, s390_verllg, 0, O2_U64, BT_OV_V2DI_V2DI_ULONG) >>> + >>> +B_DEF (s390_verllb, rotlv16qi3, 0, B_VX, O2_U32, BT_FN_UV16QI_UV16QI_UINT) >>> +B_DEF (s390_verllh, rotlv8hi3, 0, B_VX, O2_U32, BT_FN_UV8HI_UV8HI_UINT) >>> +B_DEF (s390_verllf, rotlv4si3, 0, B_VX, O2_U32, BT_FN_UV4SI_UV4SI_UINT) >>> +B_DEF (s390_verllg, rotlv2di3, 0, B_VX, O2_U32, BT_FN_UV2DI_UV2DI_UINT) >>> >>> OB_DEF (s390_vec_rl_mask, s390_vec_rl_mask_s8,s390_vec_rl_mask_u64,B_VX, BT_FN_OV4SI_OV4SI_OV4SI_UCHAR) >>> OB_DEF_VAR (s390_vec_rl_mask_s8, s390_verimb, 0, O3_U8, BT_OV_V16QI_V16QI_UV16QI_UCHAR) >>> diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc >>> index 49ab4fc7360..64f56d8effa 100644 >>> --- a/gcc/config/s390/s390.cc >>> +++ b/gcc/config/s390/s390.cc >>> @@ -815,8 +815,8 @@ s390_const_operand_ok (tree arg, int argnum, int op_flags, tree decl) >>> { >>> if (O_UIMM_P (op_flags)) >>> { >>> - unsigned HOST_WIDE_INT bitwidths[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32, 4 }; >>> - unsigned HOST_WIDE_INT bitmasks[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 12 }; >>> + unsigned HOST_WIDE_INT bitwidths[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32, 64, 4 }; >>> + unsigned HOST_WIDE_INT bitmasks[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12 }; >>> unsigned HOST_WIDE_INT bitwidth = bitwidths[op_flags - O_U1]; >>> unsigned HOST_WIDE_INT bitmask = bitmasks[op_flags - O_U1]; >>> >>> @@ -824,7 +824,7 @@ s390_const_operand_ok (tree arg, int argnum, int op_flags, tree decl) >>> gcc_assert(ARRAY_SIZE(bitmasks) == (O_M12 - O_U1 + 1)); >>> >>> if (!tree_fits_uhwi_p (arg) >>> - || tree_to_uhwi (arg) > (HOST_WIDE_INT_1U << bitwidth) - 1 >>> + || tree_to_uhwi (arg) > ((HOST_WIDE_INT_1U << (bitwidth - 1) << 1) - 1) >>> || (bitmask && tree_to_uhwi (arg) & ~bitmask)) >>> { >>> if (bitmask) >>