From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32485 invoked by alias); 29 Aug 2014 18:48:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 32468 invoked by uid 89); 29 Aug 2014 18:48:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 29 Aug 2014 18:48:08 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s7TIm5Di032417 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 29 Aug 2014 14:48:06 -0400 Received: from stumpy.slc.redhat.com (ovpn-113-40.phx2.redhat.com [10.3.113.40]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s7TIm4VK021716; Fri, 29 Aug 2014 14:48:05 -0400 Message-ID: <5400CAE4.4010902@redhat.com> Date: Fri, 29 Aug 2014 18:48:00 -0000 From: Jeff Law User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.7.0 MIME-Version: 1.0 To: Uros Bizjak , Ilya Enkovich CC: gcc@gnu.org, "gcc-patches@gcc.gnu.org" , Evgeny Stupachenko , Richard Biener , Vladimir Makarov Subject: Re: Enable EBX for x86 in 32bits PIC code References: <20140707114750.GB31640@tucnak.redhat.com> <20140822121151.GA60032@msticlxl57.ims.intel.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2014-08/txt/msg02655.txt.bz2 On 08/28/14 07:01, Uros Bizjak wrote: > On Fri, Aug 22, 2014 at 2:21 PM, Ilya Enkovich wrote: >> Hi, >> >> On Cauldron 2014 we had a couple of talks about relaxation of ebx usage in 32bit PIC mode. It was decided that the best approach would be to not fix ebx register, use speudo register for GOT base address and let allocator do the rest. This should be similar to how clang and icc work with GOT base address. I've been working for some time on such patch and now want to share my results. > > +#define PIC_OFFSET_TABLE_REGNUM > \ > + ((TARGET_64BIT && (ix86_cmodel == CM_SMALL_PIC \ > + || TARGET_PECOFF)) > \ > + || !flag_pic ? INVALID_REGNUM \ > + : X86_TUNE_RELAX_PIC_REG ? (pic_offset_table_rtx ? INVALID_REGNUM \ > + : REAL_PIC_OFFSET_TABLE_REGNUM) \ > + : reload_completed ? REGNO (pic_offset_table_rtx) \ > : REAL_PIC_OFFSET_TABLE_REGNUM) > > I'd like to avoid X86_TUNE_RELAX_PIC_REG and always treat EBX as an > allocatable register. This way, we can avoid all mess with implicit > xchgs in atomic_compare_and_swap_doubleword. Also, having > allocatable EBX would allow us to introduce __builtin_cpuid builtin > and cleanup cpiud.h. I think for the initial WIP patch it was fine. However I think we all agree that we want EBX as an allocatable register without any special conditions. So I'd recommend pulling this out of the WIP patches as well. Jeff