From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16733 invoked by alias); 18 Sep 2014 11:45:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 16714 invoked by uid 89); 18 Sep 2014 11:45:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 18 Sep 2014 11:45:38 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 18 Sep 2014 12:45:35 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Sep 2014 12:45:34 +0100 Message-ID: <541AC5DE.2020702@arm.com> Date: Thu, 18 Sep 2014 11:45:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 1/14][AArch64] Temporarily remove aarch64_gimple_fold_builtin code for reduction operations References: <541AC4D2.9040901@arm.com> In-Reply-To: <541AC4D2.9040901@arm.com> X-MC-Unique: 114091812453501701 Content-Type: multipart/mixed; boundary="------------020904010101000206000602" X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg01457.txt.bz2 This is a multi-part message in MIME format. --------------020904010101000206000602 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 988 The gimple folding ties the AArch64 backend to the tree representation of t= he=20 midend via the neon intrinsics. This code enables constant folding of Neon= =20 intrinsics reduction ops, so improves performance, but is not necessary for= =20 correctness. By temporarily removing it (here), we can then change the mide= nd=20 representation independently of the AArch64 backend + intrinsics. However, I'm leaving the code in place, as a later patch will bring it all = back=20 in a very similar form (but enabled for bigendian). Bootstrapped on aarch64-none-linux; tested aarch64.exp on aarch64-none-elf = and=20 aarch64_be-none-elf. (The removed code was already disabled for bigendian; = and=20 this is solely a __builtin-folding mechanism, i.e. used only for Neon/ACLE= =20 intrinsics.) gcc/ChangeLog: * config/aarch64/aarch64.c (TARGET_GIMPLE_FOLD_BUILTIN): Comment out. * config/aarch64/aarch64-builtins.c (aarch64_gimple_fold_builtin): Remove using preprocessor directives.= --------------020904010101000206000602 Content-Type: text/x-patch; name=1_aarch64_disable_.gimple_fold.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="1_aarch64_disable_.gimple_fold.patch" Content-length: 1536 diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aar= ch64-builtins.c index 5217f4a5f39224dbf8029542ad33790ef2c191be..15eb7c686d95b1d66cbd514500e= c29ba074eaa3f 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1333,6 +1333,9 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBU= TE_UNUSED, tree *args, return NULL_TREE; } =20 +/* Handling of reduction operations temporarily removed so as to decouple + changes to tree codes from AArch64 NEON Intrinsics. */ +#if 0 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *gsi) { @@ -1404,6 +1407,7 @@ aarch64_gimple_fold_builtin (gimple_stmt_iterator *gs= i) =20 return changed; } +#endif =20 void aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e7946fc0b70ced70a4e98caa0a33121f29242aad..9197ec038b7d40a601c886b8461= 13c50a29cf5e2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -9925,8 +9925,8 @@ aarch64_expand_movmem (rtx *operands) #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required =20 -#undef TARGET_GIMPLE_FOLD_BUILTIN -#define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin +//#undef TARGET_GIMPLE_FOLD_BUILTIN +//#define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin =20 #undef TARGET_GIMPLIFY_VA_ARG_EXPR #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr= --------------020904010101000206000602--