From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 551 invoked by alias); 9 Oct 2014 15:02:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 538 invoked by uid 89); 9 Oct 2014 15:02:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 09 Oct 2014 15:02:50 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 09 Oct 2014 16:02:46 +0100 Received: from [10.1.203.42] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 9 Oct 2014 16:02:45 +0100 Message-ID: <5436A3A8.9000803@arm.com> Date: Thu, 09 Oct 2014 15:07:00 -0000 From: Tejas Belagod User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: "charles.baylis@linaro.org" , Richard Earnshaw , "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Kyrylo Tkachov Subject: Re: [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* intrinsics References: <1412789236-26461-1-git-send-email-charles.baylis@linaro.org> <1412789236-26461-2-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1412789236-26461-2-git-send-email-charles.baylis@linaro.org> X-MC-Unique: 114100916024606101 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2014-10/txt/msg00820.txt.bz2 > > +(define_insn "vec_load_lanesoi_lane" Best to prepend "aarch64_" the pattern name, IMHO, else it looks like a=20 standard pattern name(eg. vec_load_lanes) at first glance. Otherwise, LGTM(but I can't approve it). Thanks for this patch. Thanks, Tejas. > + [(set (match_operand:OI 0 "register_operand" "=3Dw") > + (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand"= "Utv") > + (match_operand:OI 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i") > + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] > + UNSPEC_LD2_LANE))] > + "TARGET_SIMD" > + "ld2\\t{%S0. - %T0.}[%3], %1" > + [(set_attr "type" "neon_load2_one_lane")] > +) > + > (define_insn "vec_store_lanesoi" > [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=3DUtv") > (unspec:OI [(match_operand:OI 1 "register_operand" "w") > @@ -4022,6 +4034,18 @@ > [(set_attr "type" "neon_load3_3reg")] > ) > > +(define_insn "vec_load_lanesci_lane" > + [(set (match_operand:CI 0 "register_operand" "=3Dw") > + (unspec:CI [(match_operand: 1 "aarch64_simd_struct_operan= d" "Utv") > + (match_operand:CI 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i") > + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > + UNSPEC_LD3_LANE))] > + "TARGET_SIMD" > + "ld3\\t{%S0. - %U0.}[%3], %1" > + [(set_attr "type" "neon_load3_one_lane")] > +) > + > (define_insn "vec_store_lanesci" > [(set (match_operand:CI 0 "aarch64_simd_struct_operand" "=3DUtv") > (unspec:CI [(match_operand:CI 1 "register_operand" "w") > @@ -4053,6 +4077,18 @@ > [(set_attr "type" "neon_load4_4reg")] > ) > > +(define_insn "vec_load_lanesxi_lane" > + [(set (match_operand:XI 0 "register_operand" "=3Dw") > + (unspec:XI [(match_operand: 1 "aarch64_simd_struct_operand= " "Utv") > + (match_operand:XI 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i") > + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > + UNSPEC_LD4_LANE))] > + "TARGET_SIMD" > + "ld4\\t{%S0. - %V0.}[%3], %1" > + [(set_attr "type" "neon_load4_one_lane")] > +) > + > (define_insn "vec_store_lanesxi" > [(set (match_operand:XI 0 "aarch64_simd_struct_operand" "=3DUtv") > (unspec:XI [(match_operand:XI 1 "register_operand" "w") > @@ -4366,6 +4402,65 @@ > DONE; > }) > > +(define_expand "aarch64_ld2_lane" > + [(match_operand:OI 0 "register_operand" "=3Dw") > + (match_operand:DI 1 "register_operand" "w") > + (match_operand:OI 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i") > + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > + "TARGET_SIMD" > +{ > + enum machine_mode mode =3D mode; > + rtx mem =3D gen_rtx_MEM (mode, operands[1]); > + > + aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode= )); > + emit_insn (gen_vec_load_lanesoi_lane (operands[0], > + mem, > + operands[2], > + operands[3])); > + DONE; > +}) > + > +(define_expand "aarch64_ld3_lane" > + [(match_operand:CI 0 "register_operand" "=3Dw") > + (match_operand:DI 1 "register_operand" "w") > + (match_operand:CI 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i") > + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > + "TARGET_SIMD" > +{ > + enum machine_mode mode =3D mode; > + rtx mem =3D gen_rtx_MEM (mode, operands[1]); > + > + aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode= )); > + emit_insn (gen_vec_load_lanesci_lane (operands[0], > + mem, > + operands[2], > + operands[3])); > + DONE; > +}) > + > +(define_expand "aarch64_ld4_lane" > + [(match_operand:XI 0 "register_operand" "=3Dw") > + (match_operand:DI 1 "register_operand" "w") > + (match_operand:XI 2 "register_operand" "0") > + (match_operand:SI 3 "immediate_operand" "i") > + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > + "TARGET_SIMD" > +{ > + enum machine_mode mode =3D mode; > + rtx mem =3D gen_rtx_MEM (mode, operands[1]); > + > + aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode= )); > + emit_insn (gen_vec_load_lanesxi_lane (operands[0], > + mem, > + operands[2], > + operands[3])); > + DONE; > +}) > + > + > + > ;; Expanders for builtins to extract vector registers from large > ;; opaque integer modes. > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 74b554e..6b5f51f 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -92,6 +92,9 @@ > UNSPEC_LD2 > UNSPEC_LD3 > UNSPEC_LD4 > + UNSPEC_LD2_LANE > + UNSPEC_LD3_LANE > + UNSPEC_LD4_LANE > UNSPEC_MB > UNSPEC_NOP > UNSPEC_PRLG_STK >