From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28514 invoked by alias); 24 Oct 2014 11:57:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 28501 invoked by uid 89); 24 Oct 2014 11:57:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 24 Oct 2014 11:57:25 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 24 Oct 2014 12:57:21 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 24 Oct 2014 12:57:21 +0100 Message-ID: <544A3EA0.7000204@arm.com> Date: Fri, 24 Oct 2014 11:58:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 7/11][ARM] Migrate to new reduc_plus_scal_optab In-Reply-To: <544A3E0B.2000803@arm.com> X-MC-Unique: 114102412572102201 Content-Type: multipart/mixed; boundary="------------030200070803040607040103" X-IsSubscribed: yes X-SW-Source: 2014-10/txt/msg02537.txt.bz2 This is a multi-part message in MIME format. --------------030200070803040607040103 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 358 This migrates ARM from reduc_splus_optab and reduc_uplus optab to a single= =20 reduc_plus_optab. Tested, in combination with next patch: bootstrap on arm-none-linux-gnueabihf cross-tested check-gcc on arm-none-eabi. gcc/ChangeLog: config/arm/neon.md (reduc_plus_*): Rename to... (reduc_plus_scal_*): ...this; reduce to temp and extract scalar result.= --------------030200070803040607040103 Content-Type: text/x-patch; name=7_arm_reduc_plus.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="7_arm_reduc_plus.patch" Content-length: 2972 commit 22e60bd46f2a591f5357a543d76b19ed89f401ed Author: Alan Lawrence Date: Thu Aug 28 16:12:24 2014 +0100 ARM reduc_plus_scal, V_elem not V_ext, rm old reduc_[us]plus, emit the = extract! diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 41cf913..d13fe5d 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1349,33 +1349,47 @@ =20 ;; Reduction operations =20 -(define_expand "reduc_splus_" - [(match_operand:VD 0 "s_register_operand" "") +(define_expand "reduc_plus_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VD 1 "s_register_operand" "")] "TARGET_NEON && (! || flag_unsafe_math_optimizations)" { - neon_pairwise_reduce (operands[0], operands[1], mode, + rtx vec =3D gen_reg_rtx (mode); + neon_pairwise_reduce (vec, operands[1], mode, &gen_neon_vpadd_internal); + /* The same result is actually computed into every element. */ + emit_insn (gen_vec_extract (operands[0], vec, const0_rtx)); DONE; }) =20 -(define_expand "reduc_splus_" - [(match_operand:VQ 0 "s_register_operand" "") +(define_expand "reduc_plus_scal_" + [(match_operand: 0 "nonimmediate_operand" "") (match_operand:VQ 1 "s_register_operand" "")] "TARGET_NEON && (! || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { rtx step1 =3D gen_reg_rtx (mode); - rtx res_d =3D gen_reg_rtx (mode); =20 emit_insn (gen_quad_halves_plus (step1, operands[1])); - emit_insn (gen_reduc_splus_ (res_d, step1)); - emit_insn (gen_move_lo_quad_ (operands[0], res_d)); + emit_insn (gen_reduc_plus_scal_ (operands[0], step1)); + + DONE; +}) + +(define_expand "reduc_plus_scal_v2di" + [(match_operand:DI 0 "nonimmediate_operand" "=3Dw") + (match_operand:V2DI 1 "s_register_operand" "")] + "TARGET_NEON && !BYTES_BIG_ENDIAN" +{ + rtx vec =3D gen_reg_rtx (V2DImode); + + emit_insn (gen_arm_reduc_plus_internal_v2di (vec, operands[1])); + emit_insn (gen_vec_extractv2di (operands[0], vec, const0_rtx)); =20 DONE; }) =20 -(define_insn "reduc_splus_v2di" +(define_insn "arm_reduc_plus_internal_v2di" [(set (match_operand:V2DI 0 "s_register_operand" "=3Dw") (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")] UNSPEC_VPADD))] @@ -1384,17 +1398,6 @@ [(set_attr "type" "neon_add_q")] ) =20 -;; NEON does not distinguish between signed and unsigned addition except on -;; widening operations. -(define_expand "reduc_uplus_" - [(match_operand:VDQI 0 "s_register_operand" "") - (match_operand:VDQI 1 "s_register_operand" "")] - "TARGET_NEON && ( || !BYTES_BIG_ENDIAN)" -{ - emit_insn (gen_reduc_splus_ (operands[0], operands[1])); - DONE; -}) - (define_expand "reduc_smin_" [(match_operand:VD 0 "s_register_operand" "") (match_operand:VD 1 "s_register_operand" "")]= --------------030200070803040607040103--