From: Alan Lawrence <alan.lawrence@arm.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: [PATCH 8/11][ARM] Migrate to new reduc_[us](min|max)_scal_optab
Date: Fri, 24 Oct 2014 12:05:00 -0000 [thread overview]
Message-ID: <544A3F95.3050305@arm.com> (raw)
In-Reply-To: <544A3E0B.2000803@arm.com>
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Similarly to last patch.
Tested, in combination with previous patch:
bootstrap on arm-none-linux-gnueabihf
cross-tested check-gcc on arm-none-eabi.
gcc/ChangeLog:
config/arm/neon.md (reduc_smin_<mode> *2): Rename to...
(reduc_smin_scal_<mode> *2): ...this; extract scalar result.
(reduc_smax_<mode> *2): Rename to...
(reduc_smax_scal_<mode> *2): ...this; extract scalar result.
(reduc_umin_<mode> *2): Rename to...
(reduc_umin_scal_<mode> *2): ...this; extract scalar result.
(reduc_umax_<mode> *2): Rename to...
(reduc_umax_scal_<mode> *2): ...this; extract scalar result.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 8_arm_reduc_minmax.patch --]
[-- Type: text/x-patch; name=8_arm_reduc_minmax.patch, Size: 5679 bytes --]
commit 537c31561933f8054a2289198f35b19cf5c4196e
Author: Alan Lawrence <alan.lawrence@arm.com>
Date: Thu Aug 28 16:49:24 2014 +0100
ARM reduc_[us](min|max)_scal, V_elem not V_ext, rm old non-_scal version.
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index d13fe5d..19e1ba0 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1398,104 +1398,109 @@
[(set_attr "type" "neon_add_q")]
)
-(define_expand "reduc_smin_<mode>"
- [(match_operand:VD 0 "s_register_operand" "")
+(define_expand "reduc_smin_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VD 1 "s_register_operand" "")]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
- neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ rtx vec = gen_reg_rtx (<MODE>mode);
+
+ neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpsmin<mode>);
+ /* The result is computed into every element of the vector. */
+ emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
DONE;
})
-(define_expand "reduc_smin_<mode>"
- [(match_operand:VQ 0 "s_register_operand" "")
+(define_expand "reduc_smin_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VQ 1 "s_register_operand" "")]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)
&& !BYTES_BIG_ENDIAN"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
- rtx res_d = gen_reg_rtx (<V_HALF>mode);
emit_insn (gen_quad_halves_smin<mode> (step1, operands[1]));
- emit_insn (gen_reduc_smin_<V_half> (res_d, step1));
- emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
+ emit_insn (gen_reduc_smin_scal_<V_half> (operands[0], step1));
DONE;
})
-(define_expand "reduc_smax_<mode>"
- [(match_operand:VD 0 "s_register_operand" "")
+(define_expand "reduc_smax_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VD 1 "s_register_operand" "")]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
- neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ rtx vec = gen_reg_rtx (<MODE>mode);
+ neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpsmax<mode>);
+ /* The result is computed into every element of the vector. */
+ emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
DONE;
})
-(define_expand "reduc_smax_<mode>"
- [(match_operand:VQ 0 "s_register_operand" "")
+(define_expand "reduc_smax_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VQ 1 "s_register_operand" "")]
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)
&& !BYTES_BIG_ENDIAN"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
- rtx res_d = gen_reg_rtx (<V_HALF>mode);
emit_insn (gen_quad_halves_smax<mode> (step1, operands[1]));
- emit_insn (gen_reduc_smax_<V_half> (res_d, step1));
- emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
+ emit_insn (gen_reduc_smax_scal_<V_half> (operands[0], step1));
DONE;
})
-(define_expand "reduc_umin_<mode>"
- [(match_operand:VDI 0 "s_register_operand" "")
+(define_expand "reduc_umin_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VDI 1 "s_register_operand" "")]
"TARGET_NEON"
{
- neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ rtx vec = gen_reg_rtx (<MODE>mode);
+ neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpumin<mode>);
+ /* The result is computed into every element of the vector. */
+ emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
DONE;
})
-(define_expand "reduc_umin_<mode>"
- [(match_operand:VQI 0 "s_register_operand" "")
+(define_expand "reduc_umin_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VQI 1 "s_register_operand" "")]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
- rtx res_d = gen_reg_rtx (<V_HALF>mode);
emit_insn (gen_quad_halves_umin<mode> (step1, operands[1]));
- emit_insn (gen_reduc_umin_<V_half> (res_d, step1));
- emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
+ emit_insn (gen_reduc_umin_scal_<V_half> (operands[0], step1));
DONE;
})
-(define_expand "reduc_umax_<mode>"
- [(match_operand:VDI 0 "s_register_operand" "")
+(define_expand "reduc_umax_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VDI 1 "s_register_operand" "")]
"TARGET_NEON"
{
- neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
+ rtx vec = gen_reg_rtx (<MODE>mode);
+ neon_pairwise_reduce (vec, operands[1], <MODE>mode,
&gen_neon_vpumax<mode>);
+ /* The result is computed into every element of the vector. */
+ emit_insn (gen_vec_extract<mode> (operands[0], vec, const0_rtx));
DONE;
})
-(define_expand "reduc_umax_<mode>"
- [(match_operand:VQI 0 "s_register_operand" "")
+(define_expand "reduc_umax_scal_<mode>"
+ [(match_operand:<V_elem> 0 "nonimmediate_operand" "")
(match_operand:VQI 1 "s_register_operand" "")]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
- rtx res_d = gen_reg_rtx (<V_HALF>mode);
emit_insn (gen_quad_halves_umax<mode> (step1, operands[1]));
- emit_insn (gen_reduc_umax_<V_half> (res_d, step1));
- emit_insn (gen_move_lo_quad_<mode> (operands[0], res_d));
+ emit_insn (gen_reduc_umax_scal_<V_half> (operands[0], step1));
DONE;
})
next prev parent reply other threads:[~2014-10-24 12:01 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-24 11:57 [PATCH v2 0-6/11] Fix PR/61114, make direct vector reductions endianness-neutral Alan Lawrence
2014-10-24 11:58 ` [PATCH 7/11][ARM] Migrate to new reduc_plus_scal_optab Alan Lawrence
2014-11-03 17:32 ` Ramana Radhakrishnan
2014-10-24 12:01 ` [PATCH v2 0-6/11] Fix PR/61114, make direct vector reductions endianness-neutral Richard Biener
2014-10-24 12:05 ` Alan Lawrence [this message]
2014-11-04 11:08 ` [PATCH 8/11][ARM] Migrate to new reduc_[us](min|max)_scal_optab Ramana Radhakrishnan
2014-10-24 12:06 ` [PATCH 9/11][i386] Migrate reduction optabs to reduc_..._scal Alan Lawrence
2014-10-24 12:07 ` [PATCH 10/11][RS6000] " Alan Lawrence
2014-10-24 12:14 ` Alan Lawrence
2014-10-25 0:08 ` David Edelsohn
2014-11-03 17:51 ` Bill Schmidt
2014-11-06 16:44 ` Alan Lawrence
2014-11-06 18:57 ` Bill Schmidt
2014-11-07 10:09 ` Alan Lawrence
2014-11-10 22:39 ` Michael Meissner
2014-11-11 7:10 ` Segher Boessenkool
2014-11-12 1:54 ` Michael Meissner
2014-11-12 9:26 ` Segher Boessenkool
2014-11-12 19:20 ` Michael Meissner
2014-11-12 12:32 ` Alan Lawrence
2014-11-12 18:53 ` Alan Lawrence
2014-12-11 15:59 ` Ping: " Alan Lawrence
2014-12-11 18:37 ` Alan Lawrence
2014-10-24 12:12 ` [Protopatch 11/11][IA64] Migrate to reduc_(plus|min|max)_scal_v2df optab Alan Lawrence
2014-10-24 12:50 ` Alan Lawrence
2014-10-24 15:19 ` [PATCH v2 0-6/11] Fix PR/61114, make direct vector reductions endianness-neutral Matthew Fortune
2014-10-27 11:48 ` Richard Biener
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