From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16755 invoked by alias); 24 Oct 2014 12:14:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 16743 invoked by uid 89); 24 Oct 2014 12:14:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 24 Oct 2014 12:14:06 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 24 Oct 2014 13:14:04 +0100 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 24 Oct 2014 13:14:02 +0100 Message-ID: <544A4289.2060407@arm.com> Date: Fri, 24 Oct 2014 12:50:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Steve Ellcey Subject: Re: [Protopatch 11/11][IA64] Migrate to reduc_(plus|min|max)_scal_v2df optab In-Reply-To: <544A40F0.2090907@arm.com> X-MC-Unique: 114102413140401001 Content-Type: multipart/mixed; boundary="------------060605020409050300060609" X-IsSubscribed: yes X-SW-Source: 2014-10/txt/msg02546.txt.bz2 This is a multi-part message in MIME format. --------------060605020409050300060609 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 18 Ooops, attached.= --------------060605020409050300060609 Content-Type: text/x-patch; name=11_ia64.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="11_ia64.patch" Content-length: 2480 commit 56296417b9f6795e541b1101dce6e6ac1789de9a Author: Alan Lawrence Date: Wed Oct 8 15:58:27 2014 +0100 IA64 (?!) diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index e3ce292..45f4156 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -1217,45 +1217,54 @@ "fpmin %0 =3D %1, %2" [(set_attr "itanium_class" "fmisc")]) =20 -(define_expand "reduc_splus_v2sf" - [(match_operand:V2SF 0 "fr_register_operand" "") +(define_expand "reduc_plus_scal_v2sf" + [(match_operand:SF 0 "fr_register_operand" "") (match_operand:V2SF 1 "fr_register_operand" "")] "" { rtx tmp =3D gen_reg_rtx (V2SFmode); + rtx tmp2 =3D gen_reg_rtx (V2SFmode); + if (TARGET_BIG_ENDIAN) emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); else emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); - emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp)); + emit_insn (gen_addv2sf3 (tmp2, operands[1], tmp)); + emit_insn (gen_vec_extractv2sf (operands[0], tmp2, GEN_INT (0))); DONE; }) =20 -(define_expand "reduc_smax_v2sf" - [(match_operand:V2SF 0 "fr_register_operand" "") +(define_expand "reduc_smax_scal_v2sf" + [(match_operand:SF 0 "fr_register_operand" "") (match_operand:V2SF 1 "fr_register_operand" "")] "" { rtx tmp =3D gen_reg_rtx (V2SFmode); + rtx tmp2 =3D gen_reg_rtx (V2SFmode); + if (TARGET_BIG_ENDIAN) emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); else emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); - emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp)); + emit_insn (gen_smaxv2sf3 (tmp2, operands[1], tmp)); + emit_insn (gen_vec_extractv2sf (operands[0], tmp2, GEN_INT (0))); DONE; }) =20 -(define_expand "reduc_smin_v2sf" - [(match_operand:V2SF 0 "fr_register_operand" "") +(define_expand "reduc_smin_scal_v2sf" + [(match_operand:SF 0 "fr_register_operand" "") (match_operand:V2SF 1 "fr_register_operand" "")] "" { rtx tmp =3D gen_reg_rtx (V2SFmode); + rtx tmp2 =3D gen_reg_rtx (V2SFmode); + if (TARGET_BIG_ENDIAN) emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); else emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); - emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp)); + emit_insn (gen_sminv2sf3 (tmp2, operands[1], tmp)); + emit_insn (gen_vec_extractv2sf (operands[0], tmp2, GEN_INT (0))); DONE; }) =20= --------------060605020409050300060609--