* [patch 1/2][ARM]: New CPU support for Marvell Whitney
@ 2014-12-18 10:21 Xingxing Pan
2014-12-19 10:37 ` Kyrill Tkachov
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Xingxing Pan @ 2014-12-18 10:21 UTC (permalink / raw)
To: gcc-patches; +Cc: ramana.radhakrishnan, richard.earnshaw, xyqi, lgao1, xxingpan
Hi,
This patch contains Marvell Whitney core's pipeline description.
Test on arm-linux-gnueabi and no new regression are found.
Is it OK for trunk?
Regards,
Xingxing
2014-12-18 Xingxing Pan <xxingpan@marvell.com>
* config/arm/arm-cores.def: Add new core marvell-whitney.
* config/arm/arm-protos.h:
(marvell_whitney_vector_element_size_is_byte): Declare.
(marvell_whitney_non_shift_with_shift_operand): Ditto.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm.c (arm_marvell_whitney_tune): New structure.
(arm_issue_rate): Add marvell_whitney.
(marvell_whitney_vector_element_size_is_byte): New function.
(marvell_whitney_non_shift_with_shift_operand): Ditto.
* config/arm/arm.md: Include marvell-whitney.md.
(generic_sched): Add marvell_whitney.
(generic_vfp): Ditto.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
* config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
* config/arm/marvell-whitney.md: New file.
* doc/invoke.texi: Document marvell-whitney.
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 423ee9e..b0ffbe1 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7,
cortexm7, 7EM,
FL_LDSCHED, cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM,
FL_LDSCHED, v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M,
FL_LDSCHED, v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4,
7A, FL_LDSCHED, 9e)
+ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney,
7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
/* V7 big.LITTLE implementations */
ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A,
FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 20cfa9f..e86db1e 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -231,6 +231,9 @@ extern void arm_order_regs_for_local_alloc (void);
extern int arm_max_conditional_execute ();
+extern bool marvell_whitney_vector_element_size_is_byte (rtx insn);
+extern bool marvell_whitney_non_shift_with_shift_operand (rtx insn);
+
/* Vectorizer cost model implementation. */
struct cpu_vec_costs {
const int scalar_stmt_cost; /* Cost of any scalar operation,
excluding
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 9b1886e..3371ce3 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -298,6 +298,9 @@ EnumValue
Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
EnumValue
+Enum(processor_type) String(marvell-whitney) Value(marvell_whitney)
+
+EnumValue
Enum(processor_type) String(cortex-a15.cortex-a7)
Value(cortexa15cortexa7)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d300c51..c73c33c 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -28,9 +28,10 @@
cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
genericv7a,cortexa5,cortexa7,
cortexa8,cortexa9,cortexa12,
- cortexa15,cortexa17,cortexr4,cortexr4f,
- cortexr5,cortexr7,cortexm7,
- cortexm4,cortexm3,marvell_pj4,
- cortexa15cortexa7,cortexa17cortexa7,cortexa53,
- cortexa57,cortexa57cortexa53"
+ cortexa15,cortexa17,cortexr4,
+ cortexr4f,cortexr5,cortexr7,
+ cortexm7,cortexm4,cortexm3,
+ marvell_pj4,marvell_whitney,cortexa15cortexa7,
+ cortexa17cortexa7,cortexa53,cortexa57,
+ cortexa57cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0ec526b..183da4c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1914,6 +1914,25 @@ const struct tune_params arm_cortex_a9_tune =
8 /* Maximum insns to
inline memset. */
};
+const struct tune_params arm_marvell_whitney_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa9_extra_costs,
+ cortex_a9_sched_adjust_cost,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_BENEFICIAL(4,32,32),
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non
short circuit. */
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ false, /* Prefer Neon for
64-bits bitops. */
+ false, false, /* Prefer 32-bit
encodings. */
+ false, /* Prefer Neon for
stringops. */
+ 8 /* Maximum insns to
inline memset. */
+};
+
const struct tune_params arm_cortex_a12_tune =
{
arm_9e_rtx_costs,
@@ -11608,6 +11627,49 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx
link, rtx_insn *dep, int * cost)
return true;
}
+/* Return true if vector element size is byte. */
+bool
+marvell_whitney_vector_element_size_is_byte (rtx insn)
+{
+ if (GET_CODE (PATTERN (insn)) == SET)
+ {
+ if ((GET_MODE (SET_DEST (PATTERN (insn))) == V8QImode) ||
+ (GET_MODE (SET_DEST (PATTERN (insn))) == V16QImode))
+ return true;
+ }
+
+ return false;
+}
+
+/* Return true if INSN has shift operation but is not a shift insn. */
+bool
+marvell_whitney_non_shift_with_shift_operand (rtx insn)
+{
+ rtx pat = PATTERN (insn);
+
+ if (GET_CODE (pat) != SET)
+ return false;
+
+ /* Is not a shift insn. */
+ rtx rvalue = SET_SRC (pat);
+ RTX_CODE code = GET_CODE (rvalue);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return false;
+
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
+ {
+ /* Has shift operation. */
+ RTX_CODE code = GET_CODE (*iter);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return true;
+ }
+
+ return false;
+}
+
/* Implement TARGET_REGISTER_MOVE_COST.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
@@ -27031,6 +27093,7 @@ arm_issue_rate (void)
{
case cortexa15:
case cortexa57:
+ case marvell_whitney:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 822760b..8f02743 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -386,7 +386,8 @@
arm926ejs,arm1020e,arm1026ejs,arm1136js,\
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa17,\
- cortexa53,cortexm4,cortexm7,marvell_pj4")
+ cortexa53,cortexm4,cortexm7,marvell_pj4,\
+ marvell_whitney")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -396,7 +397,7 @@
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
cortexa8,cortexa9,cortexa53,cortexm4,\
- cortexm7,marvell_pj4")
+ cortexm7,marvell_pj4,marvell_whitney")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -426,6 +427,7 @@
(include "cortex-m4-fpu.md")
(include "vfp11.md")
(include "marvell-pj4.md")
+(include "marvell-whitney.md")
;;---------------------------------------------------------------------------
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index aa93aa4..07fab0f 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -68,6 +68,7 @@
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
@@ -96,6 +97,7 @@
|mcpu=cortex-m0.small-multiply \
|mcpu=cortex-m0plus.small-multiply \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=generic-armv7-a \
|march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \
diff --git a/gcc/config/arm/marvell-whitney.md
b/gcc/config/arm/marvell-whitney.md
new file mode 100644
index 0000000..57391a7
--- /dev/null
+++ b/gcc/config/arm/marvell-whitney.md
@@ -0,0 +1,683 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+;;
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_attr "whitney_type"
+ "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
+
wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
+
wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
+
wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
+ wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
+ unknown"
+ (cond [
+ (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
+ adc_imm,bfm,branch,call,clz,extend,logic_imm,\
+
logic_reg,logics_imm,logics_reg,logics_shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
+ shift_reg,rev")
+ (const_string "wTP1")
+ (eq_attr "type" "alu_shift_imm,alu_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_non_shift_with_shift_operand
(insn)")
+ (const_string "wTP2")
+ (const_string "wTP1"))
+ (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
+
mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
+ logic_shift_reg,multiple")
+ (const_string "wTP2")
+ (eq_attr "type" "mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
+ smulxy,umlal,umull")
+ (const_string "wTP3")
+ (eq_attr "type" "sdiv,udiv")
+ (const_string "wTP4")
+ (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
+ (const_string "wTP5")
+ (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
+ neon_load2_all_lanes,neon_load2_all_lanes_q,\
+ neon_load2_2reg_q")
+ (const_string "wTP7")
+ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
+ neon_load3_3reg,neon_load3_3reg_q,\
+ neon_load3_all_lanes,neon_load3_all_lanes_q")
+ (const_string "wTP8")
+ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
+ neon_load4_4reg,neon_load4_4reg_q,\
+ neon_load4_all_lanes,neon_load4_all_lanes_q")
+ (const_string "wTP9")
+ (eq_attr "type" "load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
+
neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
+ (const_string "wTP10")
+ (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
+ neon_load1_2reg,neon_load1_2reg_q,")
+ (const_string "wTP11")
+ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
+ neon_load1_one_lane,neon_load1_one_lane_q,")
+ (const_string "wTP6")
+ (eq_attr "type" "f_stored,f_stores,store1,store2")
+ (const_string "wTP12")
+ (eq_attr "type" "f_stored,neon_store1_3reg,neon_store1_3reg_q,\
+ neon_store1_4reg,neon_store1_4reg_q,\
+ neon_store2_4reg,neon_store2_4reg_q,\
+ neon_store3_3reg,neon_store3_3reg_q,\
+ neon_store3_one_lane,neon_store3_one_lane_q,\
+ neon_store4_4reg,neon_store4_4reg_q,\
+ neon_store4_one_lane,neon_store4_one_lane_q,\
+ store3,store4")
+ (const_string "wTP13")
+ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
+ neon_store1_2reg,neon_store1_2reg_q,\
+ neon_store1_one_lane,neon_store1_one_lane_q,\
+ neon_store2_2reg,neon_store2_2reg_q,\
+ neon_store2_one_lane,neon_store2_one_lane_q")
+ (const_string "wTP14")
+ (eq_attr "type" "fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
+ (const_string "wTP15")
+ (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
+ (const_string "wTP16")
+ (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
+ neon_fp_round_d")
+ (const_string "wTP17")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
+ neon_fp_round_d_q")
+ (const_string "wTP18")
+ (eq_attr "type" "fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
+ neon_fp_recps_s,neon_fp_rsqrts_s")
+ (const_string "wTP19")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
+ neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
+ (const_string "wTP20")
+ (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
+ neon_fp_abs_s,neon_fp_neg_s")
+ (const_string "wTP21")
+ (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
+ (const_string "wTP22")
+ (eq_attr "type" "fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
+ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
+ (const_string "wTP23")
+ (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
+
neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
+ (const_string "wTP24")
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
+
neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
+ (const_string "wTP25")
+ (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
+ neon_int_to_fp_s_q,neon_int_to_fp_d_q")
+ (const_string "wTP26")
+ (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
+ neon_fp_reduc_add_s")
+ (const_string "wTP27")
+ (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
+ neon_fp_reduc_add_s_q")
+ (const_string "wTP28")
+ (eq_attr "type" "fdivs")
+ (const_string "wTP29")
+ (eq_attr "type" "fsqrts")
+ (const_string "wTP30")
+ (eq_attr "type" "fdivd")
+ (const_string "wTP31")
+ (eq_attr "type" "fsqrtd")
+ (const_string "wTP32")
+ (eq_attr "type" "neon_reduc_add_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP33")
+ (const_string "wTP35"))
+ (eq_attr "type" "neon_reduc_add_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP34")
+ (const_string "wTP36"))
+ (eq_attr "type"
"neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
+ neon_reduc_add,neon_sub,neon_sub_halve")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP37")
+ (const_string "wTP39"))
+ (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
+ neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP38")
+ (const_string "wTP40"))
+ (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
+ neon_compare,neon_compare_zero,neon_sub_long,\
+ neon_sub_widen,neon_tst")
+ (const_string "wTP37")
+ (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
+ neon_compare_zero_q,neon_tst_q")
+ (const_string "wTP38")
+ (eq_attr "type"
"neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
+ (const_string "wTP40")
+ (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
+ neon_tbl4,neon_zip")
+ (const_string "wTP41")
+ (eq_attr "type" "neon_permute_q,neon_zip_q")
+ (const_string "wTP42")
+ (eq_attr "type" "neon_bsl,neon_logic")
+ (const_string "wTP43")
+ (eq_attr "type" "neon_arith_acc,neon_shift_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP43")
+ (const_string "wTP45"))
+ (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP44")
+ (const_string "wTP46"))
+ (eq_attr "type" "neon_logic_q")
+ (const_string "wTP44")
+ (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
+ neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
+ neon_move,neon_reduc_minmax,neon_rev")
+ (const_string "wTP47")
+ (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
+
neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
+
neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
+ neon_rev_q,neon_sat_shift_imm_narrow_q,\
+ neon_shift_imm_narrow_q")
+ (const_string "wTP48")
+ (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
+
neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
+ neon_shift_imm,neon_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP47")
+ (const_string "wTP49"))
+ (eq_attr "type" "neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
+ neon_sat_shift_imm_q,neon_shift_imm_q,\
+ neon_shift_reg_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte
(insn)")
+ (const_string "wTP48")
+ (const_string "wTP50"))
+ (eq_attr "type"
"neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
+ neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
+ (const_string "wTP51")
+ (eq_attr "type"
"neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
+ neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
+ neon_sat_mul_b_long,neon_sat_mul_h_long,\
+ neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
+
neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
+ neon_sat_mul_s_scalar_q")
+ (const_string "wTP52")
+ (eq_attr "type"
"neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
+ neon_mla_s_scalar")
+ (const_string "wTP53")
+ (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
+ neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
+
neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
+ neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
+ neon_sat_mla_b_long,neon_sat_mla_h_long,\
+ neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
+ neon_sat_mla_s_scalar_long")
+ (const_string "wTP54")
+ (eq_attr "type" "f_flag,f_mrc,f_mrrc")
+ (const_string "wTP57")
+ (eq_attr "type" "neon_to_gp,neon_to_gp_q")
+ (const_string "wTP55")
+ (eq_attr "type" "f_mcr,f_mcrr")
+ (const_string "wTP58")
+ (eq_attr "type" "neon_from_gp_q")
+ (const_string "wTP59")
+ (eq_attr "type" "neon_from_gp")
+ (const_string "wTP56")]
+ (const_string "unknown")))
+
+(define_attr "tune_marvell_whitney" "yes,no"
+ (const (if_then_else (eq_attr "tune" "marvell_whitney")
+ (const_string "yes")
+ (const_string "no"))))
+
+(define_automaton "whitney_pipe")
+
+(define_cpu_unit "wCU1" "whitney_pipe")
+(define_cpu_unit "wCU2" "whitney_pipe")
+(define_cpu_unit "wCU3" "whitney_pipe")
+(define_cpu_unit "wCU4" "whitney_pipe")
+(define_cpu_unit "wCU5" "whitney_pipe")
+(define_cpu_unit "wCU6" "whitney_pipe")
+(define_cpu_unit "wCU7" "whitney_pipe")
+(define_cpu_unit "wCU8" "whitney_pipe")
+(define_cpu_unit "wCU9" "whitney_pipe")
+(define_cpu_unit "wCU10" "whitney_pipe")
+(define_cpu_unit "wCU11" "whitney_pipe")
+(define_cpu_unit "wCU12" "whitney_pipe")
+(define_cpu_unit "wCU13" "whitney_pipe")
+
+(define_insn_reservation "wIR1" 1
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP1"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR2" 2
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP2"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR3" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP3"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU8"
+)
+
+(define_insn_reservation "wIR4" 17
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP4"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU7*8"
+)
+
+(define_insn_reservation "wIR5" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP5"))
+ "(wCU1|wCU2|(wCU3+wCU4)), (wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR6" 0
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP12"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU6"
+)
+
+(define_insn_reservation "wIR7" 8
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP6"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR8" 8
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP7"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR9" 9
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP8"))
+ "(wCU1+wCU3+wCU4+wCU2)*3,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR10" 9
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP9"))
+ "(wCU1+wCU3+wCU4+wCU2)*4,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR11" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP10"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR12" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP11"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR13" 0
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP13"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,wCU6"
+)
+
+(define_insn_reservation "wIR14" 0
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP14"))
+ "wCU1+wCU3+wCU4+wCU2,wCU6"
+)
+
+(define_insn_reservation "wIR15" 6
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP15"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR16" 6
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP16"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR17" 6
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP17"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR18" 6
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP18"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR19" 10
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP19"))
+ "(wCU1+wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR20" 10
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP20"))
+ "(wCU1+wCU2)*2, wCU9"
+)
+
+(define_insn_reservation "wIR21" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP21"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR22" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP22"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR23" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP23"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR24" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP24"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR25" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP25"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR26" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP26"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR27" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP27"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR28" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP28"))
+ "(wCU1+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR29" 16
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP29"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR30" 16
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP30"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR31" 26
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP31"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR32" 26
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP32"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR33" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP33"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR34" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP34"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR35" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP35"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR36" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP36"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR37" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP37"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR38" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP38"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR39" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP39"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR40" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP40"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR41" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP41"))
+ "(wCU1+wCU3+wCU4+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR42" 4
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP42"))
+ "(wCU1+wCU3+wCU4+wCU2)*2, wCU10*3"
+)
+
+(define_insn_reservation "wIR43" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP43"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR44" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP44"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR45" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP45"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR46" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP46"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR47" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP47"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR48" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP48"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR49" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP49"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR50" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP50"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR51" 5
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP51"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR52" 5
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP52"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR53" 5
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP53"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR54" 5
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP54"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR55" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP55"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR56" 2
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP56"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR57" 3
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP57"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR58" 2
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP58"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR59" 2
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "wTP59"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU11*2"
+)
+
+(define_insn_reservation "wIR60" 0
+ (and (eq_attr "tune_marvell_whitney" "yes")
+ (eq_attr "whitney_type" "unknown"))
+ "wCU13"
+)
+
+(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 5 "wIR22" "wIR41")
+(define_bypass 6 "wIR22" "wIR42")
+(define_bypass 6 "wIR23" "wIR41, wIR42")
+(define_bypass 6 "wIR24" "wIR41")
+(define_bypass 7 "wIR24" "wIR42")
+(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 7 "wIR26" "wIR41")
+(define_bypass 8 "wIR26" "wIR42")
+(define_bypass 6 "wIR27" "wIR41, wIR42")
+(define_bypass 6 "wIR28" "wIR41, wIR42")
+(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 6 "wIR33" "wIR41, wIR42")
+(define_bypass 6 "wIR34" "wIR41")
+(define_bypass 7 "wIR34" "wIR42")
+(define_bypass 6 "wIR35" "wIR41, wIR42")
+(define_bypass 6 "wIR36" "wIR41")
+(define_bypass 7 "wIR36" "wIR42")
+(define_bypass 6 "wIR37" "wIR41, wIR42")
+(define_bypass 6 "wIR38" "wIR41")
+(define_bypass 7 "wIR38" "wIR42")
+(define_bypass 6 "wIR39" "wIR41, wIR42")
+(define_bypass 6 "wIR40" "wIR41")
+(define_bypass 7 "wIR40" "wIR42")
+(define_bypass 6 "wIR41" "wIR41, wIR42")
+(define_bypass 6 "wIR42" "wIR41")
+(define_bypass 7 "wIR42" "wIR42")
+(define_bypass 6 "wIR43" "wIR41, wIR42")
+(define_bypass 6 "wIR44" "wIR41")
+(define_bypass 7 "wIR44" "wIR42")
+(define_bypass 6 "wIR45" "wIR41, wIR42")
+(define_bypass 6 "wIR46" "wIR41")
+(define_bypass 7 "wIR46" "wIR42")
+(define_bypass 6 "wIR47" "wIR41, wIR42")
+(define_bypass 6 "wIR48" "wIR41")
+(define_bypass 7 "wIR48" "wIR42")
+(define_bypass 6 "wIR49" "wIR41, wIR42")
+(define_bypass 6 "wIR50" "wIR41")
+(define_bypass 7 "wIR50" "wIR42")
+(define_bypass 8 "wIR51" "wIR41, wIR42")
+(define_bypass 8 "wIR52" "wIR41")
+(define_bypass 9 "wIR52" "wIR42")
+(define_bypass 8 "wIR53" "wIR41, wIR42")
+(define_bypass 8 "wIR54" "wIR41")
+(define_bypass 9 "wIR54" "wIR42")
+(define_bypass 2 "wIR56" "wIR41, wIR42")
+(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 5 "wIR58" "wIR41, wIR42")
+(define_bypass 5 "wIR59" "wIR41")
+(define_bypass 6 "wIR59" "wIR42")
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index d82a123..8af9ad2 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -61,7 +61,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/thumb2.md \
$(srcdir)/config/arm/vec-common.md \
$(srcdir)/config/arm/vfp11.md \
- $(srcdir)/config/arm/vfp.md
+ $(srcdir)/config/arm/vfp.md \
+ $(srcdir)/config/arm/marvell-whitney.md
s-config s-conditions s-flags s-codes s-constants s-emit s-recog
s-preds \
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 15068da..c2522de 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12869,6 +12869,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
@samp{marvell-pj4},
+@samp{marvell-whitney},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2014-12-18 10:21 [patch 1/2][ARM]: New CPU support for Marvell Whitney Xingxing Pan
@ 2014-12-19 10:37 ` Kyrill Tkachov
2014-12-19 10:59 ` Kyrill Tkachov
2015-02-26 10:12 ` Ramana Radhakrishnan
2 siblings, 0 replies; 13+ messages in thread
From: Kyrill Tkachov @ 2014-12-19 10:37 UTC (permalink / raw)
To: Xingxing Pan, gcc-patches
Cc: Ramana Radhakrishnan, Richard Earnshaw, xyqi, lgao1
Hi Xingxing,
On 18/12/14 10:13, Xingxing Pan wrote:
> +
> +(define_attr "tune_marvell_whitney" "yes,no"
> + (const (if_then_else (eq_attr "tune" "marvell_whitney")
> + (const_string "yes")
> + (const_string "no"))))
Why do you need this? The canonical way we do this in the other .md
files is check
for the "tune" attribute directly.
> +
> +(define_automaton "whitney_pipe")
> +
> +(define_cpu_unit "wCU1" "whitney_pipe")
> +(define_cpu_unit "wCU2" "whitney_pipe")
> +(define_cpu_unit "wCU3" "whitney_pipe")
> +(define_cpu_unit "wCU4" "whitney_pipe")
> +(define_cpu_unit "wCU5" "whitney_pipe")
> +(define_cpu_unit "wCU6" "whitney_pipe")
> +(define_cpu_unit "wCU7" "whitney_pipe")
> +(define_cpu_unit "wCU8" "whitney_pipe")
> +(define_cpu_unit "wCU9" "whitney_pipe")
> +(define_cpu_unit "wCU10" "whitney_pipe")
> +(define_cpu_unit "wCU11" "whitney_pipe")
> +(define_cpu_unit "wCU12" "whitney_pipe")
> +(define_cpu_unit "wCU13" "whitney_pipe")
> +
> +(define_insn_reservation "wIR1" 1
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP1"))
> + "wCU1|wCU2|(wCU3+wCU4)"
> +)
Further to the comment above, this could be written as:
+(define_insn_reservation "wIR1" 1
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP1"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
Same with the other reservations in this file.
Kyrill
> +
> +(define_insn_reservation "wIR2" 2
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP2"))
> + "wCU1|wCU2|(wCU3+wCU4)"
> +)
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2014-12-18 10:21 [patch 1/2][ARM]: New CPU support for Marvell Whitney Xingxing Pan
2014-12-19 10:37 ` Kyrill Tkachov
@ 2014-12-19 10:59 ` Kyrill Tkachov
2014-12-19 11:03 ` Xingxing Pan
2015-02-26 10:12 ` Ramana Radhakrishnan
2 siblings, 1 reply; 13+ messages in thread
From: Kyrill Tkachov @ 2014-12-19 10:59 UTC (permalink / raw)
To: Xingxing Pan, gcc-patches
Cc: Ramana Radhakrishnan, Richard Earnshaw, xyqi, lgao1
Hi Xingxin,
It seems that your mail client mangled this patch, at least the
following hunk doesn't apply, even when I try to get it from the web
archives.
Could you please resend it as an attachment perhaps?
Thanks,
Kyrill
On 18/12/14 10:13, Xingxing Pan wrote:
> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
> index 423ee9e..b0ffbe1 100644
> --- a/gcc/config/arm/arm-cores.def
> +++ b/gcc/config/arm/arm-cores.def
> @@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7,
> cortexm7, 7EM,
> FL_LDSCHED, cortex_m7)
> ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM,
> FL_LDSCHED, v7m)
> ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M,
> FL_LDSCHED, v7m)
> ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4,
> 7A, FL_LDSCHED, 9e)
> +ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney,
> 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2014-12-19 10:59 ` Kyrill Tkachov
@ 2014-12-19 11:03 ` Xingxing Pan
2014-12-22 12:36 ` [PING][patch " Xingxing Pan
2015-01-09 11:29 ` [patch " Kyrill Tkachov
0 siblings, 2 replies; 13+ messages in thread
From: Xingxing Pan @ 2014-12-19 11:03 UTC (permalink / raw)
To: Kyrill Tkachov, gcc-patches
Cc: Ramana Radhakrishnan, Richard Earnshaw, Xinyu Qi, Liping Gao
[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]
On 19/12/2014 18:38, Kyrill Tkachov wrote:
> Hi Xingxin,
>
> It seems that your mail client mangled this patch, at least the
> following hunk doesn't apply, even when I try to get it from the web
> archives.
> Could you please resend it as an attachment perhaps?
>
> Thanks,
> Kyrill
>
> On 18/12/14 10:13, Xingxing Pan wrote:
>> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
>> index 423ee9e..b0ffbe1 100644
>> --- a/gcc/config/arm/arm-cores.def
>> +++ b/gcc/config/arm/arm-cores.def
>> @@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7,
>> cortexm7, 7EM,
>> FL_LDSCHED, cortex_m7)
>> ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM,
>> FL_LDSCHED, v7m)
>> ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M,
>> FL_LDSCHED, v7m)
>> ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4,
>> 7A, FL_LDSCHED, 9e)
>> +ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney,
>> 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
>
>
Hi Kyrill,
I've changed the code to use "tune" attribute directly. The new patch is
attached.
Thanks,
Xingxing
[-- Attachment #2: whitney-p1.patch --]
[-- Type: text/x-patch, Size: 36537 bytes --]
commit 56745b611d40b77e1911075159f89959335d0298
Author: Xingxing Pan <xxingpan@marvell.com>
Date: Thu Dec 18 16:58:05 2014 +0800
2014-12-18 Xingxing Pan <xxingpan@marvell.com>
* config/arm/arm-cores.def: Add new core marvell-whitney.
* config/arm/arm-protos.h:
(marvell_whitney_vector_element_size_is_byte): Declare.
(marvell_whitney_non_shift_with_shift_operand): Ditto.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm.c (arm_marvell_whitney_tune): New structure.
(arm_issue_rate): Add marvell_whitney.
(marvell_whitney_vector_element_size_is_byte): New function.
(marvell_whitney_non_shift_with_shift_operand): Ditto.
* config/arm/arm.md: Include marvell-whitney.md.
(generic_sched): Add marvell_whitney.
(generic_vfp): Ditto.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
* config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
* config/arm/marvell-whitney.md: New file.
* doc/invoke.texi: Document marvell-whitney.
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 423ee9e..b0ffbe1 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e)
+ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
/* V7 big.LITTLE implementations */
ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 20cfa9f..e86db1e 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -231,6 +231,9 @@ extern void arm_order_regs_for_local_alloc (void);
extern int arm_max_conditional_execute ();
+extern bool marvell_whitney_vector_element_size_is_byte (rtx insn);
+extern bool marvell_whitney_non_shift_with_shift_operand (rtx insn);
+
/* Vectorizer cost model implementation. */
struct cpu_vec_costs {
const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 9b1886e..3371ce3 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -298,6 +298,9 @@ EnumValue
Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
EnumValue
+Enum(processor_type) String(marvell-whitney) Value(marvell_whitney)
+
+EnumValue
Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d300c51..c73c33c 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -28,9 +28,10 @@
cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
genericv7a,cortexa5,cortexa7,
cortexa8,cortexa9,cortexa12,
- cortexa15,cortexa17,cortexr4,cortexr4f,
- cortexr5,cortexr7,cortexm7,
- cortexm4,cortexm3,marvell_pj4,
- cortexa15cortexa7,cortexa17cortexa7,cortexa53,
- cortexa57,cortexa57cortexa53"
+ cortexa15,cortexa17,cortexr4,
+ cortexr4f,cortexr5,cortexr7,
+ cortexm7,cortexm4,cortexm3,
+ marvell_pj4,marvell_whitney,cortexa15cortexa7,
+ cortexa17cortexa7,cortexa53,cortexa57,
+ cortexa57cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0ec526b..183da4c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1914,6 +1914,25 @@ const struct tune_params arm_cortex_a9_tune =
8 /* Maximum insns to inline memset. */
};
+const struct tune_params arm_marvell_whitney_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa9_extra_costs,
+ cortex_a9_sched_adjust_cost,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_BENEFICIAL(4,32,32),
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false, /* Prefer 32-bit encodings. */
+ false, /* Prefer Neon for stringops. */
+ 8 /* Maximum insns to inline memset. */
+};
+
const struct tune_params arm_cortex_a12_tune =
{
arm_9e_rtx_costs,
@@ -11608,6 +11627,49 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int * cost)
return true;
}
+/* Return true if vector element size is byte. */
+bool
+marvell_whitney_vector_element_size_is_byte (rtx insn)
+{
+ if (GET_CODE (PATTERN (insn)) == SET)
+ {
+ if ((GET_MODE (SET_DEST (PATTERN (insn))) == V8QImode) ||
+ (GET_MODE (SET_DEST (PATTERN (insn))) == V16QImode))
+ return true;
+ }
+
+ return false;
+}
+
+/* Return true if INSN has shift operation but is not a shift insn. */
+bool
+marvell_whitney_non_shift_with_shift_operand (rtx insn)
+{
+ rtx pat = PATTERN (insn);
+
+ if (GET_CODE (pat) != SET)
+ return false;
+
+ /* Is not a shift insn. */
+ rtx rvalue = SET_SRC (pat);
+ RTX_CODE code = GET_CODE (rvalue);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return false;
+
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
+ {
+ /* Has shift operation. */
+ RTX_CODE code = GET_CODE (*iter);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return true;
+ }
+
+ return false;
+}
+
/* Implement TARGET_REGISTER_MOVE_COST.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
@@ -27031,6 +27093,7 @@ arm_issue_rate (void)
{
case cortexa15:
case cortexa57:
+ case marvell_whitney:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 822760b..8f02743 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -386,7 +386,8 @@
arm926ejs,arm1020e,arm1026ejs,arm1136js,\
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa17,\
- cortexa53,cortexm4,cortexm7,marvell_pj4")
+ cortexa53,cortexm4,cortexm7,marvell_pj4,\
+ marvell_whitney")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -396,7 +397,7 @@
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
cortexa8,cortexa9,cortexa53,cortexm4,\
- cortexm7,marvell_pj4")
+ cortexm7,marvell_pj4,marvell_whitney")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -426,6 +427,7 @@
(include "cortex-m4-fpu.md")
(include "vfp11.md")
(include "marvell-pj4.md")
+(include "marvell-whitney.md")
\f
;;---------------------------------------------------------------------------
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index aa93aa4..07fab0f 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -68,6 +68,7 @@
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
@@ -96,6 +97,7 @@
|mcpu=cortex-m0.small-multiply \
|mcpu=cortex-m0plus.small-multiply \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=generic-armv7-a \
|march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \
diff --git a/gcc/config/arm/marvell-whitney.md b/gcc/config/arm/marvell-whitney.md
new file mode 100644
index 0000000..7e0b2de
--- /dev/null
+++ b/gcc/config/arm/marvell-whitney.md
@@ -0,0 +1,678 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+;;
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_attr "whitney_type"
+ "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
+ wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
+ wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
+ wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
+ wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
+ unknown"
+ (cond [
+ (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
+ adc_imm,bfm,branch,call,clz,extend,logic_imm,\
+ logic_reg,logics_imm,logics_reg,logics_shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
+ shift_reg,rev")
+ (const_string "wTP1")
+ (eq_attr "type" "alu_shift_imm,alu_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_non_shift_with_shift_operand (insn)")
+ (const_string "wTP2")
+ (const_string "wTP1"))
+ (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
+ mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
+ logic_shift_reg,multiple")
+ (const_string "wTP2")
+ (eq_attr "type" "mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
+ smulxy,umlal,umull")
+ (const_string "wTP3")
+ (eq_attr "type" "sdiv,udiv")
+ (const_string "wTP4")
+ (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
+ (const_string "wTP5")
+ (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
+ neon_load2_all_lanes,neon_load2_all_lanes_q,\
+ neon_load2_2reg_q")
+ (const_string "wTP7")
+ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
+ neon_load3_3reg,neon_load3_3reg_q,\
+ neon_load3_all_lanes,neon_load3_all_lanes_q")
+ (const_string "wTP8")
+ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
+ neon_load4_4reg,neon_load4_4reg_q,\
+ neon_load4_all_lanes,neon_load4_all_lanes_q")
+ (const_string "wTP9")
+ (eq_attr "type" "load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
+ neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
+ (const_string "wTP10")
+ (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
+ neon_load1_2reg,neon_load1_2reg_q,")
+ (const_string "wTP11")
+ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
+ neon_load1_one_lane,neon_load1_one_lane_q,")
+ (const_string "wTP6")
+ (eq_attr "type" "f_stored,f_stores,store1,store2")
+ (const_string "wTP12")
+ (eq_attr "type" "f_stored,neon_store1_3reg,neon_store1_3reg_q,\
+ neon_store1_4reg,neon_store1_4reg_q,\
+ neon_store2_4reg,neon_store2_4reg_q,\
+ neon_store3_3reg,neon_store3_3reg_q,\
+ neon_store3_one_lane,neon_store3_one_lane_q,\
+ neon_store4_4reg,neon_store4_4reg_q,\
+ neon_store4_one_lane,neon_store4_one_lane_q,\
+ store3,store4")
+ (const_string "wTP13")
+ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
+ neon_store1_2reg,neon_store1_2reg_q,\
+ neon_store1_one_lane,neon_store1_one_lane_q,\
+ neon_store2_2reg,neon_store2_2reg_q,\
+ neon_store2_one_lane,neon_store2_one_lane_q")
+ (const_string "wTP14")
+ (eq_attr "type" "fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
+ (const_string "wTP15")
+ (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
+ (const_string "wTP16")
+ (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
+ neon_fp_round_d")
+ (const_string "wTP17")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
+ neon_fp_round_d_q")
+ (const_string "wTP18")
+ (eq_attr "type" "fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
+ neon_fp_recps_s,neon_fp_rsqrts_s")
+ (const_string "wTP19")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
+ neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
+ (const_string "wTP20")
+ (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
+ neon_fp_abs_s,neon_fp_neg_s")
+ (const_string "wTP21")
+ (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
+ (const_string "wTP22")
+ (eq_attr "type" "fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
+ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
+ (const_string "wTP23")
+ (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
+ neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
+ (const_string "wTP24")
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
+ neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
+ (const_string "wTP25")
+ (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
+ neon_int_to_fp_s_q,neon_int_to_fp_d_q")
+ (const_string "wTP26")
+ (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
+ neon_fp_reduc_add_s")
+ (const_string "wTP27")
+ (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
+ neon_fp_reduc_add_s_q")
+ (const_string "wTP28")
+ (eq_attr "type" "fdivs")
+ (const_string "wTP29")
+ (eq_attr "type" "fsqrts")
+ (const_string "wTP30")
+ (eq_attr "type" "fdivd")
+ (const_string "wTP31")
+ (eq_attr "type" "fsqrtd")
+ (const_string "wTP32")
+ (eq_attr "type" "neon_reduc_add_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP33")
+ (const_string "wTP35"))
+ (eq_attr "type" "neon_reduc_add_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP34")
+ (const_string "wTP36"))
+ (eq_attr "type" "neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
+ neon_reduc_add,neon_sub,neon_sub_halve")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP37")
+ (const_string "wTP39"))
+ (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
+ neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP38")
+ (const_string "wTP40"))
+ (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
+ neon_compare,neon_compare_zero,neon_sub_long,\
+ neon_sub_widen,neon_tst")
+ (const_string "wTP37")
+ (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
+ neon_compare_zero_q,neon_tst_q")
+ (const_string "wTP38")
+ (eq_attr "type" "neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
+ (const_string "wTP40")
+ (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
+ neon_tbl4,neon_zip")
+ (const_string "wTP41")
+ (eq_attr "type" "neon_permute_q,neon_zip_q")
+ (const_string "wTP42")
+ (eq_attr "type" "neon_bsl,neon_logic")
+ (const_string "wTP43")
+ (eq_attr "type" "neon_arith_acc,neon_shift_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP43")
+ (const_string "wTP45"))
+ (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP44")
+ (const_string "wTP46"))
+ (eq_attr "type" "neon_logic_q")
+ (const_string "wTP44")
+ (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
+ neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
+ neon_move,neon_reduc_minmax,neon_rev")
+ (const_string "wTP47")
+ (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
+ neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
+ neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
+ neon_rev_q,neon_sat_shift_imm_narrow_q,\
+ neon_shift_imm_narrow_q")
+ (const_string "wTP48")
+ (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
+ neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
+ neon_shift_imm,neon_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP47")
+ (const_string "wTP49"))
+ (eq_attr "type" "neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
+ neon_sat_shift_imm_q,neon_shift_imm_q,\
+ neon_shift_reg_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_element_size_is_byte (insn)")
+ (const_string "wTP48")
+ (const_string "wTP50"))
+ (eq_attr "type" "neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
+ neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
+ (const_string "wTP51")
+ (eq_attr "type" "neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
+ neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
+ neon_sat_mul_b_long,neon_sat_mul_h_long,\
+ neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
+ neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
+ neon_sat_mul_s_scalar_q")
+ (const_string "wTP52")
+ (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
+ neon_mla_s_scalar")
+ (const_string "wTP53")
+ (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
+ neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
+ neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
+ neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
+ neon_sat_mla_b_long,neon_sat_mla_h_long,\
+ neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
+ neon_sat_mla_s_scalar_long")
+ (const_string "wTP54")
+ (eq_attr "type" "f_flag,f_mrc,f_mrrc")
+ (const_string "wTP57")
+ (eq_attr "type" "neon_to_gp,neon_to_gp_q")
+ (const_string "wTP55")
+ (eq_attr "type" "f_mcr,f_mcrr")
+ (const_string "wTP58")
+ (eq_attr "type" "neon_from_gp_q")
+ (const_string "wTP59")
+ (eq_attr "type" "neon_from_gp")
+ (const_string "wTP56")]
+ (const_string "unknown")))
+
+(define_automaton "whitney_pipe")
+
+(define_cpu_unit "wCU1" "whitney_pipe")
+(define_cpu_unit "wCU2" "whitney_pipe")
+(define_cpu_unit "wCU3" "whitney_pipe")
+(define_cpu_unit "wCU4" "whitney_pipe")
+(define_cpu_unit "wCU5" "whitney_pipe")
+(define_cpu_unit "wCU6" "whitney_pipe")
+(define_cpu_unit "wCU7" "whitney_pipe")
+(define_cpu_unit "wCU8" "whitney_pipe")
+(define_cpu_unit "wCU9" "whitney_pipe")
+(define_cpu_unit "wCU10" "whitney_pipe")
+(define_cpu_unit "wCU11" "whitney_pipe")
+(define_cpu_unit "wCU12" "whitney_pipe")
+(define_cpu_unit "wCU13" "whitney_pipe")
+
+(define_insn_reservation "wIR1" 1
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP1"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR2" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP2"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR3" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP3"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU8"
+)
+
+(define_insn_reservation "wIR4" 17
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP4"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU7*8"
+)
+
+(define_insn_reservation "wIR5" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP5"))
+ "(wCU1|wCU2|(wCU3+wCU4)), (wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR6" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP12"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU6"
+)
+
+(define_insn_reservation "wIR7" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP6"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR8" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP7"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR9" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP8"))
+ "(wCU1+wCU3+wCU4+wCU2)*3,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR10" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP9"))
+ "(wCU1+wCU3+wCU4+wCU2)*4,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR11" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP10"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR12" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP11"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR13" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP13"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,wCU6"
+)
+
+(define_insn_reservation "wIR14" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP14"))
+ "wCU1+wCU3+wCU4+wCU2,wCU6"
+)
+
+(define_insn_reservation "wIR15" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP15"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR16" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP16"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR17" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP17"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR18" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP18"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR19" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP19"))
+ "(wCU1+wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR20" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP20"))
+ "(wCU1+wCU2)*2, wCU9"
+)
+
+(define_insn_reservation "wIR21" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP21"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR22" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP22"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR23" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP23"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR24" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP24"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR25" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP25"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR26" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP26"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR27" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP27"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR28" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP28"))
+ "(wCU1+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR29" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP29"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR30" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP30"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR31" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP31"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR32" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP32"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR33" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP33"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR34" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP34"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR35" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP35"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR36" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP36"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR37" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP37"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR38" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP38"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR39" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP39"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR40" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP40"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR41" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP41"))
+ "(wCU1+wCU3+wCU4+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR42" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP42"))
+ "(wCU1+wCU3+wCU4+wCU2)*2, wCU10*3"
+)
+
+(define_insn_reservation "wIR43" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP43"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR44" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP44"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR45" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP45"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR46" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP46"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR47" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP47"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR48" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP48"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR49" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP49"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR50" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP50"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR51" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP51"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR52" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP52"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR53" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP53"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR54" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP54"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR55" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP55"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR56" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP56"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR57" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP57"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR58" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP58"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR59" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP59"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU11*2"
+)
+
+(define_insn_reservation "wIR60" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "unknown"))
+ "wCU13"
+)
+
+(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 5 "wIR22" "wIR41")
+(define_bypass 6 "wIR22" "wIR42")
+(define_bypass 6 "wIR23" "wIR41, wIR42")
+(define_bypass 6 "wIR24" "wIR41")
+(define_bypass 7 "wIR24" "wIR42")
+(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 7 "wIR26" "wIR41")
+(define_bypass 8 "wIR26" "wIR42")
+(define_bypass 6 "wIR27" "wIR41, wIR42")
+(define_bypass 6 "wIR28" "wIR41, wIR42")
+(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 6 "wIR33" "wIR41, wIR42")
+(define_bypass 6 "wIR34" "wIR41")
+(define_bypass 7 "wIR34" "wIR42")
+(define_bypass 6 "wIR35" "wIR41, wIR42")
+(define_bypass 6 "wIR36" "wIR41")
+(define_bypass 7 "wIR36" "wIR42")
+(define_bypass 6 "wIR37" "wIR41, wIR42")
+(define_bypass 6 "wIR38" "wIR41")
+(define_bypass 7 "wIR38" "wIR42")
+(define_bypass 6 "wIR39" "wIR41, wIR42")
+(define_bypass 6 "wIR40" "wIR41")
+(define_bypass 7 "wIR40" "wIR42")
+(define_bypass 6 "wIR41" "wIR41, wIR42")
+(define_bypass 6 "wIR42" "wIR41")
+(define_bypass 7 "wIR42" "wIR42")
+(define_bypass 6 "wIR43" "wIR41, wIR42")
+(define_bypass 6 "wIR44" "wIR41")
+(define_bypass 7 "wIR44" "wIR42")
+(define_bypass 6 "wIR45" "wIR41, wIR42")
+(define_bypass 6 "wIR46" "wIR41")
+(define_bypass 7 "wIR46" "wIR42")
+(define_bypass 6 "wIR47" "wIR41, wIR42")
+(define_bypass 6 "wIR48" "wIR41")
+(define_bypass 7 "wIR48" "wIR42")
+(define_bypass 6 "wIR49" "wIR41, wIR42")
+(define_bypass 6 "wIR50" "wIR41")
+(define_bypass 7 "wIR50" "wIR42")
+(define_bypass 8 "wIR51" "wIR41, wIR42")
+(define_bypass 8 "wIR52" "wIR41")
+(define_bypass 9 "wIR52" "wIR42")
+(define_bypass 8 "wIR53" "wIR41, wIR42")
+(define_bypass 8 "wIR54" "wIR41")
+(define_bypass 9 "wIR54" "wIR42")
+(define_bypass 2 "wIR56" "wIR41, wIR42")
+(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 5 "wIR58" "wIR41, wIR42")
+(define_bypass 5 "wIR59" "wIR41")
+(define_bypass 6 "wIR59" "wIR42")
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index d82a123..8af9ad2 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -61,7 +61,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/thumb2.md \
$(srcdir)/config/arm/vec-common.md \
$(srcdir)/config/arm/vfp11.md \
- $(srcdir)/config/arm/vfp.md
+ $(srcdir)/config/arm/vfp.md \
+ $(srcdir)/config/arm/marvell-whitney.md
s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 15068da..c2522de 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12869,6 +12869,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
@samp{marvell-pj4},
+@samp{marvell-whitney},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PING][patch 1/2][ARM]: New CPU support for Marvell Whitney
2014-12-19 11:03 ` Xingxing Pan
@ 2014-12-22 12:36 ` Xingxing Pan
2015-01-09 11:29 ` [patch " Kyrill Tkachov
1 sibling, 0 replies; 13+ messages in thread
From: Xingxing Pan @ 2014-12-22 12:36 UTC (permalink / raw)
To: Kyrill Tkachov, gcc-patches
Cc: Ramana Radhakrishnan, Richard Earnshaw, Xinyu Qi, Liping Gao
On 19/12/2014 19:01, Xingxing Pan wrote:
> On 19/12/2014 18:38, Kyrill Tkachov wrote:
>> Hi Xingxin,
>>
>> It seems that your mail client mangled this patch, at least the
>> following hunk doesn't apply, even when I try to get it from the web
>> archives.
>> Could you please resend it as an attachment perhaps?
>>
>> Thanks,
>> Kyrill
>>
>> On 18/12/14 10:13, Xingxing Pan wrote:
>>> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
>>> index 423ee9e..b0ffbe1 100644
>>> --- a/gcc/config/arm/arm-cores.def
>>> +++ b/gcc/config/arm/arm-cores.def
>>> @@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7,
>>> cortexm7, 7EM,
>>> FL_LDSCHED, cortex_m7)
>>> ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM,
>>> FL_LDSCHED, v7m)
>>> ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M,
>>> FL_LDSCHED, v7m)
>>> ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4,
>>> 7A, FL_LDSCHED, 9e)
>>> +ARM_CORE("marvell-whitney", marvell_whitney,
>>> marvell_whitney,
>>> 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
>>
>>
>
> Hi Kyrill,
>
> I've changed the code to use "tune" attribute directly. The new patch is
> attached.
>
> Thanks,
> Xingxing
Any comments are welcome.
Thanks,
Xingxing
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2014-12-19 11:03 ` Xingxing Pan
2014-12-22 12:36 ` [PING][patch " Xingxing Pan
@ 2015-01-09 11:29 ` Kyrill Tkachov
2015-01-13 9:51 ` Xingxing Pan
1 sibling, 1 reply; 13+ messages in thread
From: Kyrill Tkachov @ 2015-01-09 11:29 UTC (permalink / raw)
To: Xingxing Pan, gcc-patches
Cc: Ramana Radhakrishnan, Richard Earnshaw, Xinyu Qi, Liping Gao
Hi Xingxing,
On 19/12/14 11:01, Xingxing Pan wrote:
> +/* Return true if vector element size is byte. */
Minor nit: two spaces after full stop and before */ Same in other places
in the patch.
> +bool
> +marvell_whitney_vector_element_size_is_byte (rtx insn)
> +{
> + if (GET_CODE (PATTERN (insn)) == SET)
> + {
> + if ((GET_MODE (SET_DEST (PATTERN (insn))) == V8QImode) ||
> + (GET_MODE (SET_DEST (PATTERN (insn))) == V16QImode))
> + return true;
> + }
> +
> + return false;
> +}
I see this is called from inside marvell-whitney.md. It seems to me that
this function takes RTX insns. Can the type of this be strengthened to
rtx_insn * ?
Also, this should be refactored and written a bit more generally by
checking for VECTOR_MODE_P and then GET_MODE_INNER for QImode, saving
you the trouble of enumerating the different vector QI modes.
> +
> +/* Return true if INSN has shift operation but is not a shift insn. */
> +bool
> +marvell_whitney_non_shift_with_shift_operand (rtx insn)
Similar comment. Can this be strengthened to rtx_insn * ?
Thanks,
Kyrill
> +{
> + rtx pat = PATTERN (insn);
> +
> + if (GET_CODE (pat) != SET)
> + return false;
> +
> + /* Is not a shift insn. */
> + rtx rvalue = SET_SRC (pat);
> + RTX_CODE code = GET_CODE (rvalue);
> + if (code == ASHIFT || code == ASHIFTRT
> + || code == LSHIFTRT || code == ROTATERT)
> + return false;
> +
> + subrtx_iterator::array_type array;
> + FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
> + {
> + /* Has shift operation. */
> + RTX_CODE code = GET_CODE (*iter);
> + if (code == ASHIFT || code == ASHIFTRT
> + || code == LSHIFTRT || code == ROTATERT)
> + return true;
> + }
> +
> + return false;
> +}
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2015-01-09 11:29 ` [patch " Kyrill Tkachov
@ 2015-01-13 9:51 ` Xingxing Pan
2015-02-25 13:43 ` Xingxing Pan
0 siblings, 1 reply; 13+ messages in thread
From: Xingxing Pan @ 2015-01-13 9:51 UTC (permalink / raw)
To: Kyrill Tkachov, gcc-patches
Cc: Ramana Radhakrishnan, Richard Earnshaw, Xinyu Qi, Liping Gao
[-- Attachment #1: Type: text/plain, Size: 1950 bytes --]
On 09/01/2015 19:22, Kyrill Tkachov wrote:
> Hi Xingxing,
>
> On 19/12/14 11:01, Xingxing Pan wrote:
>> +/* Return true if vector element size is byte. */
> Minor nit: two spaces after full stop and before */ Same in other places
> in the patch.
>
>> +bool
>> +marvell_whitney_vector_element_size_is_byte (rtx insn)
>> +{
>> + if (GET_CODE (PATTERN (insn)) == SET)
>> + {
>> + if ((GET_MODE (SET_DEST (PATTERN (insn))) == V8QImode) ||
>> + (GET_MODE (SET_DEST (PATTERN (insn))) == V16QImode))
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>
> I see this is called from inside marvell-whitney.md. It seems to me that
> this function takes RTX insns. Can the type of this be strengthened to
> rtx_insn * ?
> Also, this should be refactored and written a bit more generally by
> checking for VECTOR_MODE_P and then GET_MODE_INNER for QImode, saving
> you the trouble of enumerating the different vector QI modes.
>
>
>> +
>> +/* Return true if INSN has shift operation but is not a shift insn. */
>> +bool
>> +marvell_whitney_non_shift_with_shift_operand (rtx insn)
>
> Similar comment. Can this be strengthened to rtx_insn * ?
>
> Thanks,
> Kyrill
>> +{
>> + rtx pat = PATTERN (insn);
>> +
>> + if (GET_CODE (pat) != SET)
>> + return false;
>> +
>> + /* Is not a shift insn. */
>> + rtx rvalue = SET_SRC (pat);
>> + RTX_CODE code = GET_CODE (rvalue);
>> + if (code == ASHIFT || code == ASHIFTRT
>> + || code == LSHIFTRT || code == ROTATERT)
>> + return false;
>> +
>> + subrtx_iterator::array_type array;
>> + FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
>> + {
>> + /* Has shift operation. */
>> + RTX_CODE code = GET_CODE (*iter);
>> + if (code == ASHIFT || code == ASHIFTRT
>> + || code == LSHIFTRT || code == ROTATERT)
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>
>
Hi Kyrill,
Thanks for advice. Refactored patch is attached.
--
Regards,
Xingxing
[-- Attachment #2: whitney-part1-20140113.patch --]
[-- Type: text/x-patch, Size: 36076 bytes --]
commit 3627056607b1e8604ac8d85ed44fdc7d3209cd3e
Author: Xingxing Pan <xxingpan@marvell.com>
Date: Thu Dec 18 16:58:05 2014 +0800
2015-01-13 Xingxing Pan <xxingpan@marvell.com>
* config/arm/arm-cores.def: Add new core marvell-whitney.
* config/arm/arm-protos.h:
(marvell_whitney_vector_mode_qi): Declare.
(marvell_whitney_inner_shift): Ditto.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm.c (arm_marvell_whitney_tune): New structure.
(arm_issue_rate): Add marvell_whitney.
(marvell_whitney_vector_mode_qi): New function.
(marvell_whitney_inner_shift): Ditto.
* config/arm/arm.md: Include marvell-whitney.md.
(generic_sched): Add marvell_whitney.
(generic_vfp): Ditto.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
* config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
* config/arm/marvell-whitney.md: New file.
* doc/invoke.texi: Document marvell-whitney.
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 6fa5d99..26eb7ab 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e)
+ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
/* V7 big.LITTLE implementations */
ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index fc45348..45001ae 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -231,6 +231,9 @@ extern void arm_order_regs_for_local_alloc (void);
extern int arm_max_conditional_execute ();
+extern bool marvell_whitney_vector_mode_qi (rtx_insn *insn);
+extern bool marvell_whitney_inner_shift (rtx_insn *insn);
+
/* Vectorizer cost model implementation. */
struct cpu_vec_costs {
const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index ece9d5e..dc5f364 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -298,6 +298,9 @@ EnumValue
Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
EnumValue
+Enum(processor_type) String(marvell-whitney) Value(marvell_whitney)
+
+EnumValue
Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 452820ab..c73c33c 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -31,6 +31,7 @@
cortexa15,cortexa17,cortexr4,
cortexr4f,cortexr5,cortexr7,
cortexm7,cortexm4,cortexm3,
- marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
- cortexa53,cortexa57,cortexa57cortexa53"
+ marvell_pj4,marvell_whitney,cortexa15cortexa7,
+ cortexa17cortexa7,cortexa53,cortexa57,
+ cortexa57cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c34ecf..993be02 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1920,6 +1920,25 @@ const struct tune_params arm_cortex_a9_tune =
8 /* Maximum insns to inline memset. */
};
+const struct tune_params arm_marvell_whitney_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa9_extra_costs,
+ cortex_a9_sched_adjust_cost,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_BENEFICIAL(4,32,32),
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false, /* Prefer 32-bit encodings. */
+ false, /* Prefer Neon for stringops. */
+ 8 /* Maximum insns to inline memset. */
+};
+
const struct tune_params arm_cortex_a12_tune =
{
arm_9e_rtx_costs,
@@ -11614,6 +11633,51 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int * cost)
return true;
}
+/* Return true if vector element size is byte. */
+bool
+marvell_whitney_vector_mode_qi (rtx_insn *insn)
+{
+ machine_mode mode;
+
+ if (GET_CODE (PATTERN (insn)) == SET)
+ {
+ mode = GET_MODE (SET_DEST (PATTERN (insn)));
+ if (VECTOR_MODE_P (mode) && GET_MODE_INNER (mode) == QImode)
+ return true;
+ }
+
+ return false;
+}
+
+/* Return true if a non-shift insn has a shift operand. */
+bool
+marvell_whitney_inner_shift (rtx_insn *insn)
+{
+ rtx pat = PATTERN (insn);
+
+ if (GET_CODE (pat) != SET)
+ return false;
+
+ /* Is not a shift insn. */
+ rtx rvalue = SET_SRC (pat);
+ RTX_CODE code = GET_CODE (rvalue);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return false;
+
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
+ {
+ /* Has shift operation. */
+ RTX_CODE code = GET_CODE (*iter);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return true;
+ }
+
+ return false;
+}
+
/* Implement TARGET_REGISTER_MOVE_COST.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
@@ -27037,6 +27101,7 @@ arm_issue_rate (void)
{
case cortexa15:
case cortexa57:
+ case marvell_whitney:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index c61057f..c554bf3 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -386,7 +386,8 @@
arm926ejs,arm1020e,arm1026ejs,arm1136js,\
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa17,\
- cortexa53,cortexm4,cortexm7,marvell_pj4")
+ cortexa53,cortexm4,cortexm7,marvell_pj4,\
+ marvell_whitney")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -396,7 +397,7 @@
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
cortexa8,cortexa9,cortexa53,cortexm4,\
- cortexm7,marvell_pj4")
+ cortexm7,marvell_pj4,marvell_whitney")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -426,6 +427,7 @@
(include "cortex-m4-fpu.md")
(include "vfp11.md")
(include "marvell-pj4.md")
+(include "marvell-whitney.md")
\f
;;---------------------------------------------------------------------------
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 6e69b81..641d7c5 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -68,6 +68,7 @@
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
@@ -96,6 +97,7 @@
|mcpu=cortex-m0.small-multiply \
|mcpu=cortex-m0plus.small-multiply \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=generic-armv7-a \
|march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \
diff --git a/gcc/config/arm/marvell-whitney.md b/gcc/config/arm/marvell-whitney.md
new file mode 100644
index 0000000..fffbd29
--- /dev/null
+++ b/gcc/config/arm/marvell-whitney.md
@@ -0,0 +1,678 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+;;
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_attr "whitney_type"
+ "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
+ wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
+ wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
+ wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
+ wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
+ unknown"
+ (cond [
+ (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
+ adc_imm,bfm,branch,call,clz,extend,logic_imm,\
+ logic_reg,logics_imm,logics_reg,logics_shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
+ shift_reg,rev")
+ (const_string "wTP1")
+ (eq_attr "type" "alu_shift_imm,alu_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_inner_shift (insn)")
+ (const_string "wTP2")
+ (const_string "wTP1"))
+ (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
+ mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
+ logic_shift_reg,multiple")
+ (const_string "wTP2")
+ (eq_attr "type" "mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
+ smulxy,umlal,umull")
+ (const_string "wTP3")
+ (eq_attr "type" "sdiv,udiv")
+ (const_string "wTP4")
+ (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
+ (const_string "wTP5")
+ (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
+ neon_load2_all_lanes,neon_load2_all_lanes_q,\
+ neon_load2_2reg_q")
+ (const_string "wTP7")
+ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
+ neon_load3_3reg,neon_load3_3reg_q,\
+ neon_load3_all_lanes,neon_load3_all_lanes_q")
+ (const_string "wTP8")
+ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
+ neon_load4_4reg,neon_load4_4reg_q,\
+ neon_load4_all_lanes,neon_load4_all_lanes_q")
+ (const_string "wTP9")
+ (eq_attr "type" "load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
+ neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
+ (const_string "wTP10")
+ (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
+ neon_load1_2reg,neon_load1_2reg_q,")
+ (const_string "wTP11")
+ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
+ neon_load1_one_lane,neon_load1_one_lane_q,")
+ (const_string "wTP6")
+ (eq_attr "type" "f_stored,f_stores,store1,store2")
+ (const_string "wTP12")
+ (eq_attr "type" "f_stored,neon_store1_3reg,neon_store1_3reg_q,\
+ neon_store1_4reg,neon_store1_4reg_q,\
+ neon_store2_4reg,neon_store2_4reg_q,\
+ neon_store3_3reg,neon_store3_3reg_q,\
+ neon_store3_one_lane,neon_store3_one_lane_q,\
+ neon_store4_4reg,neon_store4_4reg_q,\
+ neon_store4_one_lane,neon_store4_one_lane_q,\
+ store3,store4")
+ (const_string "wTP13")
+ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
+ neon_store1_2reg,neon_store1_2reg_q,\
+ neon_store1_one_lane,neon_store1_one_lane_q,\
+ neon_store2_2reg,neon_store2_2reg_q,\
+ neon_store2_one_lane,neon_store2_one_lane_q")
+ (const_string "wTP14")
+ (eq_attr "type" "fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
+ (const_string "wTP15")
+ (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
+ (const_string "wTP16")
+ (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
+ neon_fp_round_d")
+ (const_string "wTP17")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
+ neon_fp_round_d_q")
+ (const_string "wTP18")
+ (eq_attr "type" "fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
+ neon_fp_recps_s,neon_fp_rsqrts_s")
+ (const_string "wTP19")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
+ neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
+ (const_string "wTP20")
+ (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
+ neon_fp_abs_s,neon_fp_neg_s")
+ (const_string "wTP21")
+ (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
+ (const_string "wTP22")
+ (eq_attr "type" "fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
+ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
+ (const_string "wTP23")
+ (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
+ neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
+ (const_string "wTP24")
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
+ neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
+ (const_string "wTP25")
+ (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
+ neon_int_to_fp_s_q,neon_int_to_fp_d_q")
+ (const_string "wTP26")
+ (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
+ neon_fp_reduc_add_s")
+ (const_string "wTP27")
+ (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
+ neon_fp_reduc_add_s_q")
+ (const_string "wTP28")
+ (eq_attr "type" "fdivs")
+ (const_string "wTP29")
+ (eq_attr "type" "fsqrts")
+ (const_string "wTP30")
+ (eq_attr "type" "fdivd")
+ (const_string "wTP31")
+ (eq_attr "type" "fsqrtd")
+ (const_string "wTP32")
+ (eq_attr "type" "neon_reduc_add_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP33")
+ (const_string "wTP35"))
+ (eq_attr "type" "neon_reduc_add_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP34")
+ (const_string "wTP36"))
+ (eq_attr "type" "neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
+ neon_reduc_add,neon_sub,neon_sub_halve")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP37")
+ (const_string "wTP39"))
+ (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
+ neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP38")
+ (const_string "wTP40"))
+ (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
+ neon_compare,neon_compare_zero,neon_sub_long,\
+ neon_sub_widen,neon_tst")
+ (const_string "wTP37")
+ (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
+ neon_compare_zero_q,neon_tst_q")
+ (const_string "wTP38")
+ (eq_attr "type" "neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
+ (const_string "wTP40")
+ (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
+ neon_tbl4,neon_zip")
+ (const_string "wTP41")
+ (eq_attr "type" "neon_permute_q,neon_zip_q")
+ (const_string "wTP42")
+ (eq_attr "type" "neon_bsl,neon_logic")
+ (const_string "wTP43")
+ (eq_attr "type" "neon_arith_acc,neon_shift_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP43")
+ (const_string "wTP45"))
+ (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP44")
+ (const_string "wTP46"))
+ (eq_attr "type" "neon_logic_q")
+ (const_string "wTP44")
+ (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
+ neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
+ neon_move,neon_reduc_minmax,neon_rev")
+ (const_string "wTP47")
+ (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
+ neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
+ neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
+ neon_rev_q,neon_sat_shift_imm_narrow_q,\
+ neon_shift_imm_narrow_q")
+ (const_string "wTP48")
+ (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
+ neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
+ neon_shift_imm,neon_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP47")
+ (const_string "wTP49"))
+ (eq_attr "type" "neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
+ neon_sat_shift_imm_q,neon_shift_imm_q,\
+ neon_shift_reg_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP48")
+ (const_string "wTP50"))
+ (eq_attr "type" "neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
+ neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
+ (const_string "wTP51")
+ (eq_attr "type" "neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
+ neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
+ neon_sat_mul_b_long,neon_sat_mul_h_long,\
+ neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
+ neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
+ neon_sat_mul_s_scalar_q")
+ (const_string "wTP52")
+ (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
+ neon_mla_s_scalar")
+ (const_string "wTP53")
+ (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
+ neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
+ neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
+ neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
+ neon_sat_mla_b_long,neon_sat_mla_h_long,\
+ neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
+ neon_sat_mla_s_scalar_long")
+ (const_string "wTP54")
+ (eq_attr "type" "f_flag,f_mrc,f_mrrc")
+ (const_string "wTP57")
+ (eq_attr "type" "neon_to_gp,neon_to_gp_q")
+ (const_string "wTP55")
+ (eq_attr "type" "f_mcr,f_mcrr")
+ (const_string "wTP58")
+ (eq_attr "type" "neon_from_gp_q")
+ (const_string "wTP59")
+ (eq_attr "type" "neon_from_gp")
+ (const_string "wTP56")]
+ (const_string "unknown")))
+
+(define_automaton "whitney_pipe")
+
+(define_cpu_unit "wCU1" "whitney_pipe")
+(define_cpu_unit "wCU2" "whitney_pipe")
+(define_cpu_unit "wCU3" "whitney_pipe")
+(define_cpu_unit "wCU4" "whitney_pipe")
+(define_cpu_unit "wCU5" "whitney_pipe")
+(define_cpu_unit "wCU6" "whitney_pipe")
+(define_cpu_unit "wCU7" "whitney_pipe")
+(define_cpu_unit "wCU8" "whitney_pipe")
+(define_cpu_unit "wCU9" "whitney_pipe")
+(define_cpu_unit "wCU10" "whitney_pipe")
+(define_cpu_unit "wCU11" "whitney_pipe")
+(define_cpu_unit "wCU12" "whitney_pipe")
+(define_cpu_unit "wCU13" "whitney_pipe")
+
+(define_insn_reservation "wIR1" 1
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP1"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR2" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP2"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR3" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP3"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU8"
+)
+
+(define_insn_reservation "wIR4" 17
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP4"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU7*8"
+)
+
+(define_insn_reservation "wIR5" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP5"))
+ "(wCU1|wCU2|(wCU3+wCU4)), (wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR6" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP12"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU6"
+)
+
+(define_insn_reservation "wIR7" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP6"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR8" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP7"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR9" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP8"))
+ "(wCU1+wCU3+wCU4+wCU2)*3,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR10" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP9"))
+ "(wCU1+wCU3+wCU4+wCU2)*4,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR11" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP10"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR12" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP11"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR13" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP13"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,wCU6"
+)
+
+(define_insn_reservation "wIR14" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP14"))
+ "wCU1+wCU3+wCU4+wCU2,wCU6"
+)
+
+(define_insn_reservation "wIR15" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP15"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR16" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP16"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR17" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP17"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR18" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP18"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR19" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP19"))
+ "(wCU1+wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR20" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP20"))
+ "(wCU1+wCU2)*2, wCU9"
+)
+
+(define_insn_reservation "wIR21" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP21"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR22" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP22"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR23" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP23"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR24" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP24"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR25" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP25"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR26" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP26"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR27" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP27"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR28" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP28"))
+ "(wCU1+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR29" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP29"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR30" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP30"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR31" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP31"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR32" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP32"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR33" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP33"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR34" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP34"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR35" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP35"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR36" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP36"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR37" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP37"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR38" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP38"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR39" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP39"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR40" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP40"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR41" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP41"))
+ "(wCU1+wCU3+wCU4+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR42" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP42"))
+ "(wCU1+wCU3+wCU4+wCU2)*2, wCU10*3"
+)
+
+(define_insn_reservation "wIR43" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP43"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR44" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP44"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR45" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP45"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR46" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP46"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR47" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP47"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR48" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP48"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR49" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP49"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR50" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP50"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR51" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP51"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR52" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP52"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR53" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP53"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR54" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP54"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR55" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP55"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR56" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP56"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR57" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP57"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR58" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP58"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR59" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP59"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU11*2"
+)
+
+(define_insn_reservation "wIR60" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "unknown"))
+ "wCU13"
+)
+
+(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 5 "wIR22" "wIR41")
+(define_bypass 6 "wIR22" "wIR42")
+(define_bypass 6 "wIR23" "wIR41, wIR42")
+(define_bypass 6 "wIR24" "wIR41")
+(define_bypass 7 "wIR24" "wIR42")
+(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 7 "wIR26" "wIR41")
+(define_bypass 8 "wIR26" "wIR42")
+(define_bypass 6 "wIR27" "wIR41, wIR42")
+(define_bypass 6 "wIR28" "wIR41, wIR42")
+(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 6 "wIR33" "wIR41, wIR42")
+(define_bypass 6 "wIR34" "wIR41")
+(define_bypass 7 "wIR34" "wIR42")
+(define_bypass 6 "wIR35" "wIR41, wIR42")
+(define_bypass 6 "wIR36" "wIR41")
+(define_bypass 7 "wIR36" "wIR42")
+(define_bypass 6 "wIR37" "wIR41, wIR42")
+(define_bypass 6 "wIR38" "wIR41")
+(define_bypass 7 "wIR38" "wIR42")
+(define_bypass 6 "wIR39" "wIR41, wIR42")
+(define_bypass 6 "wIR40" "wIR41")
+(define_bypass 7 "wIR40" "wIR42")
+(define_bypass 6 "wIR41" "wIR41, wIR42")
+(define_bypass 6 "wIR42" "wIR41")
+(define_bypass 7 "wIR42" "wIR42")
+(define_bypass 6 "wIR43" "wIR41, wIR42")
+(define_bypass 6 "wIR44" "wIR41")
+(define_bypass 7 "wIR44" "wIR42")
+(define_bypass 6 "wIR45" "wIR41, wIR42")
+(define_bypass 6 "wIR46" "wIR41")
+(define_bypass 7 "wIR46" "wIR42")
+(define_bypass 6 "wIR47" "wIR41, wIR42")
+(define_bypass 6 "wIR48" "wIR41")
+(define_bypass 7 "wIR48" "wIR42")
+(define_bypass 6 "wIR49" "wIR41, wIR42")
+(define_bypass 6 "wIR50" "wIR41")
+(define_bypass 7 "wIR50" "wIR42")
+(define_bypass 8 "wIR51" "wIR41, wIR42")
+(define_bypass 8 "wIR52" "wIR41")
+(define_bypass 9 "wIR52" "wIR42")
+(define_bypass 8 "wIR53" "wIR41, wIR42")
+(define_bypass 8 "wIR54" "wIR41")
+(define_bypass 9 "wIR54" "wIR42")
+(define_bypass 2 "wIR56" "wIR41, wIR42")
+(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 5 "wIR58" "wIR41, wIR42")
+(define_bypass 5 "wIR59" "wIR41")
+(define_bypass 6 "wIR59" "wIR42")
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index df97a13..18dde79 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -61,7 +61,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/thumb2.md \
$(srcdir)/config/arm/vec-common.md \
$(srcdir)/config/arm/vfp11.md \
- $(srcdir)/config/arm/vfp.md
+ $(srcdir)/config/arm/vfp.md \
+ $(srcdir)/config/arm/marvell-whitney.md
s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0182952..5734e3f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12954,6 +12954,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
@samp{marvell-pj4},
+@samp{marvell-whitney},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2015-01-13 9:51 ` Xingxing Pan
@ 2015-02-25 13:43 ` Xingxing Pan
2015-02-26 8:04 ` Xingxing Pan
2015-02-26 10:27 ` Kyrill Tkachov
0 siblings, 2 replies; 13+ messages in thread
From: Xingxing Pan @ 2015-02-25 13:43 UTC (permalink / raw)
To: Kyrill Tkachov, gcc-patches, nickc, paul, Ramana Radhakrishnan,
Richard Earnshaw, James Greenhalgh
Cc: Xinyu Qi, Liping Gao
[-- Attachment #1: Type: text/plain, Size: 128 bytes --]
Hi,
This patch merges pipeline description for marvell-whitney to latest code base.
Is it OK for trunk?
--
Regards,
Xingxing
[-- Attachment #2: whitney_p1_20150225.patch --]
[-- Type: text/x-patch, Size: 35978 bytes --]
commit 83974dde8d9f773df1004aa1d5e3b05d8a33f5e0
Author: Xingxing Pan <xxingpan@marvell.com>
Date: Wed Feb 25 10:24:40 2015 +0800
2015-02-25 Xingxing Pan <xxingpan@marvell.com>
* config/arm/arm-cores.def: Add new core marvell-whitney.
* config/arm/arm-protos.h:
(marvell_whitney_vector_mode_qi): Declare.
(marvell_whitney_inner_shift): Ditto.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm.c (arm_marvell_whitney_tune): New structure.
(arm_issue_rate): Add marvell_whitney.
(marvell_whitney_vector_mode_qi): New function.
(marvell_whitney_inner_shift): Ditto.
* config/arm/arm.md: Include marvell-whitney.md.
(generic_sched): Add marvell_whitney.
(generic_vfp): Ditto.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
* config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
* config/arm/marvell-whitney.md: New file.
* doc/invoke.texi: Document marvell-whitney.
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index d7e730d..fc76eb5 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e)
+ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
/* V7 big.LITTLE implementations */
ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 307babb..d047dbc 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -231,6 +231,9 @@ extern void arm_order_regs_for_local_alloc (void);
extern int arm_max_conditional_execute ();
+extern bool marvell_whitney_vector_mode_qi (rtx_insn *insn);
+extern bool marvell_whitney_inner_shift (rtx_insn *insn);
+
/* Vectorizer cost model implementation. */
struct cpu_vec_costs {
const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 3450e5b..f0f9f3f 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -298,6 +298,9 @@ EnumValue
Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
EnumValue
+Enum(processor_type) String(marvell-whitney) Value(marvell_whitney)
+
+EnumValue
Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d459f27..fbfab2e 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -31,7 +31,8 @@
cortexa15,cortexa17,cortexr4,
cortexr4f,cortexr5,cortexr7,
cortexm7,cortexm4,cortexm3,
- marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
- cortexa53,cortexa57,cortexa72,
- xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ marvell_pj4,marvell_whitney,cortexa15cortexa7,
+ cortexa17cortexa7,cortexa53,cortexa57,
+ cortexa72,xgene1,cortexa57cortexa53,
+ cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7bf5b4d..e68287f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2000,6 +2000,25 @@ const struct tune_params arm_cortex_a9_tune =
ARM_SCHED_AUTOPREF_OFF /* Sched L2 autopref. */
};
+const struct tune_params arm_marvell_whitney_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa9_extra_costs,
+ cortex_a9_sched_adjust_cost,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_BENEFICIAL(4,32,32),
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false, /* Prefer 32-bit encodings. */
+ false, /* Prefer Neon for stringops. */
+ 8 /* Maximum insns to inline memset. */
+};
+
const struct tune_params arm_cortex_a12_tune =
{
arm_9e_rtx_costs,
@@ -11717,6 +11736,51 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int * cost)
return true;
}
+/* Return true if vector element size is byte. */
+bool
+marvell_whitney_vector_mode_qi (rtx_insn *insn)
+{
+ machine_mode mode;
+
+ if (GET_CODE (PATTERN (insn)) == SET)
+ {
+ mode = GET_MODE (SET_DEST (PATTERN (insn)));
+ if (VECTOR_MODE_P (mode) && GET_MODE_INNER (mode) == QImode)
+ return true;
+ }
+
+ return false;
+}
+
+/* Return true if a non-shift insn has a shift operand. */
+bool
+marvell_whitney_inner_shift (rtx_insn *insn)
+{
+ rtx pat = PATTERN (insn);
+
+ if (GET_CODE (pat) != SET)
+ return false;
+
+ /* Is not a shift insn. */
+ rtx rvalue = SET_SRC (pat);
+ RTX_CODE code = GET_CODE (rvalue);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return false;
+
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
+ {
+ /* Has shift operation. */
+ RTX_CODE code = GET_CODE (*iter);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return true;
+ }
+
+ return false;
+}
+
/* Implement TARGET_REGISTER_MOVE_COST.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
@@ -27154,6 +27218,7 @@ arm_issue_rate (void)
case cortexa15:
case cortexa57:
+ case marvell_whitney:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index c13e9b2..58937ec 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -373,7 +373,7 @@
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa17,\
cortexa53,cortexa57,cortexm4,cortexm7,\
- marvell_pj4,xgene1")
+ marvell_pj4,marvell_whitney,xgene1")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -383,7 +383,7 @@
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
cortexa8,cortexa9,cortexa53,cortexm4,\
- cortexm7,marvell_pj4,xgene1")
+ cortexm7,marvell_pj4,marvell_whitney,xgene1")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -414,6 +414,7 @@
(include "cortex-m4-fpu.md")
(include "vfp11.md")
(include "marvell-pj4.md")
+(include "marvell-whitney.md")
(include "xgene1.md")
\f
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c62130d..a64625c 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -68,6 +68,7 @@
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
@@ -102,6 +103,7 @@
|mcpu=cortex-m0.small-multiply \
|mcpu=cortex-m0plus.small-multiply \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=generic-armv7-a \
|march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \
diff --git a/gcc/config/arm/marvell-whitney.md b/gcc/config/arm/marvell-whitney.md
new file mode 100644
index 0000000..fffbd29
--- /dev/null
+++ b/gcc/config/arm/marvell-whitney.md
@@ -0,0 +1,678 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+;;
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_attr "whitney_type"
+ "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
+ wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
+ wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
+ wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
+ wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
+ unknown"
+ (cond [
+ (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
+ adc_imm,bfm,branch,call,clz,extend,logic_imm,\
+ logic_reg,logics_imm,logics_reg,logics_shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
+ shift_reg,rev")
+ (const_string "wTP1")
+ (eq_attr "type" "alu_shift_imm,alu_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_inner_shift (insn)")
+ (const_string "wTP2")
+ (const_string "wTP1"))
+ (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
+ mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
+ logic_shift_reg,multiple")
+ (const_string "wTP2")
+ (eq_attr "type" "mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
+ smulxy,umlal,umull")
+ (const_string "wTP3")
+ (eq_attr "type" "sdiv,udiv")
+ (const_string "wTP4")
+ (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
+ (const_string "wTP5")
+ (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
+ neon_load2_all_lanes,neon_load2_all_lanes_q,\
+ neon_load2_2reg_q")
+ (const_string "wTP7")
+ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
+ neon_load3_3reg,neon_load3_3reg_q,\
+ neon_load3_all_lanes,neon_load3_all_lanes_q")
+ (const_string "wTP8")
+ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
+ neon_load4_4reg,neon_load4_4reg_q,\
+ neon_load4_all_lanes,neon_load4_all_lanes_q")
+ (const_string "wTP9")
+ (eq_attr "type" "load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
+ neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
+ (const_string "wTP10")
+ (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
+ neon_load1_2reg,neon_load1_2reg_q,")
+ (const_string "wTP11")
+ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
+ neon_load1_one_lane,neon_load1_one_lane_q,")
+ (const_string "wTP6")
+ (eq_attr "type" "f_stored,f_stores,store1,store2")
+ (const_string "wTP12")
+ (eq_attr "type" "f_stored,neon_store1_3reg,neon_store1_3reg_q,\
+ neon_store1_4reg,neon_store1_4reg_q,\
+ neon_store2_4reg,neon_store2_4reg_q,\
+ neon_store3_3reg,neon_store3_3reg_q,\
+ neon_store3_one_lane,neon_store3_one_lane_q,\
+ neon_store4_4reg,neon_store4_4reg_q,\
+ neon_store4_one_lane,neon_store4_one_lane_q,\
+ store3,store4")
+ (const_string "wTP13")
+ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
+ neon_store1_2reg,neon_store1_2reg_q,\
+ neon_store1_one_lane,neon_store1_one_lane_q,\
+ neon_store2_2reg,neon_store2_2reg_q,\
+ neon_store2_one_lane,neon_store2_one_lane_q")
+ (const_string "wTP14")
+ (eq_attr "type" "fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
+ (const_string "wTP15")
+ (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
+ (const_string "wTP16")
+ (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
+ neon_fp_round_d")
+ (const_string "wTP17")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
+ neon_fp_round_d_q")
+ (const_string "wTP18")
+ (eq_attr "type" "fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
+ neon_fp_recps_s,neon_fp_rsqrts_s")
+ (const_string "wTP19")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
+ neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
+ (const_string "wTP20")
+ (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
+ neon_fp_abs_s,neon_fp_neg_s")
+ (const_string "wTP21")
+ (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
+ (const_string "wTP22")
+ (eq_attr "type" "fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
+ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
+ (const_string "wTP23")
+ (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
+ neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
+ (const_string "wTP24")
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
+ neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
+ (const_string "wTP25")
+ (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
+ neon_int_to_fp_s_q,neon_int_to_fp_d_q")
+ (const_string "wTP26")
+ (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
+ neon_fp_reduc_add_s")
+ (const_string "wTP27")
+ (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
+ neon_fp_reduc_add_s_q")
+ (const_string "wTP28")
+ (eq_attr "type" "fdivs")
+ (const_string "wTP29")
+ (eq_attr "type" "fsqrts")
+ (const_string "wTP30")
+ (eq_attr "type" "fdivd")
+ (const_string "wTP31")
+ (eq_attr "type" "fsqrtd")
+ (const_string "wTP32")
+ (eq_attr "type" "neon_reduc_add_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP33")
+ (const_string "wTP35"))
+ (eq_attr "type" "neon_reduc_add_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP34")
+ (const_string "wTP36"))
+ (eq_attr "type" "neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
+ neon_reduc_add,neon_sub,neon_sub_halve")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP37")
+ (const_string "wTP39"))
+ (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
+ neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP38")
+ (const_string "wTP40"))
+ (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
+ neon_compare,neon_compare_zero,neon_sub_long,\
+ neon_sub_widen,neon_tst")
+ (const_string "wTP37")
+ (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
+ neon_compare_zero_q,neon_tst_q")
+ (const_string "wTP38")
+ (eq_attr "type" "neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
+ (const_string "wTP40")
+ (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
+ neon_tbl4,neon_zip")
+ (const_string "wTP41")
+ (eq_attr "type" "neon_permute_q,neon_zip_q")
+ (const_string "wTP42")
+ (eq_attr "type" "neon_bsl,neon_logic")
+ (const_string "wTP43")
+ (eq_attr "type" "neon_arith_acc,neon_shift_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP43")
+ (const_string "wTP45"))
+ (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP44")
+ (const_string "wTP46"))
+ (eq_attr "type" "neon_logic_q")
+ (const_string "wTP44")
+ (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
+ neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
+ neon_move,neon_reduc_minmax,neon_rev")
+ (const_string "wTP47")
+ (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
+ neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
+ neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
+ neon_rev_q,neon_sat_shift_imm_narrow_q,\
+ neon_shift_imm_narrow_q")
+ (const_string "wTP48")
+ (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
+ neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
+ neon_shift_imm,neon_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP47")
+ (const_string "wTP49"))
+ (eq_attr "type" "neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
+ neon_sat_shift_imm_q,neon_shift_imm_q,\
+ neon_shift_reg_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP48")
+ (const_string "wTP50"))
+ (eq_attr "type" "neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
+ neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
+ (const_string "wTP51")
+ (eq_attr "type" "neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
+ neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
+ neon_sat_mul_b_long,neon_sat_mul_h_long,\
+ neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
+ neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
+ neon_sat_mul_s_scalar_q")
+ (const_string "wTP52")
+ (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
+ neon_mla_s_scalar")
+ (const_string "wTP53")
+ (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
+ neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
+ neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
+ neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
+ neon_sat_mla_b_long,neon_sat_mla_h_long,\
+ neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
+ neon_sat_mla_s_scalar_long")
+ (const_string "wTP54")
+ (eq_attr "type" "f_flag,f_mrc,f_mrrc")
+ (const_string "wTP57")
+ (eq_attr "type" "neon_to_gp,neon_to_gp_q")
+ (const_string "wTP55")
+ (eq_attr "type" "f_mcr,f_mcrr")
+ (const_string "wTP58")
+ (eq_attr "type" "neon_from_gp_q")
+ (const_string "wTP59")
+ (eq_attr "type" "neon_from_gp")
+ (const_string "wTP56")]
+ (const_string "unknown")))
+
+(define_automaton "whitney_pipe")
+
+(define_cpu_unit "wCU1" "whitney_pipe")
+(define_cpu_unit "wCU2" "whitney_pipe")
+(define_cpu_unit "wCU3" "whitney_pipe")
+(define_cpu_unit "wCU4" "whitney_pipe")
+(define_cpu_unit "wCU5" "whitney_pipe")
+(define_cpu_unit "wCU6" "whitney_pipe")
+(define_cpu_unit "wCU7" "whitney_pipe")
+(define_cpu_unit "wCU8" "whitney_pipe")
+(define_cpu_unit "wCU9" "whitney_pipe")
+(define_cpu_unit "wCU10" "whitney_pipe")
+(define_cpu_unit "wCU11" "whitney_pipe")
+(define_cpu_unit "wCU12" "whitney_pipe")
+(define_cpu_unit "wCU13" "whitney_pipe")
+
+(define_insn_reservation "wIR1" 1
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP1"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR2" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP2"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR3" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP3"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU8"
+)
+
+(define_insn_reservation "wIR4" 17
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP4"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU7*8"
+)
+
+(define_insn_reservation "wIR5" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP5"))
+ "(wCU1|wCU2|(wCU3+wCU4)), (wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR6" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP12"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU6"
+)
+
+(define_insn_reservation "wIR7" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP6"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR8" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP7"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR9" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP8"))
+ "(wCU1+wCU3+wCU4+wCU2)*3,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR10" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP9"))
+ "(wCU1+wCU3+wCU4+wCU2)*4,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR11" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP10"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR12" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP11"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR13" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP13"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,wCU6"
+)
+
+(define_insn_reservation "wIR14" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP14"))
+ "wCU1+wCU3+wCU4+wCU2,wCU6"
+)
+
+(define_insn_reservation "wIR15" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP15"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR16" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP16"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR17" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP17"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR18" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP18"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR19" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP19"))
+ "(wCU1+wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR20" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP20"))
+ "(wCU1+wCU2)*2, wCU9"
+)
+
+(define_insn_reservation "wIR21" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP21"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR22" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP22"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR23" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP23"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR24" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP24"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR25" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP25"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR26" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP26"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR27" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP27"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR28" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP28"))
+ "(wCU1+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR29" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP29"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR30" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP30"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR31" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP31"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR32" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP32"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR33" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP33"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR34" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP34"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR35" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP35"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR36" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP36"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR37" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP37"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR38" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP38"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR39" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP39"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR40" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP40"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR41" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP41"))
+ "(wCU1+wCU3+wCU4+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR42" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP42"))
+ "(wCU1+wCU3+wCU4+wCU2)*2, wCU10*3"
+)
+
+(define_insn_reservation "wIR43" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP43"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR44" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP44"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR45" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP45"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR46" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP46"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR47" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP47"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR48" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP48"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR49" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP49"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR50" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP50"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR51" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP51"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR52" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP52"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR53" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP53"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR54" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP54"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR55" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP55"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR56" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP56"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR57" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP57"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR58" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP58"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR59" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP59"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU11*2"
+)
+
+(define_insn_reservation "wIR60" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "unknown"))
+ "wCU13"
+)
+
+(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 5 "wIR22" "wIR41")
+(define_bypass 6 "wIR22" "wIR42")
+(define_bypass 6 "wIR23" "wIR41, wIR42")
+(define_bypass 6 "wIR24" "wIR41")
+(define_bypass 7 "wIR24" "wIR42")
+(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 7 "wIR26" "wIR41")
+(define_bypass 8 "wIR26" "wIR42")
+(define_bypass 6 "wIR27" "wIR41, wIR42")
+(define_bypass 6 "wIR28" "wIR41, wIR42")
+(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 6 "wIR33" "wIR41, wIR42")
+(define_bypass 6 "wIR34" "wIR41")
+(define_bypass 7 "wIR34" "wIR42")
+(define_bypass 6 "wIR35" "wIR41, wIR42")
+(define_bypass 6 "wIR36" "wIR41")
+(define_bypass 7 "wIR36" "wIR42")
+(define_bypass 6 "wIR37" "wIR41, wIR42")
+(define_bypass 6 "wIR38" "wIR41")
+(define_bypass 7 "wIR38" "wIR42")
+(define_bypass 6 "wIR39" "wIR41, wIR42")
+(define_bypass 6 "wIR40" "wIR41")
+(define_bypass 7 "wIR40" "wIR42")
+(define_bypass 6 "wIR41" "wIR41, wIR42")
+(define_bypass 6 "wIR42" "wIR41")
+(define_bypass 7 "wIR42" "wIR42")
+(define_bypass 6 "wIR43" "wIR41, wIR42")
+(define_bypass 6 "wIR44" "wIR41")
+(define_bypass 7 "wIR44" "wIR42")
+(define_bypass 6 "wIR45" "wIR41, wIR42")
+(define_bypass 6 "wIR46" "wIR41")
+(define_bypass 7 "wIR46" "wIR42")
+(define_bypass 6 "wIR47" "wIR41, wIR42")
+(define_bypass 6 "wIR48" "wIR41")
+(define_bypass 7 "wIR48" "wIR42")
+(define_bypass 6 "wIR49" "wIR41, wIR42")
+(define_bypass 6 "wIR50" "wIR41")
+(define_bypass 7 "wIR50" "wIR42")
+(define_bypass 8 "wIR51" "wIR41, wIR42")
+(define_bypass 8 "wIR52" "wIR41")
+(define_bypass 9 "wIR52" "wIR42")
+(define_bypass 8 "wIR53" "wIR41, wIR42")
+(define_bypass 8 "wIR54" "wIR41")
+(define_bypass 9 "wIR54" "wIR42")
+(define_bypass 2 "wIR56" "wIR41, wIR42")
+(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 5 "wIR58" "wIR41, wIR42")
+(define_bypass 5 "wIR59" "wIR41")
+(define_bypass 6 "wIR59" "wIR42")
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index ab5b6e7..4c3402b 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -62,7 +62,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/thumb2.md \
$(srcdir)/config/arm/vec-common.md \
$(srcdir)/config/arm/vfp11.md \
- $(srcdir)/config/arm/vfp.md
+ $(srcdir)/config/arm/vfp.md \
+ $(srcdir)/config/arm/marvell-whitney.md
s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ef4cc75..bc3578d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13006,6 +13006,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
@samp{marvell-pj4},
+@samp{marvell-whitney},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2015-02-25 13:43 ` Xingxing Pan
@ 2015-02-26 8:04 ` Xingxing Pan
2015-02-26 9:59 ` Maxim Kuvyrkov
2015-02-26 10:27 ` Kyrill Tkachov
1 sibling, 1 reply; 13+ messages in thread
From: Xingxing Pan @ 2015-02-26 8:04 UTC (permalink / raw)
To: Kyrill Tkachov, gcc-patches, nickc, Ramana Radhakrishnan,
Richard Earnshaw, James Greenhalgh
Cc: Xinyu Qi, Liping Gao
[-- Attachment #1: Type: text/plain, Size: 212 bytes --]
On 02/25/2015 09:32 PM, Xingxing Pan wrote:
> Hi,
>
> This patch merges pipeline description for marvell-whitney to latest
> code base.
> Is it OK for trunk?
>
Refactor the commit message.
--
Regards,
Xingxing
[-- Attachment #2: 0001-Add-pipeline-description-for-marvell-whitney.patch --]
[-- Type: text/x-patch, Size: 35831 bytes --]
Add pipeline description for marvell-whitney.
2015-02-26 Xingxing Pan <xxingpan@marvell.com>
* config/arm/arm-cores.def: Add new core marvell-whitney.
* config/arm/arm-protos.h:
(marvell_whitney_vector_mode_qi): Declare.
(marvell_whitney_inner_shift): Ditto.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm.c (arm_marvell_whitney_tune): New structure.
(arm_issue_rate): Add marvell_whitney.
(marvell_whitney_vector_mode_qi): New function.
(marvell_whitney_inner_shift): Ditto.
* config/arm/arm.md: Include marvell-whitney.md.
(generic_sched): Add marvell_whitney.
(generic_vfp): Ditto.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
* config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
* config/arm/marvell-whitney.md: New file.
* doc/invoke.texi: Document marvell-whitney.
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index d7e730d..fc76eb5 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e)
+ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
/* V7 big.LITTLE implementations */
ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 307babb..d047dbc 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -231,6 +231,9 @@ extern void arm_order_regs_for_local_alloc (void);
extern int arm_max_conditional_execute ();
+extern bool marvell_whitney_vector_mode_qi (rtx_insn *insn);
+extern bool marvell_whitney_inner_shift (rtx_insn *insn);
+
/* Vectorizer cost model implementation. */
struct cpu_vec_costs {
const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 3450e5b..f0f9f3f 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -298,6 +298,9 @@ EnumValue
Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
EnumValue
+Enum(processor_type) String(marvell-whitney) Value(marvell_whitney)
+
+EnumValue
Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d459f27..fbfab2e 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -31,7 +31,8 @@
cortexa15,cortexa17,cortexr4,
cortexr4f,cortexr5,cortexr7,
cortexm7,cortexm4,cortexm3,
- marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
- cortexa53,cortexa57,cortexa72,
- xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ marvell_pj4,marvell_whitney,cortexa15cortexa7,
+ cortexa17cortexa7,cortexa53,cortexa57,
+ cortexa72,xgene1,cortexa57cortexa53,
+ cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7bf5b4d..e68287f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2000,6 +2000,25 @@ const struct tune_params arm_cortex_a9_tune =
ARM_SCHED_AUTOPREF_OFF /* Sched L2 autopref. */
};
+const struct tune_params arm_marvell_whitney_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa9_extra_costs,
+ cortex_a9_sched_adjust_cost,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_BENEFICIAL(4,32,32),
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ false, /* Prefer Neon for 64-bits bitops. */
+ false, false, /* Prefer 32-bit encodings. */
+ false, /* Prefer Neon for stringops. */
+ 8 /* Maximum insns to inline memset. */
+};
+
const struct tune_params arm_cortex_a12_tune =
{
arm_9e_rtx_costs,
@@ -11717,6 +11736,51 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int * cost)
return true;
}
+/* Return true if vector element size is byte. */
+bool
+marvell_whitney_vector_mode_qi (rtx_insn *insn)
+{
+ machine_mode mode;
+
+ if (GET_CODE (PATTERN (insn)) == SET)
+ {
+ mode = GET_MODE (SET_DEST (PATTERN (insn)));
+ if (VECTOR_MODE_P (mode) && GET_MODE_INNER (mode) == QImode)
+ return true;
+ }
+
+ return false;
+}
+
+/* Return true if a non-shift insn has a shift operand. */
+bool
+marvell_whitney_inner_shift (rtx_insn *insn)
+{
+ rtx pat = PATTERN (insn);
+
+ if (GET_CODE (pat) != SET)
+ return false;
+
+ /* Is not a shift insn. */
+ rtx rvalue = SET_SRC (pat);
+ RTX_CODE code = GET_CODE (rvalue);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return false;
+
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
+ {
+ /* Has shift operation. */
+ RTX_CODE code = GET_CODE (*iter);
+ if (code == ASHIFT || code == ASHIFTRT
+ || code == LSHIFTRT || code == ROTATERT)
+ return true;
+ }
+
+ return false;
+}
+
/* Implement TARGET_REGISTER_MOVE_COST.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
@@ -27154,6 +27218,7 @@ arm_issue_rate (void)
case cortexa15:
case cortexa57:
+ case marvell_whitney:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index c13e9b2..58937ec 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -373,7 +373,7 @@
arm1136jfs,cortexa5,cortexa7,cortexa8,\
cortexa9,cortexa12,cortexa15,cortexa17,\
cortexa53,cortexa57,cortexm4,cortexm7,\
- marvell_pj4,xgene1")
+ marvell_pj4,marvell_whitney,xgene1")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -383,7 +383,7 @@
(and (eq_attr "fpu" "vfp")
(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
cortexa8,cortexa9,cortexa53,cortexm4,\
- cortexm7,marvell_pj4,xgene1")
+ cortexm7,marvell_pj4,marvell_whitney,xgene1")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -414,6 +414,7 @@
(include "cortex-m4-fpu.md")
(include "vfp11.md")
(include "marvell-pj4.md")
+(include "marvell-whitney.md")
(include "xgene1.md")
\f
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c62130d..a64625c 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -68,6 +68,7 @@
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
@@ -102,6 +103,7 @@
|mcpu=cortex-m0.small-multiply \
|mcpu=cortex-m0plus.small-multiply \
|mcpu=marvell-pj4 \
+ |mcpu=marvell-whitney \
|mcpu=generic-armv7-a \
|march=armv7ve \
|march=armv7-m|mcpu=cortex-m3 \
diff --git a/gcc/config/arm/marvell-whitney.md b/gcc/config/arm/marvell-whitney.md
new file mode 100644
index 0000000..fffbd29
--- /dev/null
+++ b/gcc/config/arm/marvell-whitney.md
@@ -0,0 +1,678 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+;;
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_attr "whitney_type"
+ "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
+ wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
+ wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
+ wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
+ wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
+ unknown"
+ (cond [
+ (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
+ adc_imm,bfm,branch,call,clz,extend,logic_imm,\
+ logic_reg,logics_imm,logics_reg,logics_shift_reg,\
+ mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
+ shift_reg,rev")
+ (const_string "wTP1")
+ (eq_attr "type" "alu_shift_imm,alu_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_inner_shift (insn)")
+ (const_string "wTP2")
+ (const_string "wTP1"))
+ (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
+ mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
+ logic_shift_reg,multiple")
+ (const_string "wTP2")
+ (eq_attr "type" "mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
+ smulxy,umlal,umull")
+ (const_string "wTP3")
+ (eq_attr "type" "sdiv,udiv")
+ (const_string "wTP4")
+ (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
+ (const_string "wTP5")
+ (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
+ neon_load2_all_lanes,neon_load2_all_lanes_q,\
+ neon_load2_2reg_q")
+ (const_string "wTP7")
+ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
+ neon_load3_3reg,neon_load3_3reg_q,\
+ neon_load3_all_lanes,neon_load3_all_lanes_q")
+ (const_string "wTP8")
+ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
+ neon_load4_4reg,neon_load4_4reg_q,\
+ neon_load4_all_lanes,neon_load4_all_lanes_q")
+ (const_string "wTP9")
+ (eq_attr "type" "load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
+ neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
+ (const_string "wTP10")
+ (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
+ neon_load1_2reg,neon_load1_2reg_q,")
+ (const_string "wTP11")
+ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
+ neon_load1_one_lane,neon_load1_one_lane_q,")
+ (const_string "wTP6")
+ (eq_attr "type" "f_stored,f_stores,store1,store2")
+ (const_string "wTP12")
+ (eq_attr "type" "f_stored,neon_store1_3reg,neon_store1_3reg_q,\
+ neon_store1_4reg,neon_store1_4reg_q,\
+ neon_store2_4reg,neon_store2_4reg_q,\
+ neon_store3_3reg,neon_store3_3reg_q,\
+ neon_store3_one_lane,neon_store3_one_lane_q,\
+ neon_store4_4reg,neon_store4_4reg_q,\
+ neon_store4_one_lane,neon_store4_one_lane_q,\
+ store3,store4")
+ (const_string "wTP13")
+ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
+ neon_store1_2reg,neon_store1_2reg_q,\
+ neon_store1_one_lane,neon_store1_one_lane_q,\
+ neon_store2_2reg,neon_store2_2reg_q,\
+ neon_store2_one_lane,neon_store2_one_lane_q")
+ (const_string "wTP14")
+ (eq_attr "type" "fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
+ (const_string "wTP15")
+ (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
+ (const_string "wTP16")
+ (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
+ neon_fp_round_d")
+ (const_string "wTP17")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
+ neon_fp_round_d_q")
+ (const_string "wTP18")
+ (eq_attr "type" "fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
+ neon_fp_recps_s,neon_fp_rsqrts_s")
+ (const_string "wTP19")
+ (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
+ neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
+ (const_string "wTP20")
+ (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
+ neon_fp_abs_s,neon_fp_neg_s")
+ (const_string "wTP21")
+ (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
+ (const_string "wTP22")
+ (eq_attr "type" "fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
+ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
+ (const_string "wTP23")
+ (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
+ neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
+ (const_string "wTP24")
+ (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
+ neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
+ (const_string "wTP25")
+ (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
+ neon_int_to_fp_s_q,neon_int_to_fp_d_q")
+ (const_string "wTP26")
+ (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
+ neon_fp_reduc_add_s")
+ (const_string "wTP27")
+ (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
+ neon_fp_reduc_add_s_q")
+ (const_string "wTP28")
+ (eq_attr "type" "fdivs")
+ (const_string "wTP29")
+ (eq_attr "type" "fsqrts")
+ (const_string "wTP30")
+ (eq_attr "type" "fdivd")
+ (const_string "wTP31")
+ (eq_attr "type" "fsqrtd")
+ (const_string "wTP32")
+ (eq_attr "type" "neon_reduc_add_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP33")
+ (const_string "wTP35"))
+ (eq_attr "type" "neon_reduc_add_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP34")
+ (const_string "wTP36"))
+ (eq_attr "type" "neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
+ neon_reduc_add,neon_sub,neon_sub_halve")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP37")
+ (const_string "wTP39"))
+ (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
+ neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP38")
+ (const_string "wTP40"))
+ (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
+ neon_compare,neon_compare_zero,neon_sub_long,\
+ neon_sub_widen,neon_tst")
+ (const_string "wTP37")
+ (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
+ neon_compare_zero_q,neon_tst_q")
+ (const_string "wTP38")
+ (eq_attr "type" "neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
+ (const_string "wTP40")
+ (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
+ neon_tbl4,neon_zip")
+ (const_string "wTP41")
+ (eq_attr "type" "neon_permute_q,neon_zip_q")
+ (const_string "wTP42")
+ (eq_attr "type" "neon_bsl,neon_logic")
+ (const_string "wTP43")
+ (eq_attr "type" "neon_arith_acc,neon_shift_acc")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP43")
+ (const_string "wTP45"))
+ (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP44")
+ (const_string "wTP46"))
+ (eq_attr "type" "neon_logic_q")
+ (const_string "wTP44")
+ (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
+ neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
+ neon_move,neon_reduc_minmax,neon_rev")
+ (const_string "wTP47")
+ (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
+ neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
+ neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
+ neon_rev_q,neon_sat_shift_imm_narrow_q,\
+ neon_shift_imm_narrow_q")
+ (const_string "wTP48")
+ (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
+ neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
+ neon_shift_imm,neon_shift_reg")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP47")
+ (const_string "wTP49"))
+ (eq_attr "type" "neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
+ neon_sat_shift_imm_q,neon_shift_imm_q,\
+ neon_shift_reg_q")
+ (if_then_else (match_test
+ "marvell_whitney_vector_mode_qi (insn)")
+ (const_string "wTP48")
+ (const_string "wTP50"))
+ (eq_attr "type" "neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
+ neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
+ (const_string "wTP51")
+ (eq_attr "type" "neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
+ neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
+ neon_sat_mul_b_long,neon_sat_mul_h_long,\
+ neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
+ neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
+ neon_sat_mul_s_scalar_q")
+ (const_string "wTP52")
+ (eq_attr "type" "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
+ neon_mla_s_scalar")
+ (const_string "wTP53")
+ (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
+ neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
+ neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
+ neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
+ neon_sat_mla_b_long,neon_sat_mla_h_long,\
+ neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
+ neon_sat_mla_s_scalar_long")
+ (const_string "wTP54")
+ (eq_attr "type" "f_flag,f_mrc,f_mrrc")
+ (const_string "wTP57")
+ (eq_attr "type" "neon_to_gp,neon_to_gp_q")
+ (const_string "wTP55")
+ (eq_attr "type" "f_mcr,f_mcrr")
+ (const_string "wTP58")
+ (eq_attr "type" "neon_from_gp_q")
+ (const_string "wTP59")
+ (eq_attr "type" "neon_from_gp")
+ (const_string "wTP56")]
+ (const_string "unknown")))
+
+(define_automaton "whitney_pipe")
+
+(define_cpu_unit "wCU1" "whitney_pipe")
+(define_cpu_unit "wCU2" "whitney_pipe")
+(define_cpu_unit "wCU3" "whitney_pipe")
+(define_cpu_unit "wCU4" "whitney_pipe")
+(define_cpu_unit "wCU5" "whitney_pipe")
+(define_cpu_unit "wCU6" "whitney_pipe")
+(define_cpu_unit "wCU7" "whitney_pipe")
+(define_cpu_unit "wCU8" "whitney_pipe")
+(define_cpu_unit "wCU9" "whitney_pipe")
+(define_cpu_unit "wCU10" "whitney_pipe")
+(define_cpu_unit "wCU11" "whitney_pipe")
+(define_cpu_unit "wCU12" "whitney_pipe")
+(define_cpu_unit "wCU13" "whitney_pipe")
+
+(define_insn_reservation "wIR1" 1
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP1"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR2" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP2"))
+ "wCU1|wCU2|(wCU3+wCU4)"
+)
+
+(define_insn_reservation "wIR3" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP3"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU8"
+)
+
+(define_insn_reservation "wIR4" 17
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP4"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU7*8"
+)
+
+(define_insn_reservation "wIR5" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP5"))
+ "(wCU1|wCU2|(wCU3+wCU4)), (wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR6" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP12"))
+ "(wCU1|wCU2|(wCU3+wCU4)), wCU6"
+)
+
+(define_insn_reservation "wIR7" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP6"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR8" 8
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP7"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR9" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP8"))
+ "(wCU1+wCU3+wCU4+wCU2)*3,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR10" 9
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP9"))
+ "(wCU1+wCU3+wCU4+wCU2)*4,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR11" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP10"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR12" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP11"))
+ "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
+)
+
+(define_insn_reservation "wIR13" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP13"))
+ "(wCU1+wCU3+wCU4+wCU2)*2,wCU6"
+)
+
+(define_insn_reservation "wIR14" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP14"))
+ "wCU1+wCU3+wCU4+wCU2,wCU6"
+)
+
+(define_insn_reservation "wIR15" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP15"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR16" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP16"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR17" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP17"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR18" 6
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP18"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR19" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP19"))
+ "(wCU1+wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR20" 10
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP20"))
+ "(wCU1+wCU2)*2, wCU9"
+)
+
+(define_insn_reservation "wIR21" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP21"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR22" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP22"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR23" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP23"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR24" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP24"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR25" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP25"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR26" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP26"))
+ "(wCU1+wCU2), wCU11*2"
+)
+
+(define_insn_reservation "wIR27" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP27"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR28" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP28"))
+ "(wCU1+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR29" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP29"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR30" 16
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP30"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR31" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP31"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR32" 26
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP32"))
+ "(wCU1|wCU2), wCU9, wCU12*8"
+)
+
+(define_insn_reservation "wIR33" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP33"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR34" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP34"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR35" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP35"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
+)
+
+(define_insn_reservation "wIR36" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP36"))
+ "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR37" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP37"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR38" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP38"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR39" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP39"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR40" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP40"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR41" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP41"))
+ "(wCU1+wCU3+wCU4+wCU2), wCU10*2"
+)
+
+(define_insn_reservation "wIR42" 4
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP42"))
+ "(wCU1+wCU3+wCU4+wCU2)*2, wCU10*3"
+)
+
+(define_insn_reservation "wIR43" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP43"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR44" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP44"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR45" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP45"))
+ "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
+)
+
+(define_insn_reservation "wIR46" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP46"))
+ "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR47" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP47"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR48" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP48"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR49" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP49"))
+ "(wCU1|wCU2), wCU10"
+)
+
+(define_insn_reservation "wIR50" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP50"))
+ "(wCU1+wCU2), (wCU10+wCU11)"
+)
+
+(define_insn_reservation "wIR51" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP51"))
+ "(wCU1|wCU2), wCU9"
+)
+
+(define_insn_reservation "wIR52" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP52"))
+ "(wCU1+wCU2), wCU9*2"
+)
+
+(define_insn_reservation "wIR53" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP53"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
+)
+
+(define_insn_reservation "wIR54" 5
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP54"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
+)
+
+(define_insn_reservation "wIR55" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP55"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR56" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP56"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR57" 3
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP57"))
+ "(wCU1|wCU2), wCU11"
+)
+
+(define_insn_reservation "wIR58" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP58"))
+ "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
+)
+
+(define_insn_reservation "wIR59" 2
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "wTP59"))
+ "(wCU1+wCU3+wCU2+wCU4), wCU11*2"
+)
+
+(define_insn_reservation "wIR60" 0
+ (and (eq_attr "tune" "marvell_whitney")
+ (eq_attr "whitney_type" "unknown"))
+ "wCU13"
+)
+
+(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
+(define_bypass 5 "wIR22" "wIR41")
+(define_bypass 6 "wIR22" "wIR42")
+(define_bypass 6 "wIR23" "wIR41, wIR42")
+(define_bypass 6 "wIR24" "wIR41")
+(define_bypass 7 "wIR24" "wIR42")
+(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 7 "wIR26" "wIR41")
+(define_bypass 8 "wIR26" "wIR42")
+(define_bypass 6 "wIR27" "wIR41, wIR42")
+(define_bypass 6 "wIR28" "wIR41, wIR42")
+(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
+(define_bypass 6 "wIR33" "wIR41, wIR42")
+(define_bypass 6 "wIR34" "wIR41")
+(define_bypass 7 "wIR34" "wIR42")
+(define_bypass 6 "wIR35" "wIR41, wIR42")
+(define_bypass 6 "wIR36" "wIR41")
+(define_bypass 7 "wIR36" "wIR42")
+(define_bypass 6 "wIR37" "wIR41, wIR42")
+(define_bypass 6 "wIR38" "wIR41")
+(define_bypass 7 "wIR38" "wIR42")
+(define_bypass 6 "wIR39" "wIR41, wIR42")
+(define_bypass 6 "wIR40" "wIR41")
+(define_bypass 7 "wIR40" "wIR42")
+(define_bypass 6 "wIR41" "wIR41, wIR42")
+(define_bypass 6 "wIR42" "wIR41")
+(define_bypass 7 "wIR42" "wIR42")
+(define_bypass 6 "wIR43" "wIR41, wIR42")
+(define_bypass 6 "wIR44" "wIR41")
+(define_bypass 7 "wIR44" "wIR42")
+(define_bypass 6 "wIR45" "wIR41, wIR42")
+(define_bypass 6 "wIR46" "wIR41")
+(define_bypass 7 "wIR46" "wIR42")
+(define_bypass 6 "wIR47" "wIR41, wIR42")
+(define_bypass 6 "wIR48" "wIR41")
+(define_bypass 7 "wIR48" "wIR42")
+(define_bypass 6 "wIR49" "wIR41, wIR42")
+(define_bypass 6 "wIR50" "wIR41")
+(define_bypass 7 "wIR50" "wIR42")
+(define_bypass 8 "wIR51" "wIR41, wIR42")
+(define_bypass 8 "wIR52" "wIR41")
+(define_bypass 9 "wIR52" "wIR42")
+(define_bypass 8 "wIR53" "wIR41, wIR42")
+(define_bypass 8 "wIR54" "wIR41")
+(define_bypass 9 "wIR54" "wIR42")
+(define_bypass 2 "wIR56" "wIR41, wIR42")
+(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
+(define_bypass 5 "wIR58" "wIR41, wIR42")
+(define_bypass 5 "wIR59" "wIR41")
+(define_bypass 6 "wIR59" "wIR42")
diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index ab5b6e7..4c3402b 100644
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -62,7 +62,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
$(srcdir)/config/arm/thumb2.md \
$(srcdir)/config/arm/vec-common.md \
$(srcdir)/config/arm/vfp11.md \
- $(srcdir)/config/arm/vfp.md
+ $(srcdir)/config/arm/vfp.md \
+ $(srcdir)/config/arm/marvell-whitney.md
s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ef4cc75..bc3578d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13006,6 +13006,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
@samp{marvell-pj4},
+@samp{marvell-whitney},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
--
1.7.9.5
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2015-02-26 8:04 ` Xingxing Pan
@ 2015-02-26 9:59 ` Maxim Kuvyrkov
0 siblings, 0 replies; 13+ messages in thread
From: Maxim Kuvyrkov @ 2015-02-26 9:59 UTC (permalink / raw)
To: Xingxing Pan
Cc: Kyrill Tkachov, gcc-patches, Nick Clifton, Ramana Radhakrishnan,
Richard Earnshaw, James Greenhalgh, Xinyu Qi, Liping Gao
> On Feb 26, 2015, at 10:36 AM, Xingxing Pan <xxingpan@marvell.com> wrote:
>
> On 02/25/2015 09:32 PM, Xingxing Pan wrote:
>> Hi,
>>
>> This patch merges pipeline description for marvell-whitney to latest
>> code base.
>> Is it OK for trunk?
>>
> Refactor the commit message.
>
...
> Add pipeline description for marvell-whitney.
>
> 2015-02-26 Xingxing Pan <xxingpan@marvell.com>
>
> * config/arm/arm-cores.def: Add new core marvell-whitney.
> * config/arm/arm-protos.h:
> (marvell_whitney_vector_mode_qi): Declare.
> (marvell_whitney_inner_shift): Ditto.
> * config/arm/arm-tables.opt: Regenerated.
> * config/arm/arm-tune.md: Regenerated.
> * config/arm/arm.c (arm_marvell_whitney_tune): New structure.
> (arm_issue_rate): Add marvell_whitney.
> (marvell_whitney_vector_mode_qi): New function.
> (marvell_whitney_inner_shift): Ditto.
> * config/arm/arm.md: Include marvell-whitney.md.
> (generic_sched): Add marvell_whitney.
> (generic_vfp): Ditto.
> * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
> * config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
> * config/arm/marvell-whitney.md: New file.
> * doc/invoke.texi: Document marvell-whitney.
>
...
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 7bf5b4d..e68287f 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -2000,6 +2000,25 @@ const struct tune_params arm_cortex_a9_tune =
> ARM_SCHED_AUTOPREF_OFF /* Sched L2 autopref. */
> };
>
> +const struct tune_params arm_marvell_whitney_tune =
> +{
> + arm_9e_rtx_costs,
> + &cortexa9_extra_costs,
> + cortex_a9_sched_adjust_cost,
> + 1, /* Constant limit. */
> + 5, /* Max cond insns. */
> + ARM_PREFETCH_BENEFICIAL(4,32,32),
> + false, /* Prefer constant pool. */
> + arm_default_branch_cost,
> + false, /* Prefer LDRD/STRD. */
> + {true, true}, /* Prefer non short circuit. */
> + &arm_default_vec_cost, /* Vectorizer costs. */
> + false, /* Prefer Neon for 64-bits bitops. */
> + false, false, /* Prefer 32-bit encodings. */
> + false, /* Prefer Neon for stringops. */
> + 8 /* Maximum insns to inline memset. */
> +};
> +
You need to bootstrap GCC with your patch applied. As it is now, the above tune table is missing at least two entries (one for insn fusing, and one for sched L2 autoprefetcher). It should cause a bootstrap fail.
> const struct tune_params arm_cortex_a12_tune =
> {
> arm_9e_rtx_costs,
> @@ -11717,6 +11736,51 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep, int * cost)
> return true;
> }
>
> +/* Return true if vector element size is byte. */
> +bool
> +marvell_whitney_vector_mode_qi (rtx_insn *insn)
> +{
> + machine_mode mode;
> +
> + if (GET_CODE (PATTERN (insn)) == SET)
> + {
> + mode = GET_MODE (SET_DEST (PATTERN (insn)));
> + if (VECTOR_MODE_P (mode) && GET_MODE_INNER (mode) == QImode)
> + return true;
> + }
> +
> + return false;
> +}
It is preferable to avoid using predicates in DFA definitions. Predicates prevent optimizations of the DFA, which causes them to be bigger and slower. This predicate can be easily replaced by an attribute (set_attr "dest_vect_mode" "<mode>") on affected instructions (the proper name for the attribute needs some thinking though).
That said, I don't a have strong opinion on this case. It may be a worthwhile tradeoff to use the predicate to avoid adding new attribute to a dozen of instructions. If you / other reviewers prefer to keep the predicate -- please add a comment noting that it is used by the DFA.
> +
> +/* Return true if a non-shift insn has a shift operand. */
> +bool
> +marvell_whitney_inner_shift (rtx_insn *insn)
> +{
> + rtx pat = PATTERN (insn);
> +
> + if (GET_CODE (pat) != SET)
> + return false;
> +
> + /* Is not a shift insn. */
> + rtx rvalue = SET_SRC (pat);
> + RTX_CODE code = GET_CODE (rvalue);
> + if (code == ASHIFT || code == ASHIFTRT
> + || code == LSHIFTRT || code == ROTATERT)
> + return false;
> +
> + subrtx_iterator::array_type array;
> + FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
> + {
> + /* Has shift operation. */
> + RTX_CODE code = GET_CODE (*iter);
> + if (code == ASHIFT || code == ASHIFTRT
> + || code == LSHIFTRT || code == ROTATERT)
> + return true;
> + }
> +
> + return false;
> +}
Same comment as above.
Otherwise looks good.
Thanks!
--
Maxim Kuvyrkov
www.linaro.org
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2014-12-18 10:21 [patch 1/2][ARM]: New CPU support for Marvell Whitney Xingxing Pan
2014-12-19 10:37 ` Kyrill Tkachov
2014-12-19 10:59 ` Kyrill Tkachov
@ 2015-02-26 10:12 ` Ramana Radhakrishnan
2 siblings, 0 replies; 13+ messages in thread
From: Ramana Radhakrishnan @ 2015-02-26 10:12 UTC (permalink / raw)
To: Xingxing Pan
Cc: gcc-patches, Ramana Radhakrishnan, Richard Earnshaw, Xinyu Qi, lgao1
On Thu, Dec 18, 2014 at 10:13 AM, Xingxing Pan <xxingpan@marvell.com> wrote:
> Hi,
>
> This patch contains Marvell Whitney core's pipeline description.
> Test on arm-linux-gnueabi and no new regression are found.
>
> Is it OK for trunk?
I haven't had a chance to review this in detail but I think it's too
late to add such an invasive patch to the backend given we are in
stage4 today.
Ramana
>
> Regards,
> Xingxing
>
>
> 2014-12-18 Xingxing Pan <xxingpan@marvell.com>
>
> * config/arm/arm-cores.def: Add new core marvell-whitney.
> * config/arm/arm-protos.h:
> (marvell_whitney_vector_element_size_is_byte): Declare.
> (marvell_whitney_non_shift_with_shift_operand): Ditto.
> * config/arm/arm-tables.opt: Regenerated.
> * config/arm/arm-tune.md: Regenerated.
> * config/arm/arm.c (arm_marvell_whitney_tune): New structure.
> (arm_issue_rate): Add marvell_whitney.
> (marvell_whitney_vector_element_size_is_byte): New function.
> (marvell_whitney_non_shift_with_shift_operand): Ditto.
> * config/arm/arm.md: Include marvell-whitney.md.
> (generic_sched): Add marvell_whitney.
> (generic_vfp): Ditto.
> * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell-whitney.
> * config/arm/t-arm (MD_INCLUDES): Add marvell-whitney.md.
> * config/arm/marvell-whitney.md: New file.
> * doc/invoke.texi: Document marvell-whitney.
>
> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
> index 423ee9e..b0ffbe1 100644
> --- a/gcc/config/arm/arm-cores.def
> +++ b/gcc/config/arm/arm-cores.def
> @@ -159,6 +159,7 @@ ARM_CORE("cortex-m7", cortexm7, cortexm7,
> 7EM,
> FL_LDSCHED, cortex_m7)
> ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM,
> FL_LDSCHED, v7m)
> ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M,
> FL_LDSCHED, v7m)
> ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A,
> FL_LDSCHED, 9e)
> +ARM_CORE("marvell-whitney", marvell_whitney, marvell_whitney,
> 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, marvell_whitney)
>
> /* V7 big.LITTLE implementations */
> ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A,
> FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
> index 20cfa9f..e86db1e 100644
> --- a/gcc/config/arm/arm-protos.h
> +++ b/gcc/config/arm/arm-protos.h
> @@ -231,6 +231,9 @@ extern void arm_order_regs_for_local_alloc (void);
>
> extern int arm_max_conditional_execute ();
>
> +extern bool marvell_whitney_vector_element_size_is_byte (rtx insn);
> +extern bool marvell_whitney_non_shift_with_shift_operand (rtx insn);
> +
> /* Vectorizer cost model implementation. */
> struct cpu_vec_costs {
> const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
> diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
> index 9b1886e..3371ce3 100644
> --- a/gcc/config/arm/arm-tables.opt
> +++ b/gcc/config/arm/arm-tables.opt
> @@ -298,6 +298,9 @@ EnumValue
> Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
>
> EnumValue
> +Enum(processor_type) String(marvell-whitney) Value(marvell_whitney)
> +
> +EnumValue
> Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
>
> EnumValue
> diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
> index d300c51..c73c33c 100644
> --- a/gcc/config/arm/arm-tune.md
> +++ b/gcc/config/arm/arm-tune.md
> @@ -28,9 +28,10 @@
>
> cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
> genericv7a,cortexa5,cortexa7,
> cortexa8,cortexa9,cortexa12,
> - cortexa15,cortexa17,cortexr4,cortexr4f,
> - cortexr5,cortexr7,cortexm7,
> - cortexm4,cortexm3,marvell_pj4,
> - cortexa15cortexa7,cortexa17cortexa7,cortexa53,
> - cortexa57,cortexa57cortexa53"
> + cortexa15,cortexa17,cortexr4,
> + cortexr4f,cortexr5,cortexr7,
> + cortexm7,cortexm4,cortexm3,
> + marvell_pj4,marvell_whitney,cortexa15cortexa7,
> + cortexa17cortexa7,cortexa53,cortexa57,
> + cortexa57cortexa53"
> (const (symbol_ref "((enum attr_tune) arm_tune)")))
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 0ec526b..183da4c 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -1914,6 +1914,25 @@ const struct tune_params arm_cortex_a9_tune =
> 8 /* Maximum insns to inline
> memset. */
> };
>
> +const struct tune_params arm_marvell_whitney_tune =
> +{
> + arm_9e_rtx_costs,
> + &cortexa9_extra_costs,
> + cortex_a9_sched_adjust_cost,
> + 1, /* Constant limit. */
> + 5, /* Max cond insns. */
> + ARM_PREFETCH_BENEFICIAL(4,32,32),
> + false, /* Prefer constant pool. */
> + arm_default_branch_cost,
> + false, /* Prefer LDRD/STRD. */
> + {true, true}, /* Prefer non short
> circuit. */
> + &arm_default_vec_cost, /* Vectorizer costs. */
> + false, /* Prefer Neon for
> 64-bits bitops. */
> + false, false, /* Prefer 32-bit
> encodings. */
> + false, /* Prefer Neon for
> stringops. */
> + 8 /* Maximum insns to inline
> memset. */
> +};
> +
> const struct tune_params arm_cortex_a12_tune =
> {
> arm_9e_rtx_costs,
> @@ -11608,6 +11627,49 @@ fa726te_sched_adjust_cost (rtx_insn *insn, rtx
> link, rtx_insn *dep, int * cost)
> return true;
> }
>
> +/* Return true if vector element size is byte. */
> +bool
> +marvell_whitney_vector_element_size_is_byte (rtx insn)
> +{
> + if (GET_CODE (PATTERN (insn)) == SET)
> + {
> + if ((GET_MODE (SET_DEST (PATTERN (insn))) == V8QImode) ||
> + (GET_MODE (SET_DEST (PATTERN (insn))) == V16QImode))
> + return true;
> + }
> +
> + return false;
> +}
> +
> +/* Return true if INSN has shift operation but is not a shift insn. */
> +bool
> +marvell_whitney_non_shift_with_shift_operand (rtx insn)
> +{
> + rtx pat = PATTERN (insn);
> +
> + if (GET_CODE (pat) != SET)
> + return false;
> +
> + /* Is not a shift insn. */
> + rtx rvalue = SET_SRC (pat);
> + RTX_CODE code = GET_CODE (rvalue);
> + if (code == ASHIFT || code == ASHIFTRT
> + || code == LSHIFTRT || code == ROTATERT)
> + return false;
> +
> + subrtx_iterator::array_type array;
> + FOR_EACH_SUBRTX (iter, array, rvalue, ALL)
> + {
> + /* Has shift operation. */
> + RTX_CODE code = GET_CODE (*iter);
> + if (code == ASHIFT || code == ASHIFTRT
> + || code == LSHIFTRT || code == ROTATERT)
> + return true;
> + }
> +
> + return false;
> +}
> +
> /* Implement TARGET_REGISTER_MOVE_COST.
>
> Moves between VFP_REGS and GENERAL_REGS are a single insn, but
> @@ -27031,6 +27093,7 @@ arm_issue_rate (void)
> {
> case cortexa15:
> case cortexa57:
> + case marvell_whitney:
> return 3;
>
> case cortexm7:
> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> index 822760b..8f02743 100644
> --- a/gcc/config/arm/arm.md
> +++ b/gcc/config/arm/arm.md
> @@ -386,7 +386,8 @@
> arm926ejs,arm1020e,arm1026ejs,arm1136js,\
> arm1136jfs,cortexa5,cortexa7,cortexa8,\
> cortexa9,cortexa12,cortexa15,cortexa17,\
> - cortexa53,cortexm4,cortexm7,marvell_pj4")
> + cortexa53,cortexm4,cortexm7,marvell_pj4,\
> + marvell_whitney")
> (eq_attr "tune_cortexr4" "yes"))
> (const_string "no")
> (const_string "yes"))))
> @@ -396,7 +397,7 @@
> (and (eq_attr "fpu" "vfp")
> (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
> cortexa8,cortexa9,cortexa53,cortexm4,\
> - cortexm7,marvell_pj4")
> + cortexm7,marvell_pj4,marvell_whitney")
> (eq_attr "tune_cortexr4" "no"))
> (const_string "yes")
> (const_string "no"))))
> @@ -426,6 +427,7 @@
> (include "cortex-m4-fpu.md")
> (include "vfp11.md")
> (include "marvell-pj4.md")
> +(include "marvell-whitney.md")
>
>
>
> ;;---------------------------------------------------------------------------
> diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
> index aa93aa4..07fab0f 100644
> --- a/gcc/config/arm/bpabi.h
> +++ b/gcc/config/arm/bpabi.h
> @@ -68,6 +68,7 @@
> |mcpu=cortex-a15.cortex-a7 \
> |mcpu=cortex-a17.cortex-a7 \
> |mcpu=marvell-pj4 \
> + |mcpu=marvell-whitney \
> |mcpu=cortex-a53 \
> |mcpu=cortex-a57 \
> |mcpu=cortex-a57.cortex-a53 \
> @@ -96,6 +97,7 @@
> |mcpu=cortex-m0.small-multiply \
> |mcpu=cortex-m0plus.small-multiply \
> |mcpu=marvell-pj4 \
> + |mcpu=marvell-whitney \
> |mcpu=generic-armv7-a \
> |march=armv7ve \
> |march=armv7-m|mcpu=cortex-m3 \
> diff --git a/gcc/config/arm/marvell-whitney.md
> b/gcc/config/arm/marvell-whitney.md
> new file mode 100644
> index 0000000..57391a7
> --- /dev/null
> +++ b/gcc/config/arm/marvell-whitney.md
> @@ -0,0 +1,683 @@
> +;; Marvell ARM Processor Pipeline Description
> +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
> +;;
> +;; Contributed by Marvell.
> +
> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it
> +;; under the terms of the GNU General Public License as published
> +;; by the Free Software Foundation; either version 3, or (at your
> +;; option) any later version.
> +;;
> +;; GCC is distributed in the hope that it will be useful, but WITHOUT
> +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
> +;; License for more details.
> +;;
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3. If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +(define_attr "whitney_type"
> + "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
> +
> wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
> +
> wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
> +
> wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
> + wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
> + unknown"
> + (cond [
> + (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
> + adc_imm,bfm,branch,call,clz,extend,logic_imm,\
> +
> logic_reg,logics_imm,logics_reg,logics_shift_reg,\
> + mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
> + shift_reg,rev")
> + (const_string "wTP1")
> + (eq_attr "type" "alu_shift_imm,alu_shift_reg")
> + (if_then_else (match_test
> + "marvell_whitney_non_shift_with_shift_operand
> (insn)")
> + (const_string "wTP2")
> + (const_string "wTP1"))
> + (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
> +
> mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
> + logic_shift_reg,multiple")
> + (const_string "wTP2")
> + (eq_attr "type" "mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
> + smulxy,umlal,umull")
> + (const_string "wTP3")
> + (eq_attr "type" "sdiv,udiv")
> + (const_string "wTP4")
> + (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
> + (const_string "wTP5")
> + (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
> + neon_load2_all_lanes,neon_load2_all_lanes_q,\
> + neon_load2_2reg_q")
> + (const_string "wTP7")
> + (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
> + neon_load3_3reg,neon_load3_3reg_q,\
> + neon_load3_all_lanes,neon_load3_all_lanes_q")
> + (const_string "wTP8")
> + (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
> + neon_load4_4reg,neon_load4_4reg_q,\
> + neon_load4_all_lanes,neon_load4_all_lanes_q")
> + (const_string "wTP9")
> + (eq_attr "type" "load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
> +
> neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
> + (const_string "wTP10")
> + (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
> + neon_load1_2reg,neon_load1_2reg_q,")
> + (const_string "wTP11")
> + (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
> + neon_load1_one_lane,neon_load1_one_lane_q,")
> + (const_string "wTP6")
> + (eq_attr "type" "f_stored,f_stores,store1,store2")
> + (const_string "wTP12")
> + (eq_attr "type" "f_stored,neon_store1_3reg,neon_store1_3reg_q,\
> + neon_store1_4reg,neon_store1_4reg_q,\
> + neon_store2_4reg,neon_store2_4reg_q,\
> + neon_store3_3reg,neon_store3_3reg_q,\
> + neon_store3_one_lane,neon_store3_one_lane_q,\
> + neon_store4_4reg,neon_store4_4reg_q,\
> + neon_store4_one_lane,neon_store4_one_lane_q,\
> + store3,store4")
> + (const_string "wTP13")
> + (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
> + neon_store1_2reg,neon_store1_2reg_q,\
> + neon_store1_one_lane,neon_store1_one_lane_q,\
> + neon_store2_2reg,neon_store2_2reg_q,\
> + neon_store2_one_lane,neon_store2_one_lane_q")
> + (const_string "wTP14")
> + (eq_attr "type" "fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
> + (const_string "wTP15")
> + (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
> + (const_string "wTP16")
> + (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
> + neon_fp_round_d")
> + (const_string "wTP17")
> + (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
> + neon_fp_round_d_q")
> + (const_string "wTP18")
> + (eq_attr "type" "fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
> + neon_fp_recps_s,neon_fp_rsqrts_s")
> + (const_string "wTP19")
> + (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
> + neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
> + (const_string "wTP20")
> + (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
> + neon_fp_abs_s,neon_fp_neg_s")
> + (const_string "wTP21")
> + (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
> + (const_string "wTP22")
> + (eq_attr "type" "fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
> + neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
> + (const_string "wTP23")
> + (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
> +
> neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
> + (const_string "wTP24")
> + (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
> +
> neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
> + (const_string "wTP25")
> + (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
> + neon_int_to_fp_s_q,neon_int_to_fp_d_q")
> + (const_string "wTP26")
> + (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
> + neon_fp_reduc_add_s")
> + (const_string "wTP27")
> + (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
> + neon_fp_reduc_add_s_q")
> + (const_string "wTP28")
> + (eq_attr "type" "fdivs")
> + (const_string "wTP29")
> + (eq_attr "type" "fsqrts")
> + (const_string "wTP30")
> + (eq_attr "type" "fdivd")
> + (const_string "wTP31")
> + (eq_attr "type" "fsqrtd")
> + (const_string "wTP32")
> + (eq_attr "type" "neon_reduc_add_acc")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP33")
> + (const_string "wTP35"))
> + (eq_attr "type" "neon_reduc_add_acc_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP34")
> + (const_string "wTP36"))
> + (eq_attr "type"
> "neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
> + neon_reduc_add,neon_sub,neon_sub_halve")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP37")
> + (const_string "wTP39"))
> + (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
> + neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP38")
> + (const_string "wTP40"))
> + (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
> + neon_compare,neon_compare_zero,neon_sub_long,\
> + neon_sub_widen,neon_tst")
> + (const_string "wTP37")
> + (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
> + neon_compare_zero_q,neon_tst_q")
> + (const_string "wTP38")
> + (eq_attr "type"
> "neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
> + (const_string "wTP40")
> + (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
> + neon_tbl4,neon_zip")
> + (const_string "wTP41")
> + (eq_attr "type" "neon_permute_q,neon_zip_q")
> + (const_string "wTP42")
> + (eq_attr "type" "neon_bsl,neon_logic")
> + (const_string "wTP43")
> + (eq_attr "type" "neon_arith_acc,neon_shift_acc")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP43")
> + (const_string "wTP45"))
> + (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP44")
> + (const_string "wTP46"))
> + (eq_attr "type" "neon_logic_q")
> + (const_string "wTP44")
> + (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
> + neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
> + neon_move,neon_reduc_minmax,neon_rev")
> + (const_string "wTP47")
> + (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
> +
> neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
> +
> neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
> + neon_rev_q,neon_sat_shift_imm_narrow_q,\
> + neon_shift_imm_narrow_q")
> + (const_string "wTP48")
> + (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
> +
> neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
> + neon_shift_imm,neon_shift_reg")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP47")
> + (const_string "wTP49"))
> + (eq_attr "type" "neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
> + neon_sat_shift_imm_q,neon_shift_imm_q,\
> + neon_shift_reg_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_element_size_is_byte
> (insn)")
> + (const_string "wTP48")
> + (const_string "wTP50"))
> + (eq_attr "type"
> "neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
> + neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
> + (const_string "wTP51")
> + (eq_attr "type"
> "neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
> + neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
> + neon_sat_mul_b_long,neon_sat_mul_h_long,\
> + neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
> +
> neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
> + neon_sat_mul_s_scalar_q")
> + (const_string "wTP52")
> + (eq_attr "type"
> "neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
> + neon_mla_s_scalar")
> + (const_string "wTP53")
> + (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
> + neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
> +
> neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
> + neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
> + neon_sat_mla_b_long,neon_sat_mla_h_long,\
> + neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
> + neon_sat_mla_s_scalar_long")
> + (const_string "wTP54")
> + (eq_attr "type" "f_flag,f_mrc,f_mrrc")
> + (const_string "wTP57")
> + (eq_attr "type" "neon_to_gp,neon_to_gp_q")
> + (const_string "wTP55")
> + (eq_attr "type" "f_mcr,f_mcrr")
> + (const_string "wTP58")
> + (eq_attr "type" "neon_from_gp_q")
> + (const_string "wTP59")
> + (eq_attr "type" "neon_from_gp")
> + (const_string "wTP56")]
> + (const_string "unknown")))
> +
> +(define_attr "tune_marvell_whitney" "yes,no"
> + (const (if_then_else (eq_attr "tune" "marvell_whitney")
> + (const_string "yes")
> + (const_string "no"))))
> +
> +(define_automaton "whitney_pipe")
> +
> +(define_cpu_unit "wCU1" "whitney_pipe")
> +(define_cpu_unit "wCU2" "whitney_pipe")
> +(define_cpu_unit "wCU3" "whitney_pipe")
> +(define_cpu_unit "wCU4" "whitney_pipe")
> +(define_cpu_unit "wCU5" "whitney_pipe")
> +(define_cpu_unit "wCU6" "whitney_pipe")
> +(define_cpu_unit "wCU7" "whitney_pipe")
> +(define_cpu_unit "wCU8" "whitney_pipe")
> +(define_cpu_unit "wCU9" "whitney_pipe")
> +(define_cpu_unit "wCU10" "whitney_pipe")
> +(define_cpu_unit "wCU11" "whitney_pipe")
> +(define_cpu_unit "wCU12" "whitney_pipe")
> +(define_cpu_unit "wCU13" "whitney_pipe")
> +
> +(define_insn_reservation "wIR1" 1
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP1"))
> + "wCU1|wCU2|(wCU3+wCU4)"
> +)
> +
> +(define_insn_reservation "wIR2" 2
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP2"))
> + "wCU1|wCU2|(wCU3+wCU4)"
> +)
> +
> +(define_insn_reservation "wIR3" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP3"))
> + "(wCU1|wCU2|(wCU3+wCU4)), wCU8"
> +)
> +
> +(define_insn_reservation "wIR4" 17
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP4"))
> + "(wCU1|wCU2|(wCU3+wCU4)), wCU7*8"
> +)
> +
> +(define_insn_reservation "wIR5" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP5"))
> + "(wCU1|wCU2|(wCU3+wCU4)), (wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR6" 0
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP12"))
> + "(wCU1|wCU2|(wCU3+wCU4)), wCU6"
> +)
> +
> +(define_insn_reservation "wIR7" 8
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP6"))
> + "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR8" 8
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP7"))
> + "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR9" 9
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP8"))
> + "(wCU1+wCU3+wCU4+wCU2)*3,(wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR10" 9
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP9"))
> + "(wCU1+wCU3+wCU4+wCU2)*4,(wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR11" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP10"))
> + "(wCU1+wCU3+wCU4+wCU2)*2,(wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR12" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP11"))
> + "wCU1+wCU3+wCU4+wCU2,(wCU5|wCU6)"
> +)
> +
> +(define_insn_reservation "wIR13" 0
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP13"))
> + "(wCU1+wCU3+wCU4+wCU2)*2,wCU6"
> +)
> +
> +(define_insn_reservation "wIR14" 0
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP14"))
> + "wCU1+wCU3+wCU4+wCU2,wCU6"
> +)
> +
> +(define_insn_reservation "wIR15" 6
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP15"))
> + "(wCU1|wCU2), wCU9"
> +)
> +
> +(define_insn_reservation "wIR16" 6
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP16"))
> + "(wCU1+wCU2), wCU9*2"
> +)
> +
> +(define_insn_reservation "wIR17" 6
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP17"))
> + "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
> +)
> +
> +(define_insn_reservation "wIR18" 6
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP18"))
> + "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
> +)
> +
> +(define_insn_reservation "wIR19" 10
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP19"))
> + "(wCU1+wCU2), wCU9"
> +)
> +
> +(define_insn_reservation "wIR20" 10
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP20"))
> + "(wCU1+wCU2)*2, wCU9"
> +)
> +
> +(define_insn_reservation "wIR21" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP21"))
> + "(wCU1|wCU2), wCU11"
> +)
> +
> +(define_insn_reservation "wIR22" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP22"))
> + "(wCU1+wCU2), wCU11*2"
> +)
> +
> +(define_insn_reservation "wIR23" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP23"))
> + "(wCU1|wCU2), wCU11"
> +)
> +
> +(define_insn_reservation "wIR24" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP24"))
> + "(wCU1+wCU2), wCU11*2"
> +)
> +
> +(define_insn_reservation "wIR25" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP25"))
> + "(wCU1|wCU2), wCU11"
> +)
> +
> +(define_insn_reservation "wIR26" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP26"))
> + "(wCU1+wCU2), wCU11*2"
> +)
> +
> +(define_insn_reservation "wIR27" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP27"))
> + "(wCU1|wCU2), wCU10"
> +)
> +
> +(define_insn_reservation "wIR28" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP28"))
> + "(wCU1+wCU2), wCU10*2"
> +)
> +
> +(define_insn_reservation "wIR29" 16
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP29"))
> + "(wCU1|wCU2), wCU9, wCU12*8"
> +)
> +
> +(define_insn_reservation "wIR30" 16
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP30"))
> + "(wCU1|wCU2), wCU9, wCU12*8"
> +)
> +
> +(define_insn_reservation "wIR31" 26
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP31"))
> + "(wCU1|wCU2), wCU9, wCU12*8"
> +)
> +
> +(define_insn_reservation "wIR32" 26
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP32"))
> + "(wCU1|wCU2), wCU9, wCU12*8"
> +)
> +
> +(define_insn_reservation "wIR33" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP33"))
> + "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
> +)
> +
> +(define_insn_reservation "wIR34" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP34"))
> + "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR35" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP35"))
> + "((wCU1+wCU3)|(wCU2+wCU4)), wCU10"
> +)
> +
> +(define_insn_reservation "wIR36" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP36"))
> + "(wCU1+wCU3+wCU2+wCU4), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR37" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP37"))
> + "(wCU1|wCU2), wCU10"
> +)
> +
> +(define_insn_reservation "wIR38" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP38"))
> + "(wCU1+wCU2), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR39" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP39"))
> + "(wCU1|wCU2), wCU10"
> +)
> +
> +(define_insn_reservation "wIR40" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP40"))
> + "(wCU1+wCU2), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR41" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP41"))
> + "(wCU1+wCU3+wCU4+wCU2), wCU10*2"
> +)
> +
> +(define_insn_reservation "wIR42" 4
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP42"))
> + "(wCU1+wCU3+wCU4+wCU2)*2, wCU10*3"
> +)
> +
> +(define_insn_reservation "wIR43" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP43"))
> + "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
> +)
> +
> +(define_insn_reservation "wIR44" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP44"))
> + "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR45" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP45"))
> + "((wCU1+wCU3)|(wCU4+wCU2)), wCU10"
> +)
> +
> +(define_insn_reservation "wIR46" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP46"))
> + "(wCU1+wCU3+wCU4+wCU2), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR47" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP47"))
> + "(wCU1|wCU2), wCU10"
> +)
> +
> +(define_insn_reservation "wIR48" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP48"))
> + "(wCU1+wCU2), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR49" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP49"))
> + "(wCU1|wCU2), wCU10"
> +)
> +
> +(define_insn_reservation "wIR50" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP50"))
> + "(wCU1+wCU2), (wCU10+wCU11)"
> +)
> +
> +(define_insn_reservation "wIR51" 5
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP51"))
> + "(wCU1|wCU2), wCU9"
> +)
> +
> +(define_insn_reservation "wIR52" 5
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP52"))
> + "(wCU1+wCU2), wCU9*2"
> +)
> +
> +(define_insn_reservation "wIR53" 5
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP53"))
> + "((wCU1+wCU3)|(wCU2+wCU4)), wCU9"
> +)
> +
> +(define_insn_reservation "wIR54" 5
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP54"))
> + "(wCU1+wCU3+wCU2+wCU4), wCU9*2"
> +)
> +
> +(define_insn_reservation "wIR55" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP55"))
> + "(wCU1|wCU2), wCU11"
> +)
> +
> +(define_insn_reservation "wIR56" 2
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP56"))
> + "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
> +)
> +
> +(define_insn_reservation "wIR57" 3
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP57"))
> + "(wCU1|wCU2), wCU11"
> +)
> +
> +(define_insn_reservation "wIR58" 2
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP58"))
> + "((wCU1+wCU3)|(wCU2+wCU4)), wCU11"
> +)
> +
> +(define_insn_reservation "wIR59" 2
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "wTP59"))
> + "(wCU1+wCU3+wCU2+wCU4), wCU11*2"
> +)
> +
> +(define_insn_reservation "wIR60" 0
> + (and (eq_attr "tune_marvell_whitney" "yes")
> + (eq_attr "whitney_type" "unknown"))
> + "wCU13"
> +)
> +
> +(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 5 "wIR22" "wIR41")
> +(define_bypass 6 "wIR22" "wIR42")
> +(define_bypass 6 "wIR23" "wIR41, wIR42")
> +(define_bypass 6 "wIR24" "wIR41")
> +(define_bypass 7 "wIR24" "wIR42")
> +(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
> +(define_bypass 7 "wIR26" "wIR41")
> +(define_bypass 8 "wIR26" "wIR42")
> +(define_bypass 6 "wIR27" "wIR41, wIR42")
> +(define_bypass 6 "wIR28" "wIR41, wIR42")
> +(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 6 "wIR33" "wIR41, wIR42")
> +(define_bypass 6 "wIR34" "wIR41")
> +(define_bypass 7 "wIR34" "wIR42")
> +(define_bypass 6 "wIR35" "wIR41, wIR42")
> +(define_bypass 6 "wIR36" "wIR41")
> +(define_bypass 7 "wIR36" "wIR42")
> +(define_bypass 6 "wIR37" "wIR41, wIR42")
> +(define_bypass 6 "wIR38" "wIR41")
> +(define_bypass 7 "wIR38" "wIR42")
> +(define_bypass 6 "wIR39" "wIR41, wIR42")
> +(define_bypass 6 "wIR40" "wIR41")
> +(define_bypass 7 "wIR40" "wIR42")
> +(define_bypass 6 "wIR41" "wIR41, wIR42")
> +(define_bypass 6 "wIR42" "wIR41")
> +(define_bypass 7 "wIR42" "wIR42")
> +(define_bypass 6 "wIR43" "wIR41, wIR42")
> +(define_bypass 6 "wIR44" "wIR41")
> +(define_bypass 7 "wIR44" "wIR42")
> +(define_bypass 6 "wIR45" "wIR41, wIR42")
> +(define_bypass 6 "wIR46" "wIR41")
> +(define_bypass 7 "wIR46" "wIR42")
> +(define_bypass 6 "wIR47" "wIR41, wIR42")
> +(define_bypass 6 "wIR48" "wIR41")
> +(define_bypass 7 "wIR48" "wIR42")
> +(define_bypass 6 "wIR49" "wIR41, wIR42")
> +(define_bypass 6 "wIR50" "wIR41")
> +(define_bypass 7 "wIR50" "wIR42")
> +(define_bypass 8 "wIR51" "wIR41, wIR42")
> +(define_bypass 8 "wIR52" "wIR41")
> +(define_bypass 9 "wIR52" "wIR42")
> +(define_bypass 8 "wIR53" "wIR41, wIR42")
> +(define_bypass 8 "wIR54" "wIR41")
> +(define_bypass 9 "wIR54" "wIR42")
> +(define_bypass 2 "wIR56" "wIR41, wIR42")
> +(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
> +(define_bypass 5 "wIR58" "wIR41, wIR42")
> +(define_bypass 5 "wIR59" "wIR41")
> +(define_bypass 6 "wIR59" "wIR42")
> diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
> index d82a123..8af9ad2 100644
> --- a/gcc/config/arm/t-arm
> +++ b/gcc/config/arm/t-arm
> @@ -61,7 +61,8 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
> $(srcdir)/config/arm/thumb2.md \
> $(srcdir)/config/arm/vec-common.md \
> $(srcdir)/config/arm/vfp11.md \
> - $(srcdir)/config/arm/vfp.md
> + $(srcdir)/config/arm/vfp.md \
> + $(srcdir)/config/arm/marvell-whitney.md
>
> s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
> s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 15068da..c2522de 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -12869,6 +12869,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
> @samp{cortex-m0.small-multiply},
> @samp{cortex-m0plus.small-multiply},
> @samp{marvell-pj4},
> +@samp{marvell-whitney},
> @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
> @samp{fa526}, @samp{fa626},
> @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2015-02-25 13:43 ` Xingxing Pan
2015-02-26 8:04 ` Xingxing Pan
@ 2015-02-26 10:27 ` Kyrill Tkachov
2015-02-26 10:59 ` Maxim Kuvyrkov
1 sibling, 1 reply; 13+ messages in thread
From: Kyrill Tkachov @ 2015-02-26 10:27 UTC (permalink / raw)
To: Xingxing Pan, gcc-patches, nickc, paul, Ramana Radhakrishnan,
Richard Earnshaw, James Greenhalgh
Cc: Xinyu Qi, Liping Gao
Hi Xingxing,
Some comments inline on the tuning struct and pipeline description.
On 25/02/15 13:32, Xingxing Pan wrote:
> Hi,
>
> This patch merges pipeline description for marvell-whitney to latest
code base.
> Is it OK for trunk?
>
> -- Regards, Xingxing
> whitney_p1_20150225.patch
A couple of questions:
+const struct tune_params arm_marvell_whitney_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa9_extra_costs,
+ cortex_a9_sched_adjust_cost,
Are you sure the cortexa9_extra_costs are best for this? Did you try
other cost
tables? Do you think it would be good to write your own?
The pipeline description you posted seems to be very intricate.
If such complexity is needed to get the most out of the core, then perhaps
it could benefit from a custom cost table?
Also, are you sure cortex_a9_sched_adjust_cost is appropriate?
It's a very Cortex-A9 specific hook and we don't use it for any other cores.
Did it give meaningful improvements in performance?
I don't know much about this core (any public documentation you can point
us at, perhaps?) so I'll trust you that these are optimal...
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ ARM_PREFETCH_BENEFICIAL(4,32,32),
+ false, /* Prefer constant pool. */
+ arm_default_branch_cost,
+ false, /* Prefer LDRD/STRD. */
+ {true, true}, /* Prefer non short circuit. */
+ &arm_default_vec_cost, /* Vectorizer costs. */
+ false, /* Prefer Neon for
64-bits bitops. */
+ false, false, /* Prefer 32-bit
encodings. */
+ false, /* Prefer Neon for stringops. */
+ 8 /* Maximum insns to inline memset. */
+};
+
As Maxim said, you need to take into account the two new fields that were
recently added, the fusion and prefetcher modelling ones.
>
> diff --git a/gcc/config/arm/marvell-whitney.md
b/gcc/config/arm/marvell-whitney.md
> new file mode 100644
> index 0000000..fffbd29
> --- /dev/null
> +++ b/gcc/config/arm/marvell-whitney.md
> @@ -0,0 +1,678 @@
> +;; Marvell ARM Processor Pipeline Description
> +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
Update the year to 2015 .
>
> +;;
> +;; Contributed by Marvell.
> +
> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it
> +;; under the terms of the GNU General Public License as published
> +;; by the Free Software Foundation; either version 3, or (at your
> +;; option) any later version.
> +;;
> +;; GCC is distributed in the hope that it will be useful, but WITHOUT
> +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
> +;; License for more details.
> +;;
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3. If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +(define_attr "whitney_type"
> + "wTP1,wTP2,wTP3,wTP4,wTP5,wTP6,wTP7,wTP8,wTP9,wTP10,wTP11,wTP12,wTP13,\
> +
wTP14,wTP15,wTP16,wTP17,wTP18,wTP19,wTP20,wTP21,wTP22,wTP23,wTP24,wTP25,\
> +
wTP26,wTP27,wTP28,wTP29,wTP30,wTP31,wTP32,wTP33,wTP34,wTP35,wTP36,wTP37,\
> +
wTP38,wTP39,wTP40,wTP41,wTP42,wTP43,wTP44,wTP45,wTP46,wTP47,wTP48,wTP49,\
> + wTP50,wTP51,wTP52,wTP53,wTP54,wTP55,wTP56,wTP57,wTP58,wTP59,\
These types are very hard to remember and understand, and hence maintain.
I'm assuming the wTP* notation stands for "Whitney TyPe"?
Look at the other pipeline descriptions in config/arm/ and try to give
them more
descriptive names, like: whitney_alu_simple, whitney_alu_shift_reg etc.
It will make it much easier to understand.
I've tried this patch out and added:
(automata_option "v")
(automata_option "time")
(automata_option "stats")
(automata_option "progress")
to the .md file to get some compiler build-time stats on the automata.
I see that the whitney_pipe automaton is the largest automaton in terms
of NDFA states, and second largest in minimal DFA states:
44170 NDFA states, 188695 NDFA arcs
44170 DFA states, 188695 DFA arcs
7070 minimal DFA states, 66279 minimal DFA arcs
923 all insns 30 insn equivalence classes
Could the complexity of it be reduced without sacrificing code quality?
In some cores we break up the automaton into two automata, roughly
separated into
an integer/memory unit and another one for FP/NEON units to reduce the
state space.
Look at cortex-a15.md and cortex-a15-neon.md or some other description
of that kind.
>
> + (cond [
> + (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,adc_reg,\
> + adc_imm,bfm,branch,call,clz,extend,logic_imm,\
> + logic_reg,logics_imm,logics_reg,logics_shift_reg,\
> + mov_imm,mov_reg,mvn_imm,mvn_reg,shift_imm,\
> + shift_reg,rev")
> + (const_string "wTP1")
> + (eq_attr "type" "alu_shift_imm,alu_shift_reg")
> + (if_then_else (match_test
> + "marvell_whitney_inner_shift (insn)")
> + (const_string "wTP2")
> + (const_string "wTP1"))
> + (eq_attr "type" "alus_shift_imm,alus_shift_reg,mov_shift_reg,\
> + mov_shift,mvn_shift_reg,mvn_shift,logic_shift_imm,\
> + logic_shift_reg,multiple")
> + (const_string "wTP2")
> + (eq_attr "type"
"mla,mlas,mul,muls,smlal,smlalxy,smlaxy,smull,\
> + smulxy,umlal,umull")
> + (const_string "wTP3")
> + (eq_attr "type" "sdiv,udiv")
> + (const_string "wTP4")
> + (eq_attr "type" "load1,load2,f_loads,f_loadd,load_byte")
> + (const_string "wTP5")
> + (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
> + neon_load2_all_lanes,neon_load2_all_lanes_q,\
> + neon_load2_2reg_q")
> + (const_string "wTP7")
> + (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
> + neon_load3_3reg,neon_load3_3reg_q,\
> + neon_load3_all_lanes,neon_load3_all_lanes_q")
> + (const_string "wTP8")
> + (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
> + neon_load4_4reg,neon_load4_4reg_q,\
> + neon_load4_all_lanes,neon_load4_all_lanes_q")
> + (const_string "wTP9")
> + (eq_attr "type"
"load3,load4,neon_load1_3reg,neon_load1_3reg_q,\
> + neon_load1_4reg,neon_load1_4reg_q,neon_load1_4reg")
> + (const_string "wTP10")
> + (eq_attr "type" "load2,neon_load1_1reg,neon_load1_1reg_q,\
> + neon_load1_2reg,neon_load1_2reg_q,")
> + (const_string "wTP11")
> + (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\
> + neon_load1_one_lane,neon_load1_one_lane_q,")
> + (const_string "wTP6")
> + (eq_attr "type" "f_stored,f_stores,store1,store2")
> + (const_string "wTP12")
> + (eq_attr "type"
"f_stored,neon_store1_3reg,neon_store1_3reg_q,\
> + neon_store1_4reg,neon_store1_4reg_q,\
> + neon_store2_4reg,neon_store2_4reg_q,\
> + neon_store3_3reg,neon_store3_3reg_q,\
> + neon_store3_one_lane,neon_store3_one_lane_q,\
> + neon_store4_4reg,neon_store4_4reg_q,\
> + neon_store4_one_lane,neon_store4_one_lane_q,\
> + store3,store4")
> + (const_string "wTP13")
> + (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
> + neon_store1_2reg,neon_store1_2reg_q,\
> + neon_store1_one_lane,neon_store1_one_lane_q,\
> + neon_store2_2reg,neon_store2_2reg_q,\
> + neon_store2_one_lane,neon_store2_one_lane_q")
> + (const_string "wTP14")
> + (eq_attr "type"
"fmuld,fmuls,neon_fp_mul_s,neon_fp_mul_s_scalar")
> + (const_string "wTP15")
> + (eq_attr "type" "neon_fp_mul_s_q,neon_fp_mul_s_scalar_q")
> + (const_string "wTP16")
> + (eq_attr "type" "ffmad,ffmas,neon_fp_mla_s,neon_fp_round_s,\
> + neon_fp_round_d")
> + (const_string "wTP17")
> + (eq_attr "type" "neon_fp_mla_s_q,neon_fp_round_s_q,\
> + neon_fp_round_d_q")
> + (const_string "wTP18")
> + (eq_attr "type"
"fmacd,fmacs,neon_fp_mla_s,neon_fp_mla_s_scalar,\
> + neon_fp_recps_s,neon_fp_rsqrts_s")
> + (const_string "wTP19")
> + (eq_attr "type" "neon_fp_mla_s_q,neon_fp_mla_s_scalar_q,\
> + neon_fp_recps_s_q,neon_fp_rsqrts_s_q")
> + (const_string "wTP20")
> + (eq_attr "type" "fconsts,fconstd,ffariths,ffarithd,fmov,\
> + neon_fp_abs_s,neon_fp_neg_s")
> + (const_string "wTP21")
> + (eq_attr "type" "neon_fp_abs_s_q,neon_fp_neg_s_q")
> + (const_string "wTP22")
> + (eq_attr "type"
"fcmpd,fcmps,neon_fp_minmax_s,neon_fp_compare_s,\
> + neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
> + (const_string "wTP23")
> + (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_compare_s_q,\
> + neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q")
> + (const_string "wTP24")
> + (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f,neon_fp_to_int_s,\
> + neon_fp_to_int_d,neon_int_to_fp_s,neon_int_to_fp_d")
> + (const_string "wTP25")
> + (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
> + neon_int_to_fp_s_q,neon_int_to_fp_d_q")
> + (const_string "wTP26")
> + (eq_attr "type" "faddd,fadds,neon_fp_abd_s,neon_fp_addsub_s,\
> + neon_fp_reduc_add_s")
> + (const_string "wTP27")
> + (eq_attr "type" "neon_fp_abd_s_q,neon_fp_addsub_s_q,\
> + neon_fp_reduc_add_s_q")
> + (const_string "wTP28")
> + (eq_attr "type" "fdivs")
> + (const_string "wTP29")
> + (eq_attr "type" "fsqrts")
> + (const_string "wTP30")
> + (eq_attr "type" "fdivd")
> + (const_string "wTP31")
> + (eq_attr "type" "fsqrtd")
> + (const_string "wTP32")
> + (eq_attr "type" "neon_reduc_add_acc")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP33")
> + (const_string "wTP35"))
> + (eq_attr "type" "neon_reduc_add_acc_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP34")
> + (const_string "wTP36"))
> + (eq_attr "type"
"neon_add,neon_qadd,neon_qsub,neon_reduc_add_long,\
> + neon_reduc_add,neon_sub,neon_sub_halve")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP37")
> + (const_string "wTP39"))
> + (eq_attr "type" "neon_add_q,neon_qadd_q,neon_qsub_q,\
> + neon_reduc_add_q,neon_sub_q,neon_sub_halve_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP38")
> + (const_string "wTP40"))
> + (eq_attr "type" "neon_add_halve,neon_add_long,neon_add_widen,\
> + neon_compare,neon_compare_zero,neon_sub_long,\
> + neon_sub_widen,neon_tst")
> + (const_string "wTP37")
> + (eq_attr "type" "neon_add_halve_q,neon_compare_q,\
> + neon_compare_zero_q,neon_tst_q")
> + (const_string "wTP38")
> + (eq_attr "type"
"neon_add_halve_narrow_q,neon_sub_halve_narrow_q")
> + (const_string "wTP40")
> + (eq_attr "type" "neon_permute,neon_tbl1,neon_tbl2,neon_tbl3,\
> + neon_tbl4,neon_zip")
> + (const_string "wTP41")
> + (eq_attr "type" "neon_permute_q,neon_zip_q")
> + (const_string "wTP42")
> + (eq_attr "type" "neon_bsl,neon_logic")
> + (const_string "wTP43")
> + (eq_attr "type" "neon_arith_acc,neon_shift_acc")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP43")
> + (const_string "wTP45"))
> + (eq_attr "type" "neon_arith_acc_q,neon_shift_acc_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP44")
> + (const_string "wTP46"))
> + (eq_attr "type" "neon_logic_q")
> + (const_string "wTP44")
> + (eq_attr "type" "neon_cls,neon_cnt,neon_dup,neon_ext,\
> + neon_fp_recpe_s,neon_fp_rsqrte_s,neon_minmax,\
> + neon_move,neon_reduc_minmax,neon_rev")
> + (const_string "wTP47")
> + (eq_attr "type" "neon_cls_q,neon_cnt_q,neon_dup_q,neon_ext_q,\
> + neon_fp_recpe_s_q,neon_fp_rsqrte_s_q,neon_minmax_q,\
> + neon_move_q,neon_move_narrow_q,neon_reduc_minmax_q,\
> + neon_rev_q,neon_sat_shift_imm_narrow_q,\
> + neon_shift_imm_narrow_q")
> + (const_string "wTP48")
> + (eq_attr "type" "neon_abd_long,neon_abs,neon_neg,neon_qabs,\
> + neon_qneg,neon_sat_shift_imm,neon_shift_imm_long,\
> + neon_shift_imm,neon_shift_reg")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP47")
> + (const_string "wTP49"))
> + (eq_attr "type"
"neon_abs_q,neon_neg_q,neon_qabs_q,neon_qneg_q,\
> + neon_sat_shift_imm_q,neon_shift_imm_q,\
> + neon_shift_reg_q")
> + (if_then_else (match_test
> + "marvell_whitney_vector_mode_qi (insn)")
> + (const_string "wTP48")
> + (const_string "wTP50"))
> + (eq_attr "type"
"neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
> + neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s")
> + (const_string "wTP51")
> + (eq_attr "type"
"neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
> + neon_mul_h_scalar_long,neon_mul_s_scalar_long,\
> + neon_sat_mul_b_long,neon_sat_mul_h_long,\
> + neon_sat_mul_s_long,neon_sat_mul_h_scalar_long,\
> + neon_sat_mul_s_scalar_long,neon_sat_mul_h_scalar_q,\
> + neon_sat_mul_s_scalar_q")
> + (const_string "wTP52")
> + (eq_attr "type"
"neon_mla_b,neon_mla_h,neon_mla_s,neon_mla_h_scalar,\
> + neon_mla_s_scalar")
> + (const_string "wTP53")
> + (eq_attr "type" "neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
> + neon_mla_h_scalar_q,neon_mla_s_scalar_q,\
> + neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
> + neon_mla_h_scalar_long,neon_mla_s_scalar_long,\
> + neon_sat_mla_b_long,neon_sat_mla_h_long,\
> + neon_sat_mla_s_long,neon_sat_mla_h_scalar_long,\
> + neon_sat_mla_s_scalar_long")
> + (const_string "wTP54")
> + (eq_attr "type" "f_flag,f_mrc,f_mrrc")
> + (const_string "wTP57")
> + (eq_attr "type" "neon_to_gp,neon_to_gp_q")
> + (const_string "wTP55")
> + (eq_attr "type" "f_mcr,f_mcrr")
> + (const_string "wTP58")
> + (eq_attr "type" "neon_from_gp_q")
> + (const_string "wTP59")
> + (eq_attr "type" "neon_from_gp")
> + (const_string "wTP56")]
> + (const_string "unknown")))
> +
<snip>
>
> +
> +(define_bypass 8 "wIR15" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 8 "wIR16" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 8 "wIR17" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 8 "wIR18" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 12 "wIR19" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 12 "wIR20" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 4 "wIR21" "wIR29, wIR31, wIR30, wIR32")
> +(define_bypass 5 "wIR22" "wIR41")
> +(define_bypass 6 "wIR22" "wIR42")
> +(define_bypass 6 "wIR23" "wIR41, wIR42")
> +(define_bypass 6 "wIR24" "wIR41")
> +(define_bypass 7 "wIR24" "wIR42")
> +(define_bypass 6 "wIR25" "wIR30, wIR32, wIR29, wIR31")
> +(define_bypass 7 "wIR26" "wIR41")
> +(define_bypass 8 "wIR26" "wIR42")
> +(define_bypass 6 "wIR27" "wIR41, wIR42")
> +(define_bypass 6 "wIR28" "wIR41, wIR42")
> +(define_bypass 18 "wIR29" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 18 "wIR30" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 28 "wIR31" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 28 "wIR32" "wIR29, wIR30, wIR31, wIR32")
> +(define_bypass 6 "wIR33" "wIR41, wIR42")
> +(define_bypass 6 "wIR34" "wIR41")
> +(define_bypass 7 "wIR34" "wIR42")
> +(define_bypass 6 "wIR35" "wIR41, wIR42")
> +(define_bypass 6 "wIR36" "wIR41")
> +(define_bypass 7 "wIR36" "wIR42")
> +(define_bypass 6 "wIR37" "wIR41, wIR42")
> +(define_bypass 6 "wIR38" "wIR41")
> +(define_bypass 7 "wIR38" "wIR42")
> +(define_bypass 6 "wIR39" "wIR41, wIR42")
> +(define_bypass 6 "wIR40" "wIR41")
> +(define_bypass 7 "wIR40" "wIR42")
> +(define_bypass 6 "wIR41" "wIR41, wIR42")
> +(define_bypass 6 "wIR42" "wIR41")
> +(define_bypass 7 "wIR42" "wIR42")
> +(define_bypass 6 "wIR43" "wIR41, wIR42")
> +(define_bypass 6 "wIR44" "wIR41")
> +(define_bypass 7 "wIR44" "wIR42")
> +(define_bypass 6 "wIR45" "wIR41, wIR42")
> +(define_bypass 6 "wIR46" "wIR41")
> +(define_bypass 7 "wIR46" "wIR42")
> +(define_bypass 6 "wIR47" "wIR41, wIR42")
> +(define_bypass 6 "wIR48" "wIR41")
> +(define_bypass 7 "wIR48" "wIR42")
> +(define_bypass 6 "wIR49" "wIR41, wIR42")
> +(define_bypass 6 "wIR50" "wIR41")
> +(define_bypass 7 "wIR50" "wIR42")
> +(define_bypass 8 "wIR51" "wIR41, wIR42")
> +(define_bypass 8 "wIR52" "wIR41")
> +(define_bypass 9 "wIR52" "wIR42")
> +(define_bypass 8 "wIR53" "wIR41, wIR42")
> +(define_bypass 8 "wIR54" "wIR41")
> +(define_bypass 9 "wIR54" "wIR42")
> +(define_bypass 2 "wIR56" "wIR41, wIR42")
> +(define_bypass 4 "wIR58" "wIR30, wIR32, wIR29, wIR31")
> +(define_bypass 5 "wIR58" "wIR41, wIR42")
> +(define_bypass 5 "wIR59" "wIR41")
> +(define_bypass 6 "wIR59" "wIR42")
These are very hard to understand, which brings us back to my comment above.
The instruction reservations should have more descriptive names.
Cheers,
Kyrill
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [patch 1/2][ARM]: New CPU support for Marvell Whitney
2015-02-26 10:27 ` Kyrill Tkachov
@ 2015-02-26 10:59 ` Maxim Kuvyrkov
0 siblings, 0 replies; 13+ messages in thread
From: Maxim Kuvyrkov @ 2015-02-26 10:59 UTC (permalink / raw)
To: Kyrill Tkachov
Cc: Xingxing Pan, gcc-patches, Nick Clifton, Paul Brook,
Ramana Radhakrishnan, Richard Earnshaw, James Greenhalgh,
Xinyu Qi, Liping Gao
> On Feb 26, 2015, at 1:12 PM, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote:
>
>
...
> I've tried this patch out and added:
> (automata_option "v")
> (automata_option "time")
> (automata_option "stats")
> (automata_option "progress")
>
> to the .md file to get some compiler build-time stats on the automata.
> I see that the whitney_pipe automaton is the largest automaton in terms
> of NDFA states, and second largest in minimal DFA states:
>
> 44170 NDFA states, 188695 NDFA arcs
> 44170 DFA states, 188695 DFA arcs
> 7070 minimal DFA states, 66279 minimal DFA arcs
> 923 all insns 30 insn equivalence classes
>
> Could the complexity of it be reduced without sacrificing code quality?
> In some cores we break up the automaton into two automata, roughly separated into
> an integer/memory unit and another one for FP/NEON units to reduce the state space.
> Look at cortex-a15.md and cortex-a15-neon.md or some other description of that kind.
I think converting the C predicates to attributes would reduce the number of states since DFA generator will be able to fold them.
--
Maxim Kuvyrkov
www.linaro.org
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2015-02-26 10:46 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-12-18 10:21 [patch 1/2][ARM]: New CPU support for Marvell Whitney Xingxing Pan
2014-12-19 10:37 ` Kyrill Tkachov
2014-12-19 10:59 ` Kyrill Tkachov
2014-12-19 11:03 ` Xingxing Pan
2014-12-22 12:36 ` [PING][patch " Xingxing Pan
2015-01-09 11:29 ` [patch " Kyrill Tkachov
2015-01-13 9:51 ` Xingxing Pan
2015-02-25 13:43 ` Xingxing Pan
2015-02-26 8:04 ` Xingxing Pan
2015-02-26 9:59 ` Maxim Kuvyrkov
2015-02-26 10:27 ` Kyrill Tkachov
2015-02-26 10:59 ` Maxim Kuvyrkov
2015-02-26 10:12 ` Ramana Radhakrishnan
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