From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3272 invoked by alias); 16 Jan 2015 13:55:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 3260 invoked by uid 89); 16 Jan 2015 13:55:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Jan 2015 13:55:33 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Fri, 16 Jan 2015 13:55:31 +0000 Received: from [10.1.203.161] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Jan 2015 13:55:30 +0000 Message-ID: <54B9187A.7000406@arm.com> Date: Fri, 16 Jan 2015 14:08:00 -0000 From: Tejas Belagod User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Christophe Lyon , "gcc-patches@gcc.gnu.org" Subject: Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests. References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> <1421162314-25779-4-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1421162314-25779-4-git-send-email-christophe.lyon@linaro.org> X-MC-Unique: 115011613553101001 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-01/txt/msg01377.txt.bz2 > +#ifndef NO_FLOAT_VARIANT > + VLOAD(vector, buffer, , float, f, 32, 2); > + VLOAD(vector, buffer, q, float, f, 32, 4); > +#endif > .... > +#ifndef NO_FLOAT_VARIANT > + VDUP(vector2, , float, f, 32, 2, -15.5f); > + VDUP(vector2, q, float, f, 32, 4, -14.5f); > +#endif > + > +#ifndef NO_FLOAT_VARIANT > +#define FLOAT_VARIANT(MACRO, VAR) \ > + MACRO(VAR, , float, f, 32, 2); \ > + MACRO(VAR, q, float, f, 32, 4) > +#else > +#define FLOAT_VARIANT(MACRO, VAR) > +#endif Double negative! :-) Probably easier on the reader to avoid it, but your=20 call. > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c b= /gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c > new file mode 100644 > index 0000000..2591b16 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c > @@ -0,0 +1,64 @@ > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +#define INSN_NAME vmax > +#define TEST_MSG "VMAX/VMAXQ" > + > +/* Expected results. */ > +VECT_VAR_DECL(expected,int,8,8) [] =3D { 0xf3, 0xf3, 0xf3, 0xf3, > + 0xf4, 0xf5, 0xf6, 0xf7 }; > +VECT_VAR_DECL(expected,int,16,4) [] =3D { 0xfff2, 0xfff2, 0xfff2, 0xfff3= }; > +VECT_VAR_DECL(expected,int,32,2) [] =3D { 0xfffffff0, 0xfffffff1 }; > +VECT_VAR_DECL(expected,int,64,1) [] =3D { 0x3333333333333333 }; > +VECT_VAR_DECL(expected,uint,8,8) [] =3D { 0xf3, 0xf3, 0xf3, 0xf3, > + 0xf4, 0xf5, 0xf6, 0xf7 }; > +VECT_VAR_DECL(expected,uint,16,4) [] =3D { 0xfff1, 0xfff1, 0xfff2, 0xfff= 3 }; > +VECT_VAR_DECL(expected,uint,32,2) [] =3D { 0xfffffff0, 0xfffffff1 }; > +VECT_VAR_DECL(expected,uint,64,1) [] =3D { 0x3333333333333333 }; > +VECT_VAR_DECL(expected,poly,8,8) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,poly,16,4) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3 }; > +VECT_VAR_DECL(expected,hfloat,32,2) [] =3D { 0xc1780000, 0xc1700000 }; > +VECT_VAR_DECL(expected,int,8,16) [] =3D { 0xf4, 0xf4, 0xf4, 0xf4, > + 0xf4, 0xf5, 0xf6, 0xf7, > + 0xf8, 0xf9, 0xfa, 0xfb, > + 0xfc, 0xfd, 0xfe, 0xff }; > +VECT_VAR_DECL(expected,int,16,8) [] =3D { 0xfff3, 0xfff3, 0xfff3, 0xfff3, > + 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; > +VECT_VAR_DECL(expected,int,32,4) [] =3D { 0xfffffff1, 0xfffffff1, > + 0xfffffff2, 0xfffffff3 }; > +VECT_VAR_DECL(expected,int,64,2) [] =3D { 0x3333333333333333, > + 0x3333333333333333 }; > +VECT_VAR_DECL(expected,uint,8,16) [] =3D { 0xf9, 0xf9, 0xf9, 0xf9, > + 0xf9, 0xf9, 0xf9, 0xf9, > + 0xf9, 0xf9, 0xfa, 0xfb, > + 0xfc, 0xfd, 0xfe, 0xff }; > +VECT_VAR_DECL(expected,uint,16,8) [] =3D { 0xfff2, 0xfff2, 0xfff2, 0xfff= 3, > + 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; > +VECT_VAR_DECL(expected,uint,32,4) [] =3D { 0xfffffff1, 0xfffffff1, > + 0xfffffff2, 0xfffffff3 }; > +VECT_VAR_DECL(expected,uint,64,2) [] =3D { 0x3333333333333333, > + 0x3333333333333333 }; > +VECT_VAR_DECL(expected,poly,8,16) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,poly,16,8) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3, > + 0x3333, 0x3333, 0x3333, 0x3333 }; > +VECT_VAR_DECL(expected,hfloat,32,4) [] =3D { 0xc1680000, 0xc1680000, > + 0xc1600000, 0xc1500000 }; > + > +/* Expected results with special FP values. */ > +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] =3D { 0x7fc00000, 0x7fc00000, > + 0x7fc00000, 0x7fc00000 }; > +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] =3D { 0x7fc00000, 0x7fc00000, > + 0x7fc00000, 0x7fc00000 }; > +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] =3D { 0x7f800000, 0x7f800000, > + 0x7f800000, 0x7f800000 }; > +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] =3D { 0x3f800000, 0x3f800000, > + 0x3f800000, 0x3f800000 }; > +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] =3D { 0x0, 0x0, 0x0, 0x0 }; > +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] =3D { 0x0, 0x0, 0x0, 0x0 }; > + > +#include "binary_op_no64.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c b= /gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c > new file mode 100644 > index 0000000..2b5e87c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c > @@ -0,0 +1,66 @@ > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +#define INSN_NAME vmin > +#define TEST_MSG "VMIN/VMINQ" > + > +/* Expected results. */ > +VECT_VAR_DECL(expected,int,8,8) [] =3D { 0xf0, 0xf1, 0xf2, 0xf3, > + 0xf3, 0xf3, 0xf3, 0xf3 }; > +VECT_VAR_DECL(expected,int,16,4) [] =3D { 0xfff0, 0xfff1, 0xfff2, 0xfff2= }; > +VECT_VAR_DECL(expected,int,32,2) [] =3D { 0xfffffff0, 0xfffffff0 }; > +VECT_VAR_DECL(expected,int,64,1) [] =3D { 0x3333333333333333 }; > +VECT_VAR_DECL(expected,uint,8,8) [] =3D { 0xf0, 0xf1, 0xf2, 0xf3, > + 0xf3, 0xf3, 0xf3, 0xf3 }; > +VECT_VAR_DECL(expected,uint,16,4) [] =3D { 0xfff0, 0xfff1, 0xfff1, 0xfff= 1 }; > +VECT_VAR_DECL(expected,uint,32,2) [] =3D { 0xfffffff0, 0xfffffff0 }; > +VECT_VAR_DECL(expected,uint,64,1) [] =3D { 0x3333333333333333 }; > +VECT_VAR_DECL(expected,poly,8,8) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,poly,16,4) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3 }; > +VECT_VAR_DECL(expected,hfloat,32,2) [] =3D { 0xc1800000, 0xc1780000 }; > +VECT_VAR_DECL(expected,int,8,16) [] =3D { 0xf0, 0xf1, 0xf2, 0xf3, > + 0xf4, 0xf4, 0xf4, 0xf4, > + 0xf4, 0xf4, 0xf4, 0xf4, > + 0xf4, 0xf4, 0xf4, 0xf4 }; > +VECT_VAR_DECL(expected,int,16,8) [] =3D { 0xfff0, 0xfff1, 0xfff2, 0xfff3, > + 0xfff3, 0xfff3, 0xfff3, 0xfff3 }; > +VECT_VAR_DECL(expected,int,32,4) [] =3D { 0xfffffff0, 0xfffffff1, > + 0xfffffff1, 0xfffffff1 }; > +VECT_VAR_DECL(expected,int,64,2) [] =3D { 0x3333333333333333, > + 0x3333333333333333 }; > +VECT_VAR_DECL(expected,uint,8,16) [] =3D { 0xf0, 0xf1, 0xf2, 0xf3, > + 0xf4, 0xf5, 0xf6, 0xf7, > + 0xf8, 0xf9, 0xf9, 0xf9, > + 0xf9, 0xf9, 0xf9, 0xf9 }; > +VECT_VAR_DECL(expected,uint,16,8) [] =3D { 0xfff0, 0xfff1, 0xfff2, 0xfff= 2, > + 0xfff2, 0xfff2, 0xfff2, 0xfff2 }; > +VECT_VAR_DECL(expected,uint,32,4) [] =3D { 0xfffffff0, 0xfffffff1, > + 0xfffffff1, 0xfffffff1 }; > +VECT_VAR_DECL(expected,uint,64,2) [] =3D { 0x3333333333333333, > + 0x3333333333333333 }; > +VECT_VAR_DECL(expected,poly,8,16) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,poly,16,8) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3, > + 0x3333, 0x3333, 0x3333, 0x3333 }; > + > +VECT_VAR_DECL(expected,hfloat,32,4) [] =3D { 0xc1800000, 0xc1700000, > + 0xc1680000, 0xc1680000 }; > +/* Expected results with special FP values. */ > +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] =3D { 0x7fc00000, 0x7fc00000, > + 0x7fc00000, 0x7fc00000 }; > +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] =3D { 0x7fc00000, 0x7fc00000, > + 0x7fc00000, 0x7fc00000 }; > +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] =3D { 0x3f800000, 0x3f800000, > + 0x3f800000, 0x3f800000 }; > +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] =3D { 0xff800000, 0xff800000, > + 0xff800000, 0xff800000 }; > +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] =3D { 0x80000000, 0x8000000= 0, > + 0x80000000, 0x80000000 }; > +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] =3D { 0x80000000, 0x8000000= 0, > + 0x80000000, 0x80000000 }; > + > +#include "binary_op_no64.inc" vmax and vmin do have v_f64 and vq_f64 variants. Otherwise, they look good to me(but I can't approve it). Tejas.