From: Tejas Belagod <tejas.belagod@arm.com>
To: Christophe Lyon <christophe.lyon@linaro.org>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
Date: Fri, 16 Jan 2015 15:35:00 -0000 [thread overview]
Message-ID: <54B92C45.8010103@arm.com> (raw)
In-Reply-To: <1421162314-25779-6-git-send-email-christophe.lyon@linaro.org>
On 13/01/15 15:18, Christophe Lyon wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
> new file mode 100644
> index 0000000..53cd8f3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
> @@ -0,0 +1,671 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +
> +/* vld2_dup/chunk 0. */
> +VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld2_dup/chunk 1. */
> +VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld3_dup/chunk 0. */
> +VECT_VAR_DECL(expected_vld3_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
> + 0xf1, 0xf2, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld3_0,int,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff0 };
> +VECT_VAR_DECL(expected_vld3_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld3_0,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld3_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
> + 0xf1, 0xf2, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld3_0,uint,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff0 };
> +VECT_VAR_DECL(expected_vld3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld3_0,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
> + 0xf1, 0xf2, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff0 };
> +VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld3_dup/chunk 1. */
> +VECT_VAR_DECL(expected_vld3_1,int,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
> + 0xf0, 0xf1, 0xf2, 0xf0 };
> +VECT_VAR_DECL(expected_vld3_1,int,16,4) [] = { 0xfff1, 0xfff2,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld3_1,int,32,2) [] = { 0xfffffff2, 0xfffffff0 };
> +VECT_VAR_DECL(expected_vld3_1,int,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld3_1,uint,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
> + 0xf0, 0xf1, 0xf2, 0xf0 };
> +VECT_VAR_DECL(expected_vld3_1,uint,16,4) [] = { 0xfff1, 0xfff2,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld3_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff0 };
> +VECT_VAR_DECL(expected_vld3_1,uint,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
> + 0xf0, 0xf1, 0xf2, 0xf0 };
> +VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000 };
> +VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld3_dup/chunk 2. */
> +VECT_VAR_DECL(expected_vld3_2,int,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
> + 0xf2, 0xf0, 0xf1, 0xf2 };
> +VECT_VAR_DECL(expected_vld3_2,int,16,4) [] = { 0xfff2, 0xfff0,
> + 0xfff1, 0xfff2 };
> +VECT_VAR_DECL(expected_vld3_2,int,32,2) [] = { 0xfffffff1, 0xfffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,int,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
> + 0xf2, 0xf0, 0xf1, 0xf2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,16,4) [] = { 0xfff2, 0xfff0,
> + 0xfff1, 0xfff2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,32,2) [] = { 0xfffffff1, 0xfffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
> + 0xf2, 0xf0, 0xf1, 0xf2 };
> +VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0,
> + 0xfff1, 0xfff2 };
> +VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000 };
> +VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk 0. */
> +VECT_VAR_DECL(expected_vld4_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_0,int,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_0,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld4_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk 1. */
> +VECT_VAR_DECL(expected_vld4_1,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_1,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_1,int,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld4_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
> +VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk 2. */
> +VECT_VAR_DECL(expected_vld4_2,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_2,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_2,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_2,int,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld4_2,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_2,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_2,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk3. */
> +VECT_VAR_DECL(expected_vld4_3,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_3,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_3,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,int,64,1) [] = { 0xfffffffffffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
> +VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +void exec_vldX_dup (void)
> +{
> + /* In this case, input variables are arrays of vectors. */
> +#define DECL_VLDX_DUP(T1, W, N, X) \
> + VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
> + VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
> +
> + /* We need to use a temporary result buffer (result_bis), because
> + the one used for other tests is not large enough. A subset of the
> + result data is moved from result_bis to result, and it is this
> + subset which is used to check the actual behaviour. The next
> + macro enables to move another chunk of data from result_bis to
> + result. */
> +#define TEST_VLDX_DUP(Q, T1, T2, W, N, X) \
> + VECT_ARRAY_VAR(vector, T1, W, N, X) = \
> + vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]); \
> + \
> + vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
> + VECT_ARRAY_VAR(vector, T1, W, N, X)); \
> + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
> + sizeof(VECT_VAR(result, T1, W, N)));
> +
> +
> + /* Overwrite "result" with the contents of "result_bis"[Y]. */
> +#define TEST_EXTRA_CHUNK(T1, W, N, X,Y) \
> + memcpy(VECT_VAR(result, T1, W, N), \
> + &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
> + sizeof(VECT_VAR(result, T1, W, N)));
> +
> +#define DECL_ALL_VLDX_DUP(X) \
> + DECL_VLDX_DUP(int, 8, 8, X); \
> + DECL_VLDX_DUP(int, 16, 4, X); \
> + DECL_VLDX_DUP(int, 32, 2, X); \
> + DECL_VLDX_DUP(int, 64, 1, X); \
> + DECL_VLDX_DUP(uint, 8, 8, X); \
> + DECL_VLDX_DUP(uint, 16, 4, X); \
> + DECL_VLDX_DUP(uint, 32, 2, X); \
> + DECL_VLDX_DUP(uint, 64, 1, X); \
> + DECL_VLDX_DUP(poly, 8, 8, X); \
> + DECL_VLDX_DUP(poly, 16, 4, X); \
> + DECL_VLDX_DUP(float, 32, 2, X)
> +
> +#define TEST_ALL_VLDX_DUP(X) \
> + TEST_VLDX_DUP(, int, s, 8, 8, X); \
> + TEST_VLDX_DUP(, int, s, 16, 4, X); \
> + TEST_VLDX_DUP(, int, s, 32, 2, X); \
> + TEST_VLDX_DUP(, int, s, 64, 1, X); \
> + TEST_VLDX_DUP(, uint, u, 8, 8, X); \
> + TEST_VLDX_DUP(, uint, u, 16, 4, X); \
> + TEST_VLDX_DUP(, uint, u, 32, 2, X); \
> + TEST_VLDX_DUP(, uint, u, 64, 1, X); \
> + TEST_VLDX_DUP(, poly, p, 8, 8, X); \
> + TEST_VLDX_DUP(, poly, p, 16, 4, X); \
> + TEST_VLDX_DUP(, float, f, 32, 2, X)
> +
> +#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
> + TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
> + TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
> + TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
> + TEST_EXTRA_CHUNK(int, 64, 1, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 64, 1, X, Y); \
> + TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
> + TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
> + TEST_EXTRA_CHUNK(float, 32, 2, X, Y)
> +
> +
> + DECL_ALL_VLDX_DUP(2);
> + DECL_ALL_VLDX_DUP(3);
> + DECL_ALL_VLDX_DUP(4);
> +
> + /* Special input buffers of suitable size are needed for vld2/vld3/vld4. */
> + /* Input buffers for vld2, 1 of each size */
> + VECT_ARRAY_INIT2(buffer_vld2, int, 8, 8);
> + PAD(buffer_vld2_pad, int, 8, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 16, 4);
> + PAD(buffer_vld2_pad, int, 16, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 32, 2);
> + PAD(buffer_vld2_pad, int, 32, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 64, 1);
> + PAD(buffer_vld2_pad, int, 64, 1);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 8);
> + PAD(buffer_vld2_pad, uint, 8, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 4);
> + PAD(buffer_vld2_pad, uint, 16, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 2);
> + PAD(buffer_vld2_pad, uint, 32, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 1);
> + PAD(buffer_vld2_pad, uint, 64, 1);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 8);
> + PAD(buffer_vld2_pad, poly, 8, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4);
> + PAD(buffer_vld2_pad, poly, 16, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2);
> + PAD(buffer_vld2_pad, float, 32, 2);
> +
> + VECT_ARRAY_INIT2(buffer_vld2, int, 8, 16);
> + PAD(buffer_vld2_pad, int, 8, 16);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 16, 8);
> + PAD(buffer_vld2_pad, int, 16, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 32, 4);
> + PAD(buffer_vld2_pad, int, 32, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 64, 2);
> + PAD(buffer_vld2_pad, int, 64, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 16);
> + PAD(buffer_vld2_pad, uint, 8, 16);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 8);
> + PAD(buffer_vld2_pad, uint, 16, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 4);
> + PAD(buffer_vld2_pad, uint, 32, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 2);
> + PAD(buffer_vld2_pad, uint, 64, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 16);
> + PAD(buffer_vld2_pad, poly, 8, 16);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8);
> + PAD(buffer_vld2_pad, poly, 16, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4);
> + PAD(buffer_vld2_pad, float, 32, 4);
> +
> + /* Input buffers for vld3, 1 of each size */
> + VECT_ARRAY_INIT3(buffer_vld3, int, 8, 8);
> + PAD(buffer_vld3_pad, int, 8, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 16, 4);
> + PAD(buffer_vld3_pad, int, 16, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 32, 2);
> + PAD(buffer_vld3_pad, int, 32, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 64, 1);
> + PAD(buffer_vld3_pad, int, 64, 1);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 8);
> + PAD(buffer_vld3_pad, uint, 8, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 4);
> + PAD(buffer_vld3_pad, uint, 16, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 2);
> + PAD(buffer_vld3_pad, uint, 32, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 1);
> + PAD(buffer_vld3_pad, uint, 64, 1);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 8);
> + PAD(buffer_vld3_pad, poly, 8, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4);
> + PAD(buffer_vld3_pad, poly, 16, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2);
> + PAD(buffer_vld3_pad, float, 32, 2);
> +
> + VECT_ARRAY_INIT3(buffer_vld3, int, 8, 16);
> + PAD(buffer_vld3_pad, int, 8, 16);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 16, 8);
> + PAD(buffer_vld3_pad, int, 16, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 32, 4);
> + PAD(buffer_vld3_pad, int, 32, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 64, 2);
> + PAD(buffer_vld3_pad, int, 64, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 16);
> + PAD(buffer_vld3_pad, uint, 8, 16);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 8);
> + PAD(buffer_vld3_pad, uint, 16, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 4);
> + PAD(buffer_vld3_pad, uint, 32, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 2);
> + PAD(buffer_vld3_pad, uint, 64, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 16);
> + PAD(buffer_vld3_pad, poly, 8, 16);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8);
> + PAD(buffer_vld3_pad, poly, 16, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4);
> + PAD(buffer_vld3_pad, float, 32, 4);
> +
> + /* Input buffers for vld4, 1 of each size */
> + VECT_ARRAY_INIT4(buffer_vld4, int, 8, 8);
> + PAD(buffer_vld4_pad, int, 8, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 16, 4);
> + PAD(buffer_vld4_pad, int, 16, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 32, 2);
> + PAD(buffer_vld4_pad, int, 32, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 64, 1);
> + PAD(buffer_vld4_pad, int, 64, 1);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 8);
> + PAD(buffer_vld4_pad, uint, 8, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 4);
> + PAD(buffer_vld4_pad, uint, 16, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 2);
> + PAD(buffer_vld4_pad, uint, 32, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 1);
> + PAD(buffer_vld4_pad, uint, 64, 1);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 8);
> + PAD(buffer_vld4_pad, poly, 8, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4);
> + PAD(buffer_vld4_pad, poly, 16, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2);
> + PAD(buffer_vld4_pad, float, 32, 2);
> +
> + VECT_ARRAY_INIT4(buffer_vld4, int, 8, 16);
> + PAD(buffer_vld4_pad, int, 8, 16);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 16, 8);
> + PAD(buffer_vld4_pad, int, 16, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 32, 4);
> + PAD(buffer_vld4_pad, int, 32, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 64, 2);
> + PAD(buffer_vld4_pad, int, 64, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 16);
> + PAD(buffer_vld4_pad, uint, 8, 16);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 8);
> + PAD(buffer_vld4_pad, uint, 16, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 4);
> + PAD(buffer_vld4_pad, uint, 32, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 2);
> + PAD(buffer_vld4_pad, uint, 64, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 16);
> + PAD(buffer_vld4_pad, poly, 8, 16);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8);
> + PAD(buffer_vld4_pad, poly, 16, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4);
> + PAD(buffer_vld4_pad, float, 32, 4);
> +
> + /* Check vld2_dup/vld2q_dup. */
> + clean_results ();
> +#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
> + TEST_ALL_VLDX_DUP(2);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, "chunk 0");
> +
> + TEST_ALL_EXTRA_CHUNKS(2, 1);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, "chunk 1");
> +
> + /* Check vld3_dup/vld3q_dup. */
> + clean_results ();
> +#undef TEST_MSG
> +#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
> + TEST_ALL_VLDX_DUP(3);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, "chunk 0");
> +
> + TEST_ALL_EXTRA_CHUNKS(3, 1);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, "chunk 1");
> +
> + TEST_ALL_EXTRA_CHUNKS(3, 2);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, "chunk 2");
> +
> + /* Check vld4_dup/vld4q_dup */
> + clean_results ();
> +#undef TEST_MSG
> +#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
> + TEST_ALL_VLDX_DUP(4);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, "chunk 0");
> +
> + TEST_ALL_EXTRA_CHUNKS(4, 1);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, "chunk 1");
> +
> + TEST_ALL_EXTRA_CHUNKS(4, 2);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, "chunk 2");
> +
> + TEST_ALL_EXTRA_CHUNKS(4, 3);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, "chunk 3");
> +}
> +
> +int main (void)
> +{
> + exec_vldX_dup ();
> + return 0;
> +}
> --
> 2.1.0
>
>
LGTM.
Tejas.
next prev parent reply other threads:[~2015-01-16 15:20 UTC|newest]
Thread overview: 144+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
2015-01-16 18:41 ` Tejas Belagod
2015-01-20 15:39 ` Christophe Lyon
2015-01-26 14:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
2015-01-16 17:26 ` Tejas Belagod
2015-01-19 14:14 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
2015-01-16 18:32 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
2015-01-16 18:23 ` Tejas Belagod
2015-01-19 15:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
2015-01-16 18:26 ` Tejas Belagod
2015-01-19 15:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
2015-01-19 16:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
2015-01-16 13:46 ` Tejas Belagod
2015-01-16 17:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
2015-01-16 18:48 ` Tejas Belagod
2015-01-16 19:05 ` Christophe Lyon
2015-01-16 20:34 ` Christophe Lyon
2015-01-20 15:50 ` Christophe Lyon
2015-01-26 14:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
2015-01-16 16:06 ` Tejas Belagod
2015-01-16 18:12 ` Christophe Lyon
2015-01-19 13:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
2015-01-19 16:46 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
2015-01-16 15:52 ` Tejas Belagod
2015-01-16 16:32 ` Christophe Lyon
2015-01-19 13:42 ` Marcus Shawcroft
2015-01-20 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
2015-01-16 14:08 ` Tejas Belagod
2015-01-16 16:23 ` Christophe Lyon
2015-01-16 17:20 ` Marcus Shawcroft
2015-01-16 17:59 ` Christophe Lyon
2015-01-19 13:34 ` Marcus Shawcroft
2015-01-19 15:49 ` Christophe Lyon
2015-01-19 17:33 ` Marcus Shawcroft
2015-01-21 16:35 ` Christophe Lyon
2015-01-22 12:37 ` Tejas Belagod
2015-01-22 14:42 ` Christophe Lyon
2015-01-22 15:58 ` Tejas Belagod
2015-01-22 23:10 ` Christophe Lyon
2015-01-23 11:02 ` Tejas Belagod
2015-01-23 12:08 ` Christophe Lyon
2015-01-23 15:21 ` Christophe Lyon
2015-01-25 22:51 ` Christophe Lyon
2015-01-26 13:23 ` Tejas Belagod
2015-01-26 13:57 ` Christophe Lyon
2015-02-02 10:39 ` Christophe Lyon
2015-02-02 15:38 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
2015-01-16 13:43 ` Tejas Belagod
2015-01-16 17:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
2015-01-16 16:45 ` Tejas Belagod
2015-01-19 14:11 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
2015-01-16 18:39 ` Tejas Belagod
2015-01-20 15:36 ` Christophe Lyon
2015-01-26 14:30 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
2015-01-16 16:29 ` Tejas Belagod
2015-01-19 13:54 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
2015-01-16 15:57 ` Tejas Belagod
2015-01-19 13:43 ` Marcus Shawcroft
2015-01-21 0:02 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
2015-01-16 16:21 ` Tejas Belagod
2015-01-16 16:35 ` Christophe Lyon
2015-01-20 15:30 ` Christophe Lyon
2015-01-26 14:03 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
2015-01-16 18:21 ` Tejas Belagod
2015-01-19 14:44 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
2015-01-16 14:31 ` Tejas Belagod
2015-01-16 16:31 ` Christophe Lyon
2015-01-16 17:22 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
2015-01-16 18:16 ` Tejas Belagod
2015-01-19 14:41 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
2015-01-16 18:11 ` Tejas Belagod
2015-01-19 14:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
2015-01-16 18:18 ` Tejas Belagod
2015-01-20 15:35 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
2015-01-16 15:35 ` Tejas Belagod [this message]
2015-01-16 18:17 ` Christophe Lyon
2015-01-19 13:39 ` Marcus Shawcroft
2015-01-22 16:32 ` Tejas Belagod
2015-01-22 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
2015-01-19 16:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
2015-01-16 16:23 ` Tejas Belagod
2015-01-19 13:53 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
2015-01-16 18:28 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Christophe Lyon
2015-01-16 16:30 ` Tejas Belagod
2015-01-20 15:33 ` Christophe Lyon
2015-01-26 14:08 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
2015-01-16 16:52 ` Tejas Belagod
2015-01-19 14:13 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
2015-01-16 18:24 ` Tejas Belagod
2015-01-19 15:23 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
2015-01-19 16:48 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
2015-01-16 17:54 ` Tejas Belagod
2015-01-16 18:02 ` Christophe Lyon
2015-01-20 15:34 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
2015-01-16 18:12 ` Tejas Belagod
2015-01-19 14:37 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
2015-01-16 16:22 ` Tejas Belagod
2015-01-19 13:51 ` Marcus Shawcroft
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
2015-01-19 16:54 ` Marcus Shawcroft
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
2015-01-16 18:49 ` Tejas Belagod
2015-01-16 19:20 ` Christophe Lyon
2015-01-19 17:16 ` Marcus Shawcroft
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
2015-01-20 15:26 ` Christophe Lyon
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