From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1397 invoked by alias); 16 Jan 2015 18:12:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 1374 invoked by uid 89); 16 Jan 2015 18:11:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Jan 2015 18:11:57 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Fri, 16 Jan 2015 18:11:54 +0000 Received: from [10.1.203.161] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Jan 2015 18:11:53 +0000 Message-ID: <54B95491.90402@arm.com> Date: Fri, 16 Jan 2015 18:16:00 -0000 From: Tejas Belagod User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Christophe Lyon , "gcc-patches@gcc.gnu.org" Subject: Re: [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> <1421162314-25779-21-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1421162314-25779-21-git-send-email-christophe.lyon@linaro.org> X-MC-Unique: 115011618115400201 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-01/txt/msg01458.txt.bz2 On 13/01/15 15:18, Christophe Lyon wrote: > * gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file. > * gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file. > * gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from > vXXXw.inc. > > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.in= c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc > new file mode 100644 > index 0000000..c535557 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc > @@ -0,0 +1,70 @@ > +#define FNNAME1(NAME) exec_ ## NAME > +#define FNNAME(NAME) FNNAME1(NAME) > + > +void FNNAME (INSN_NAME) (void) > +{ > + /* Basic test: y=3Dvaddw(x1,x2), then store the result. */ > +#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \ > + VECT_VAR(vector_res, T1, W2, N) =3D = \ > + INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), = \ > + VECT_VAR(vector2, T1, W, N)); \ > + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W= 2, N)) > + > +#define TEST_VADDW(INSN, T1, T2, W, W2, N) \ > + TEST_VADDW1(INSN, T1, T2, W, W2, N) > + > + DECL_VARIABLE(vector, int, 16, 8); > + DECL_VARIABLE(vector, int, 32, 4); > + DECL_VARIABLE(vector, int, 64, 2); > + DECL_VARIABLE(vector, uint, 16, 8); > + DECL_VARIABLE(vector, uint, 32, 4); > + DECL_VARIABLE(vector, uint, 64, 2); > + > + DECL_VARIABLE(vector2, int, 8, 8); > + DECL_VARIABLE(vector2, int, 16, 4); > + DECL_VARIABLE(vector2, int, 32, 2); > + DECL_VARIABLE(vector2, uint, 8, 8); > + DECL_VARIABLE(vector2, uint, 16, 4); > + DECL_VARIABLE(vector2, uint, 32, 2); > + > + DECL_VARIABLE(vector_res, int, 16, 8); > + DECL_VARIABLE(vector_res, int, 32, 4); > + DECL_VARIABLE(vector_res, int, 64, 2); > + DECL_VARIABLE(vector_res, uint, 16, 8); > + DECL_VARIABLE(vector_res, uint, 32, 4); > + DECL_VARIABLE(vector_res, uint, 64, 2); > + > + clean_results (); > + > + /* Initialize input "vector" from "buffer". */ > + VLOAD(vector, buffer, q, int, s, 16, 8); > + VLOAD(vector, buffer, q, int, s, 32, 4); > + VLOAD(vector, buffer, q, int, s, 64, 2); > + VLOAD(vector, buffer, q, uint, u, 16, 8); > + VLOAD(vector, buffer, q, uint, u, 32, 4); > + VLOAD(vector, buffer, q, uint, u, 64, 2); > + > + /* Choose init value arbitrarily. */ > + VDUP(vector2, , int, s, 8, 8, -13); > + VDUP(vector2, , int, s, 16, 4, -14); > + VDUP(vector2, , int, s, 32, 2, -16); > + VDUP(vector2, , uint, u, 8, 8, 0xf3); > + VDUP(vector2, , uint, u, 16, 4, 0xfff1); > + VDUP(vector2, , uint, u, 32, 2, 0xfffffff0); > + > + /* Execute the tests. */ > + TEST_VADDW(INSN_NAME, int, s, 8, 16, 8); > + TEST_VADDW(INSN_NAME, int, s, 16, 32, 4); > + TEST_VADDW(INSN_NAME, int, s, 32, 64, 2); > + TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8); > + TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4); > + TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2); > + > + CHECK_RESULTS (TEST_MSG, ""); > +} > + > +int main (void) > +{ > + FNNAME (INSN_NAME) (); > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c = b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c > index 95cbb31..27f54f6 100644 > --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c > @@ -2,6 +2,9 @@ > #include "arm-neon-ref.h" > #include "compute-ref-data.h" > > +#define INSN_NAME vaddw > +#define TEST_MSG "VADDW" > + > /* Expected results. */ > VECT_VAR_DECL(expected,int,8,8) [] =3D { 0x33, 0x33, 0x33, 0x33, > 0x33, 0x33, 0x33, 0x33 }; > @@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] =3D { 0x3333, 0x3= 333, 0x3333, 0x3333, > VECT_VAR_DECL(expected,hfloat,32,4) [] =3D { 0x33333333, 0x33333333, > 0x33333333, 0x33333333 }; > > -#define INSN_NAME vaddw > -#define TEST_MSG "VADDW" > - > -#define FNNAME1(NAME) exec_ ## NAME > -#define FNNAME(NAME) FNNAME1(NAME) > - > -void FNNAME (INSN_NAME) (void) > -{ > - /* Basic test: y=3Dvaddw(x1,x2), then store the result. */ > -#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \ > - VECT_VAR(vector_res, T1, W2, N) =3D = \ > - INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), = \ > - VECT_VAR(vector2, T1, W, N)); \ > - vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W= 2, N)) > - > -#define TEST_VADDW(INSN, T1, T2, W, W2, N) \ > - TEST_VADDW1(INSN, T1, T2, W, W2, N) > - > - DECL_VARIABLE(vector, int, 16, 8); > - DECL_VARIABLE(vector, int, 32, 4); > - DECL_VARIABLE(vector, int, 64, 2); > - DECL_VARIABLE(vector, uint, 16, 8); > - DECL_VARIABLE(vector, uint, 32, 4); > - DECL_VARIABLE(vector, uint, 64, 2); > - > - DECL_VARIABLE(vector2, int, 8, 8); > - DECL_VARIABLE(vector2, int, 16, 4); > - DECL_VARIABLE(vector2, int, 32, 2); > - DECL_VARIABLE(vector2, uint, 8, 8); > - DECL_VARIABLE(vector2, uint, 16, 4); > - DECL_VARIABLE(vector2, uint, 32, 2); > - > - DECL_VARIABLE(vector_res, int, 16, 8); > - DECL_VARIABLE(vector_res, int, 32, 4); > - DECL_VARIABLE(vector_res, int, 64, 2); > - DECL_VARIABLE(vector_res, uint, 16, 8); > - DECL_VARIABLE(vector_res, uint, 32, 4); > - DECL_VARIABLE(vector_res, uint, 64, 2); > - > - clean_results (); > - > - /* Initialize input "vector" from "buffer". */ > - VLOAD(vector, buffer, q, int, s, 16, 8); > - VLOAD(vector, buffer, q, int, s, 32, 4); > - VLOAD(vector, buffer, q, int, s, 64, 2); > - VLOAD(vector, buffer, q, uint, u, 16, 8); > - VLOAD(vector, buffer, q, uint, u, 32, 4); > - VLOAD(vector, buffer, q, uint, u, 64, 2); > - > - /* Choose init value arbitrarily. */ > - VDUP(vector2, , int, s, 8, 8, -13); > - VDUP(vector2, , int, s, 16, 4, -14); > - VDUP(vector2, , int, s, 32, 2, -16); > - VDUP(vector2, , uint, u, 8, 8, 0xf3); > - VDUP(vector2, , uint, u, 16, 4, 0xfff1); > - VDUP(vector2, , uint, u, 32, 2, 0xfffffff0); > - > - /* Execute the tests. */ > - TEST_VADDW(INSN_NAME, int, s, 8, 16, 8); > - TEST_VADDW(INSN_NAME, int, s, 16, 32, 4); > - TEST_VADDW(INSN_NAME, int, s, 32, 64, 2); > - TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8); > - TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4); > - TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2); > - > - CHECK_RESULTS (TEST_MSG, ""); > -} > - > -int main (void) > -{ > - FNNAME (INSN_NAME) (); > - return 0; > -} > +#include "vXXXw.inc" > diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c = b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c > new file mode 100644 > index 0000000..3e8bc98 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c > @@ -0,0 +1,50 @@ > +#include > +#include "arm-neon-ref.h" > +#include "compute-ref-data.h" > + > +#define INSN_NAME vsubw > +#define TEST_MSG "VSUBW" > + > +/* Expected results. */ > +VECT_VAR_DECL(expected,int,8,8) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,int,16,4) [] =3D { 0x3333, 0x3333, 0x3333, 0x3333= }; > +VECT_VAR_DECL(expected,int,32,2) [] =3D { 0x33333333, 0x33333333 }; > +VECT_VAR_DECL(expected,int,64,1) [] =3D { 0x3333333333333333 }; > +VECT_VAR_DECL(expected,uint,8,8) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,uint,16,4) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3 }; > +VECT_VAR_DECL(expected,uint,32,2) [] =3D { 0x33333333, 0x33333333 }; > +VECT_VAR_DECL(expected,uint,64,1) [] =3D { 0x3333333333333333 }; > +VECT_VAR_DECL(expected,poly,8,8) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,poly,16,4) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3 }; > +VECT_VAR_DECL(expected,hfloat,32,2) [] =3D { 0x33333333, 0x33333333 }; > +VECT_VAR_DECL(expected,int,8,16) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,int,16,8) [] =3D { 0xfffd, 0xfffe, 0xffff, 0x0, > + 0x1, 0x2, 0x3, 0x4 }; > +VECT_VAR_DECL(expected,int,32,4) [] =3D { 0xfffffffe, 0xffffffff, 0x0, 0= x1 }; > +VECT_VAR_DECL(expected,int,64,2) [] =3D { 0x0, 0x1 }; > +VECT_VAR_DECL(expected,uint,8,16) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,uint,16,8) [] =3D { 0xfefd, 0xfefe, 0xfeff, 0xff0= 0, > + 0xff01, 0xff02, 0xff03, 0xff04 }; > +VECT_VAR_DECL(expected,uint,32,4) [] =3D { 0xfffeffff, 0xffff0000, > + 0xffff0001, 0xffff0002 }; > +VECT_VAR_DECL(expected,uint,64,2) [] =3D { 0xffffffff00000000, > + 0xffffffff00000001 }; > +VECT_VAR_DECL(expected,poly,8,16) [] =3D { 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33, > + 0x33, 0x33, 0x33, 0x33 }; > +VECT_VAR_DECL(expected,poly,16,8) [] =3D { 0x3333, 0x3333, 0x3333, 0x333= 3, > + 0x3333, 0x3333, 0x3333, 0x3333 }; > +VECT_VAR_DECL(expected,hfloat,32,4) [] =3D { 0x33333333, 0x33333333, > + 0x33333333, 0x33333333 }; > + > +#include "vXXXw.inc" > -- > 2.1.0 > > LGTM. Tejas.