diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index f7f8ab7..66f3f4d 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -181,6 +181,15 @@ (define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) ;; compare a second time. (define_code_iterator LTUGEU [ltu geu]) +;; The signed gt, ge comparisons +(define_code_iterator GTGE [gt ge]) + +;; The unsigned gt, ge comparisons +(define_code_iterator GTUGEU [gtu geu]) + +;; Comparisons for vc +(define_code_iterator COMPARISONS [eq gt ge le lt]) + ;; A list of ... (define_code_iterator ior_xor [ior xor]) @@ -214,6 +223,11 @@ (define_code_attr t2_binop0 (define_code_attr arith_shift_insn [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) +(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") + (gtu "gt") (geu "ge")]) + +(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) + ;;---------------------------------------------------------------------------- ;; Int iterators ;;---------------------------------------------------------------------------- @@ -221,6 +235,10 @@ (define_code_attr arith_shift_insn (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) +(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE UNSPEC_VCLT UNSPEC_VCLE]) + +(define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT]) + (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM @@ -677,6 +695,11 @@ (define_int_attr sup [ ]) +(define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") + (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") + (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") + (UNSPEC_VCAGT "gt")]) + (define_int_attr r [ (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 63c327e..445df2a 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2200,134 +2200,140 @@ (define_insn "neon_vsubhn" [(set_attr "type" "neon_sub_halve_narrow_q")] ) -(define_insn "neon_vceq" - [(set (match_operand: 0 "s_register_operand" "=w,w") - (unspec: - [(match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")] - UNSPEC_VCEQ))] +;; These may expand to an UNSPEC pattern when a floating point mode is used +;; without unsafe math optimizations. +(define_expand "neon_vc" + [(match_operand: 0 "s_register_operand" "=w,w") + (neg: + (COMPARISONS:VDQW (match_operand:VDQW 1 "s_register_operand" "w,w") + (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")))] "TARGET_NEON" - "@ - vceq.\t%0, %1, %2 - vceq.\t%0, %1, #0" - [(set (attr "type") - (if_then_else (match_test "") - (const_string "neon_fp_compare_s") - (if_then_else (match_operand 2 "zero_operand") - (const_string "neon_compare_zero") - (const_string "neon_compare"))))] + { + /* For FP comparisons use UNSPECS unless -funsafe-math-optimizations + are enabled. */ + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + && !flag_unsafe_math_optimizations) + { + /* We don't just emit a gen_neon_vc_insn_unspec because + we define gen_neon_vceq_insn_unspec only for float modes + whereas this expander iterates over the integer modes as well, + but we will never expand to UNSPECs for the integer comparisons. */ + switch (mode) + { + case V2SFmode: + emit_insn (gen_neon_vcv2sf_insn_unspec (operands[0], + operands[1], + operands[2])); + break; + case V4SFmode: + emit_insn (gen_neon_vcv4sf_insn_unspec (operands[0], + operands[1], + operands[2])); + break; + default: + gcc_unreachable (); + } + } + else + emit_insn (gen_neon_vc_insn (operands[0], + operands[1], + operands[2])); + DONE; + } ) -(define_insn "neon_vcge" +(define_insn "neon_vc_insn" [(set (match_operand: 0 "s_register_operand" "=w,w") - (unspec: - [(match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")] - UNSPEC_VCGE))] - "TARGET_NEON" - "@ - vcge.\t%0, %1, %2 - vcge.\t%0, %1, #0" + (neg: + (COMPARISONS: + (match_operand:VDQW 1 "s_register_operand" "w,w") + (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz"))))] + "TARGET_NEON && !(GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + && !flag_unsafe_math_optimizations)" + { + char pattern[100]; + sprintf (pattern, "vc.%s%%#\t%%0," + " %%1, %s", + GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + ? "f" : "", + which_alternative == 0 + ? "%2" : "#0"); + output_asm_insn (pattern, operands); + return ""; + } [(set (attr "type") - (if_then_else (match_test "") - (const_string "neon_fp_compare_s") - (if_then_else (match_operand 2 "zero_operand") + (if_then_else (match_operand 2 "zero_operand") (const_string "neon_compare_zero") - (const_string "neon_compare"))))] -) - -(define_insn "neon_vcgeu" - [(set (match_operand: 0 "s_register_operand" "=w") - (unspec: - [(match_operand:VDQIW 1 "s_register_operand" "w") - (match_operand:VDQIW 2 "s_register_operand" "w")] - UNSPEC_VCGEU))] - "TARGET_NEON" - "vcge.u%#\t%0, %1, %2" - [(set_attr "type" "neon_compare")] + (const_string "neon_compare")))] ) -(define_insn "neon_vcgt" +(define_insn "neon_vc_insn_unspec" [(set (match_operand: 0 "s_register_operand" "=w,w") (unspec: - [(match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")] - UNSPEC_VCGT))] + [(match_operand:VCVTF 1 "s_register_operand" "w,w") + (match_operand:VCVTF 2 "reg_or_zero_operand" "w,Dz")] + NEON_VCMP))] "TARGET_NEON" - "@ - vcgt.\t%0, %1, %2 - vcgt.\t%0, %1, #0" - [(set (attr "type") - (if_then_else (match_test "") - (const_string "neon_fp_compare_s") - (if_then_else (match_operand 2 "zero_operand") - (const_string "neon_compare_zero") - (const_string "neon_compare"))))] + { + char pattern[100]; + sprintf (pattern, "vc.f%%#\t%%0," + " %%1, %s", + which_alternative == 0 + ? "%2" : "#0"); + output_asm_insn (pattern, operands); + return ""; +} + [(set_attr "type" "neon_fp_compare_s")] ) -(define_insn "neon_vcgtu" +(define_insn "neon_vcu" [(set (match_operand: 0 "s_register_operand" "=w") - (unspec: - [(match_operand:VDQIW 1 "s_register_operand" "w") - (match_operand:VDQIW 2 "s_register_operand" "w")] - UNSPEC_VCGTU))] + (neg: + (GTUGEU: + (match_operand:VDQIW 1 "s_register_operand" "w") + (match_operand:VDQIW 2 "s_register_operand" "w"))))] "TARGET_NEON" - "vcgt.u%#\t%0, %1, %2" + "vc.u%#\t%0, %1, %2" [(set_attr "type" "neon_compare")] ) -;; VCLE and VCLT only support comparisons with immediate zero (register -;; variants are VCGE and VCGT with operands reversed). - -(define_insn "neon_vcle" - [(set (match_operand: 0 "s_register_operand" "=w") - (unspec: - [(match_operand:VDQW 1 "s_register_operand" "w") - (match_operand:VDQW 2 "zero_operand" "Dz")] - UNSPEC_VCLE))] +(define_expand "neon_vca" + [(set (match_operand: 0 "s_register_operand") + (neg: + (GTGE: + (abs:VCVTF (match_operand:VCVTF 1 "s_register_operand")) + (abs:VCVTF (match_operand:VCVTF 2 "s_register_operand")))))] "TARGET_NEON" - "vcle.\t%0, %1, #0" - [(set (attr "type") - (if_then_else (match_test "") - (const_string "neon_fp_compare_s") - (if_then_else (match_operand 2 "zero_operand") - (const_string "neon_compare_zero") - (const_string "neon_compare"))))] -) - -(define_insn "neon_vclt" - [(set (match_operand: 0 "s_register_operand" "=w") - (unspec: - [(match_operand:VDQW 1 "s_register_operand" "w") - (match_operand:VDQW 2 "zero_operand" "Dz")] - UNSPEC_VCLT))] - "TARGET_NEON" - "vclt.\t%0, %1, #0" - [(set (attr "type") - (if_then_else (match_test "") - (const_string "neon_fp_compare_s") - (if_then_else (match_operand 2 "zero_operand") - (const_string "neon_compare_zero") - (const_string "neon_compare"))))] + { + if (flag_unsafe_math_optimizations) + emit_insn (gen_neon_vca_insn (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_neon_vca_insn_unspec (operands[0], + operands[1], + operands[2])); + DONE; + } ) -(define_insn "neon_vcage" +(define_insn "neon_vca_insn" [(set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") - (match_operand:VCVTF 2 "s_register_operand" "w")] - UNSPEC_VCAGE))] - "TARGET_NEON" - "vacge.\t%0, %1, %2" + (neg: + (GTGE: + (abs:VCVTF (match_operand:VCVTF 1 "s_register_operand" "w")) + (abs:VCVTF (match_operand:VCVTF 2 "s_register_operand" "w")))))] + "TARGET_NEON && flag_unsafe_math_optimizations" + "vac.\t%0, %1, %2" [(set_attr "type" "neon_fp_compare_s")] ) -(define_insn "neon_vcagt" +(define_insn "neon_vca_insn_unspec" [(set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand:VCVTF 1 "s_register_operand" "w") (match_operand:VCVTF 2 "s_register_operand" "w")] - UNSPEC_VCAGT))] + NEON_VACMP))] "TARGET_NEON" - "vacgt.\t%0, %1, %2" + "vac.\t%0, %1, %2" [(set_attr "type" "neon_fp_compare_s")] ) diff --git a/gcc/testsuite/gcc.target/arm/neon/pr51534.c b/gcc/testsuite/gcc.target/arm/neon/pr51534.c index 71cbb05..074bbd4 100644 --- a/gcc/testsuite/gcc.target/arm/neon/pr51534.c +++ b/gcc/testsuite/gcc.target/arm/neon/pr51534.c @@ -58,18 +58,18 @@ GEN_COND_TESTS(vceq) /* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ /* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ /* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */ -/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ -/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ +/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */ /* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ /* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */ /* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */