From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 94567 invoked by alias); 13 Mar 2015 09:14:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 94552 invoked by uid 89); 13 Mar 2015 09:14:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 13 Mar 2015 09:14:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AAF5029; Fri, 13 Mar 2015 02:14:22 -0700 (PDT) Received: from collaborate-mta1.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTP id 9B4723F267; Fri, 13 Mar 2015 02:14:07 -0700 (PDT) Received: from [10.2.206.27] (e105545-lin.cambridge.arm.com [10.2.206.27]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id D1B5013F69F; Fri, 13 Mar 2015 04:14:06 -0500 (CDT) Message-ID: <5502AA5F.6040808@arm.com> Date: Fri, 13 Mar 2015 09:14:00 -0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Kyrylo Tkachov , GCC Patches CC: Richard Earnshaw Subject: Re: [PATCH][ARM] PR target/64600 Fix another ICE with -mtune=xscale: properly sign-extend mask during constant splitting References: <54D0E6BF.8070804@arm.com> <000201d05299$cd873ad0$6895b070$@arm.com> <000401d055db$d56f8a00$804e9e00$@arm.com> In-Reply-To: <000401d055db$d56f8a00$804e9e00$@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2015-03/txt/msg00720.txt.bz2 On 03/03/15 17:59, Kyrylo Tkachov wrote: > > >> -----Original Message----- >> From: Kyrylo Tkachov >> Sent: 27 February 2015 14:30 >> To: Kyrylo Tkachov; GCC Patches >> Cc: Ramana Radhakrishnan; Richard Earnshaw >> Subject: RE: [PATCH][ARM] PR target/64600 Fix another ICE with - >> mtune=xscale: properly sign-extend mask during constant splitting >> >> On 03/02/15 15:18, Kyrill Tkachov wrote: >>> Hi all, >>> >>> The ICE in this PR occurs when -mtune=xscale triggers a particular >>> path through arm_gen_constant during expand that creates a 0xfffff00f >>> mask but for a 64-bit HOST_WIDE_INT doesn't sign extend it into >>> 0xfffffffffffff00f that signifies the required -4081. It leaves it as >>> 0xfffff00f (4294963215) that breaks when later combine tries to >>> perform an SImode bitwise AND using the wide-int machinery. >>> >>> I think the correct approach here is to use trunc_int_for_mode that >>> correctly sign-extends the constant so that it is properly represented >>> by a HOST_WIDE_INT for the required mode. >>> >>> Bootstrapped and tested arm-none-linux-gnueabihf with -mtune=xscale in >>> BOOT_CFLAGS. >>> >>> The testcase triggers for -mcpu=xscale and all slowmul targets because >>> they are the only ones that have the constant_limit tune parameter set >>> to anything >1 which is required to follow this particular path >>> through arm_split_constant. Also, the rtx costs can hide this ICE >>> sometimes. >>> >>> Ok for trunk? >>> >>> Thanks, >>> Kyrill >>> >>> 2015-02-03 Kyrylo Tkachov >>> >>> PR target/64600 >>> * config/arm/arm.c (arm_gen_constant, AND case): Call >>> trunc_int_for_mode when constructing AND mask. >>> >>> 2015-02-03 Kyrylo Tkachov >>> >>> PR target/64600 >>> * gcc.target/arm/pr64600_1.c: New test. >>> arm-xscale-wide.patch >>> commit 52388a359dd65276bccfac499a2fd9e406fbe1a8 >>> Author: Kyrylo Tkachov >>> Date: Tue Jan 20 11:21:34 2015 +0000 >>> >>> [ARM] Fix ICE due to arm_gen_constant not sign_extending >>> >>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index >>> db4834b..d0f3a52 100644 >>> --- a/gcc/config/arm/arm.c >>> +++ b/gcc/config/arm/arm.c >>> @@ -4709,19 +4709,20 @@ arm_gen_constant (enum rtx_code code, >>> machine_mode mode, rtx cond, >>> >>> if ((remainder | shift_mask) != 0xffffffff) >>> { >>> + HOST_WIDE_INT new_val >>> + = trunc_int_for_mode (remainder | shift_mask, mode); >> >> Offlist, Richard mentioned that trunc_int_for_mode may pessimize codegen >> for HImode values due to excessive setting of bits and using >> ARM_SIGN_EXTEND might be preferable. >> I've tried that and it does fix the ICE and goes through testing ok. Bootstrap >> still ongoing. >> I didn't perform any code quality investigation. Richard, are there any >> particular code sequences that you'd like us to investigate here? >> > > Here's the alternative version using ARM_SIGN_EXTEND if you want to have a look. > Thanks, > Kyrill > > > 2015-03-03 Kyrylo Tkachov > > PR target/64600 > * config/arm/arm.c (arm_gen_constant, AND case): Use > ARM_SIGN_EXTEND when constructing AND mask. > > 2015-03-03 Kyrylo Tkachov > > PR target/64600 > * gcc.target/arm/pr64600_1.c: New test. > >> Thanks, >> Kyrill This is OK. Let's take the ARM_SIGN_EXTEND version instead of the other one given what Richard says. regards Ramana >> >>> >>> + >>> if (generate) >>> { >>> rtx new_src = subtargets ? gen_reg_rtx (mode) : target; >>> - insns = arm_gen_constant (AND, mode, cond, >>> - remainder | shift_mask, >>> + insns = arm_gen_constant (AND, SImode, cond, new_val, >>> new_src, source, subtargets, 1); >>> source = new_src; >>> } >>> else >>> { >>> rtx targ = subtargets ? NULL_RTX : target; >>> - insns = arm_gen_constant (AND, mode, cond, >>> - remainder | shift_mask, >>> + insns = arm_gen_constant (AND, mode, cond, new_val, >>> targ, source, subtargets, 0); >>> } >>> } >>> @@ -4744,12 +4745,13 @@ arm_gen_constant (enum rtx_code code, >>> machine_mode mode, rtx cond, >>> >>> if ((remainder | shift_mask) != 0xffffffff) >>> { >>> + HOST_WIDE_INT new_val >>> + = trunc_int_for_mode (remainder | shift_mask, mode); >>> if (generate) >>> { >>> rtx new_src = subtargets ? gen_reg_rtx (mode) : target; >>> >>> - insns = arm_gen_constant (AND, mode, cond, >>> - remainder | shift_mask, >>> + insns = arm_gen_constant (AND, mode, cond, new_val, >>> new_src, source, subtargets, 1); >>> source = new_src; >>> } >>> @@ -4757,8 +4759,7 @@ arm_gen_constant (enum rtx_code code, >> machine_mode mode, rtx cond, >>> { >>> rtx targ = subtargets ? NULL_RTX : target; >>> >>> - insns = arm_gen_constant (AND, mode, cond, >>> - remainder | shift_mask, >>> + insns = arm_gen_constant (AND, mode, cond, new_val, >>> targ, source, subtargets, 0); >>> } >>> } >>> diff --git a/gcc/testsuite/gcc.target/arm/pr64600_1.c >>> b/gcc/testsuite/gcc.target/arm/pr64600_1.c >>> new file mode 100644 >>> index 0000000..6ba3fa2 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/arm/pr64600_1.c >>> @@ -0,0 +1,15 @@ >>> +/* { dg-do compile } */ >>> +/* { dg-options "-O2 -mtune=xscale" } */ >>> + >>> +typedef unsigned int speed_t; >>> +typedef unsigned int tcflag_t; >>> + >>> +struct termios { >>> + tcflag_t c_cflag; >>> +}; >>> + >>> +speed_t >>> +cfgetospeed (const struct termios *tp) { >>> + return tp->c_cflag & 010017; >>> +} >> >