From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28071 invoked by alias); 16 Mar 2015 13:15:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 28056 invoked by uid 89); 16 Mar 2015 13:15:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pd0-f175.google.com Received: from mail-pd0-f175.google.com (HELO mail-pd0-f175.google.com) (209.85.192.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 16 Mar 2015 13:15:50 +0000 Received: by pdbop1 with SMTP id op1so58171283pdb.2 for ; Mon, 16 Mar 2015 06:15:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type; bh=NknpXhs/MRx1W6F3uPGzDJQA7I6arP47V2HaG5OGIuw=; b=XitS4MvYj8xo0xu6Y2TEX9oEmPqL1JzN3IG3Mjxh7bcR5zNKudG59YWBxHH401P3QD rR3CH4LrWCCOEWI3RQEXZN/DFr0SAB+kyCb1IBdO19/He2D0/lK4nxsesJxtgWyxIA30 Gyw7HLfpiN977DBux180xYeuEIBYTKv8M7FPzYvGP/dsKK8pwQhh3m/vmpjnzM8rl44L jjLOM6E0+dNL/enC4624kqvMIqxQJep0METbdZ76ct1cSNU36KoJR/Eqq6vG2rW536V4 I2bhSTXODDGqfsTEBuTLIFwHyktraC2LFNkaSbspTrH1LJOBpG/pmipmcVZ61b3XOOSj QKvQ== X-Gm-Message-State: ALoCoQkLPOg4bgR4G9PVpEp37wsQovnz/iavJ8geqmvOe/wTR9vSWqFN2ks5Q0RDEK1CPC0+LaDY X-Received: by 10.66.233.194 with SMTP id ty2mr79012198pac.4.1426511747842; Mon, 16 Mar 2015 06:15:47 -0700 (PDT) Received: from [10.1.1.4] (58-6-183-210.dyn.iinet.net.au. [58.6.183.210]) by mx.google.com with ESMTPSA id nw3sm17351372pdb.71.2015.03.16.06.15.43 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Mar 2015 06:15:47 -0700 (PDT) Message-ID: <5506D77B.5060909@linaro.org> Date: Mon, 16 Mar 2015 13:15:00 -0000 From: Kugan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Kyrill Tkachov , "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft , Richard Earnshaw , Jim Wilson Subject: Re: [AArch64][PR65375] Fix RTX cost for vector SET References: <55066BCC.4010900@linaro.org> <5506AA24.3050108@arm.com> <5506CD7A.7030109@linaro.org> In-Reply-To: <5506CD7A.7030109@linaro.org> Content-Type: multipart/mixed; boundary="------------060106050704060608060406" X-IsSubscribed: yes X-SW-Source: 2015-03/txt/msg00821.txt.bz2 This is a multi-part message in MIME format. --------------060106050704060608060406 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Content-length: 1713 On 16/03/15 23:32, Kugan wrote: >>> lower-subreg.c:compute_costs() only cares about the cost of a (set (reg) >>> (const_int )) move but I think the intention, at least for now, is to >>> return extra_cost->vect.alu for all the vector operations. >> >> Almost, what we want at the moment is COSTS_N_INSNS (1) + >> extra_cost->vect.alu > > Thanks Kyrill for the review. > >>> Regression tested on aarch64-linux-gnu with no new regression. Is this >>> OK for trunk? >> >> Are you sure it's a (set (reg) (const_int)) that's being costed here? I >> thought for moves into vecto registers it would be a (set (reg) >> (const_vector)) which we don't handle in our rtx costs currently. I >> think the correct approach would be to extend the aarch64_rtx_costs >> switch statement to handle the CONST_VECT case. I believe you can use >> aarch64_simd_valid_immediate to check whether x is a valid immediate for >> a simd instruction and give it a cost of extra_cost->vect.alu. The logic >> should be similar to the CONST_INT case. > > Sorry about the (set (reg) (const_int)) above. But the actual RTL that > is being split at 220r.subreg2 is > > (insn 11 10 12 2 (set (subreg:V4SF (reg/v:OI 77 [ __o ]) 0) > (subreg:V4SF (reg/v:OI 73 [ __o ]) 0)) > /home/kugan/work/builds/gcc-fsf-gcc/tools/lib/gcc/aarch64-none-linux-gnu/5.0.0/include/arm_neon.h:22625 > 800 {*aarch64_simd_movv4sf} > (nil)) > > And also, if we return RTX cost above COSTS_N_INSNS (1), it will be > split and it dosent recover from there. Therefore we need something like > the below to prevent that happening. > Hi Kyrill, How about the attached patch? It is similar to what is currently done for scalar register move. Thanks, Kugan --------------060106050704060608060406 Content-Type: text/plain; charset=UTF-8; name="p.txt" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="p.txt" Content-length: 964 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index cba3c1a..b9db3ac 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5544,10 +5544,17 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED, /* Fall through. */ case REG: + if (VECTOR_MODE_P (GET_MODE (op0)) && REG_P (op1)) + { + /* The cost is 1 per register copied. */ + int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1) + / GET_MODE_SIZE (V4SImode); + *cost = COSTS_N_INSNS (n_minus_1 + 1); + } /* const0_rtx is in general free, but we will use an instruction to set a register to 0. */ - if (REG_P (op1) || op1 == const0_rtx) - { + else if (REG_P (op1) || op1 == const0_rtx) + { /* The cost is 1 per register copied. */ int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1) / UNITS_PER_WORD; --------------060106050704060608060406--