From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by sourceware.org (Postfix) with ESMTPS id 4019938708CB for ; Wed, 10 Mar 2021 11:34:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4019938708CB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=adacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=botcazou@adacore.com Received: by mail-wr1-x42e.google.com with SMTP id w11so22932120wrr.10 for ; Wed, 10 Mar 2021 03:34:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=44HX6Sec2XcJMTWPXy8ivgllBsCue8TIlxHGinXATmY=; b=PYCsXAnIplpo9kiaS85nMdsdFYuC5Hse1kIZt6W2b50fdKMHZli7drstur7Qp0TGcI mCZLDp9NjNefMkUEPXuywFtLARKK5D6Upbom6p3xXihsrQQ5FX4P03nAu9WdZmtWUvCW kq1OOTetFL6BswUVntXuC/3cFJUvFXA3Cr/Ce/Qi6VfWkdFUVO+mtr86CLhJfHITxJrE RfwfcxA7FYS9uApc/vwaKENY7K8ZAXCv+8pRnvLsAfdTNd4Vtr495wdDd8MeDiRf61JI lTwxWUKBb9gen54bepONuAmRHyOaSBQYjn/cNSElRE5cr/OXit0BuCRKsaPrMc4ZwBA1 KDyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=44HX6Sec2XcJMTWPXy8ivgllBsCue8TIlxHGinXATmY=; b=Ws/yMiOKVdQ3vJdHU4RRRG0dgEH3l2IcsCOBIgJqm/Z9QMG1tkTCG6ABvvbUtvCvNt xj0k3CGUDF1VHdebNq9XtKUfn0c+PFriOG0P7PtNvofD6zdhKPwRaw2v0ovqLM4veTS6 /PRhhKKgw/zMFoaU/OVhYeibesP4321hOXShzfrMCZtvZYz6O2faZoVYqyFn06ZcBDU9 dL/FPFYZVA4IWGTW1Z3vNJafuxcWBg9/NaotjKs5Vy0CkPSDLRn5DS0cSk7O34bKPh59 xVtuDsxOEyi/YQdymxArTQuYZzmRjTsZnI2+0k7Xi50K7jp0dKnM3vNmNa2Q802uCDYg Hl1w== X-Gm-Message-State: AOAM532GE1XMwc4zICkdbHbtmnZ1VzjeZ69bHZbn7mGM9dI6W2fFU7tl 4RjkkhDmdT9pjQUpDpMOF4fnRcpkDwAXgbaE X-Google-Smtp-Source: ABdhPJzQe9tZdmb6efzo80kJPbjm/kXuH3iwTNT4od53yYkaJgkcrDdOIXpLitrV6/NFdKgDq98/jA== X-Received: by 2002:a5d:4708:: with SMTP id y8mr3175276wrq.382.1615376091284; Wed, 10 Mar 2021 03:34:51 -0800 (PST) Received: from fomalhaut.localnet ([2a01:e0a:41b:84f0:cf71:f5e0:b050:bede]) by smtp.gmail.com with ESMTPSA id h10sm30314887wrp.22.2021.03.10.03.34.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Mar 2021 03:34:50 -0800 (PST) From: Eric Botcazou X-Google-Original-From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Fix miscompilation of Ada runtime in 64-bit mode Date: Wed, 10 Mar 2021 12:34:50 +0100 Message-ID: <5535387.om13OTu5Gl@fomalhaut> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart1921776.ZVOMPiBcv0" Content-Transfer-Encoding: 7Bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Mar 2021 11:34:55 -0000 This is a multi-part message in MIME format. --nextPart1921776.ZVOMPiBcv0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Returning a REGMODE_NATURAL_SIZE of 4 for DFmode in 64-bit mode is asking for trouble because sub-word SUBREGs are always treated differently than the others, in particular by the register allocator. Bootstrapped/regtested on SPARC64/Linux and SPARC/Solaris, applied on the mainline. 2021-03-10 Eric Botcazou * config/sparc/sparc.c (sparc_regmode_natural_size): Return 4 for float and vector integer modes only if the mode is not larger. -- Eric Botcazou --nextPart1921776.ZVOMPiBcv0 Content-Disposition: attachment; filename="p.diff" Content-Transfer-Encoding: 7Bit Content-Type: text/x-patch; charset="utf-8"; name="p.diff" diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index f3557936114..f1504172022 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -13585,23 +13585,18 @@ sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) emit_insn (gen_rtx_SET (operands[0], bshuf)); } -/* On sparc, any mode which naturally allocates into the float +/* On the SPARC, any mode which naturally allocates into the single float registers should return 4 here. */ unsigned int sparc_regmode_natural_size (machine_mode mode) { - int size = UNITS_PER_WORD; + const enum mode_class cl = GET_MODE_CLASS (mode); - if (TARGET_ARCH64) - { - enum mode_class mclass = GET_MODE_CLASS (mode); - - if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT) - size = 4; - } + if ((cl == MODE_FLOAT || cl == MODE_VECTOR_INT) && GET_MODE_SIZE (mode) <= 4) + return 4; - return size; + return UNITS_PER_WORD; } /* Implement TARGET_HARD_REGNO_NREGS. --nextPart1921776.ZVOMPiBcv0--