From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18696 invoked by alias); 22 Apr 2015 16:58:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 18687 invoked by uid 89); 22 Apr 2015 16:58:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Apr 2015 16:58:09 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-17.uk.mimecast.lan; Wed, 22 Apr 2015 17:58:07 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 22 Apr 2015 17:58:06 +0100 Message-ID: <5537D31E.9060900@arm.com> Date: Wed, 22 Apr 2015 16:58:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Kyrylo Tkachov , Richard Earnshaw Subject: Re: [PATCH 2/2][ARM] PR/63870: Add a __builtin_lane_check References: <54B94342.3070607@arm.com> <54B949D0.3010509@arm.com> In-Reply-To: <54B949D0.3010509@arm.com> X-MC-Unique: iPe-237uSwSx2e95uZhdIg-1 Content-Type: multipart/mixed; boundary="------------090401060404000209080509" X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg01334.txt.bz2 This is a multi-part message in MIME format. --------------090401060404000209080509 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 1277 Ping (https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01436.html). These are required for float16 patches posted at=20 https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01332.html Bootstrapped + check-gcc on arm-none-linux-gnueabihf. Alan Lawrence wrote: > This parallels the present form of __builtin_aarch64_im_lane_boundsi, and= allows=20 > to check lane indices for intrinsics that can otherwise be written in ter= ms of=20 > GCC vector extensions. >=20 > The new builtin is not used in this patch but is used in my series of flo= at16_t=20 > intrinsics (https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01434.html), an= d at=20 > some point in the future we should rewrite existing intrinsics (for other= types)=20 > to this form too, but I'm leaving that for a later patch series :). >=20 > Cross-tested check-gcc on arm-none-eabi > Bootstrapped on arm-none-linux-gnueabihf cortex-a15 >=20 > gcc/ChangeLog: >=20 > * config/arm/arm-builtins.c (enum arm_builtins): > Add ARM_BUILTIN_NEON_BASE and ARM_BUILTIN_NEON_LANE_CHECK. > (ARM_BUILTIN_NEON_BASE): Rename macro to.... > (ARM_BUILTIN_NEON_PATTERN_START): ...this. > (arm_init_neon_builtins): Register __builtin_arm_lane_check. > (arm_expand_neon_builtin): Handle ARM_BUILTIN_NEON_LANE_CHECK. --------------090401060404000209080509 Content-Type: text/x-patch; name=arm_builtin_lane_check.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="arm_builtin_lane_check.patch" Content-length: 2937 commit 3d5f2b80dc4527b4874bff458bb047946322028f Author: Alan Lawrence Date: Mon Dec 8 18:36:30 2014 +0000 Add __builtin_arm_lane_check diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 20d2198..3de2be7 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -546,12 +546,16 @@ enum arm_builtins #undef CRYPTO2 #undef CRYPTO3 =20 + ARM_BUILTIN_NEON_BASE, + ARM_BUILTIN_NEON_LANE_CHECK =3D ARM_BUILTIN_NEON_BASE, + #include "arm_neon_builtins.def" =20 ARM_BUILTIN_MAX }; =20 -#define ARM_BUILTIN_NEON_BASE (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_= data)) +#define ARM_BUILTIN_NEON_PATTERN_START \ + (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data)) =20 #undef CF #undef VAR1 @@ -910,7 +914,7 @@ arm_init_simd_builtin_scalar_types (void) static void arm_init_neon_builtins (void) { - unsigned int i, fcode =3D ARM_BUILTIN_NEON_BASE; + unsigned int i, fcode =3D ARM_BUILTIN_NEON_PATTERN_START; =20 arm_init_simd_builtin_types (); =20 @@ -920,6 +924,15 @@ arm_init_neon_builtins (void) system. */ arm_init_simd_builtin_scalar_types (); =20 + tree lane_check_fpr =3D build_function_type_list (void_type_node, + intSI_type_node, + intSI_type_node, + NULL); + arm_builtin_decls[ARM_BUILTIN_NEON_LANE_CHECK] =3D + add_builtin_function ("__builtin_arm_lane_check", lane_check_fpr, + ARM_BUILTIN_NEON_LANE_CHECK, BUILT_IN_MD, + NULL, NULL_TREE); + for (i =3D 0; i < ARRAY_SIZE (neon_builtin_data); i++, fcode++) { bool print_type_signature_p =3D false; @@ -2183,14 +2196,28 @@ arm_expand_neon_args (rtx target, machine_mode map_= mode, int fcode, return target; } =20 -/* Expand a Neon builtin. These are "special" because they don't have symb= olic +/* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds. + Most of these are "special" because they don't have symbolic constants defined per-instruction or per instruction-variant. Instead, = the required info is looked up in the table neon_builtin_data. */ static rtx arm_expand_neon_builtin (int fcode, tree exp, rtx target) { + if (fcode =3D=3D ARM_BUILTIN_NEON_LANE_CHECK) + { + tree nlanes =3D CALL_EXPR_ARG (exp, 0); + gcc_assert (TREE_CODE (nlanes) =3D=3D INTEGER_CST); + rtx lane_idx =3D expand_normal (CALL_EXPR_ARG (exp, 1)); + if (CONST_INT_P (lane_idx)) + neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp); + else + error ("%Klane index must be a constant immediate", exp); + /* Don't generate any RTL. */ + return const0_rtx; + } + neon_builtin_datum *d =3D - &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE]; + &neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START]; enum insn_code icode =3D d->code; builtin_arg args[SIMD_MAX_BUILTIN_ARGS]; int num_args =3D insn_data[d->code].n_operands; --------------090401060404000209080509--