From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 68587 invoked by alias); 22 Apr 2015 17:21:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 68574 invoked by uid 89); 22 Apr 2015 17:21:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.3 required=5.0 tests=AWL,BAYES_50,KAM_LOTSOFHASH,SPF_PASS autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Apr 2015 17:21:07 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-12.uk.mimecast.lan; Wed, 22 Apr 2015 18:21:04 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 22 Apr 2015 18:21:04 +0100 Message-ID: <5537D880.9020708@arm.com> Date: Wed, 22 Apr 2015 17:21:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 10/14][AArch64] Add vcvt(_high)?_f32_f16 intrinsics In-Reply-To: <5537D241.1000606@arm.com> X-MC-Unique: YOGC2QzgRpaxbO2rligHSw-1 Content-Type: multipart/mixed; boundary="------------020707080009060207060906" X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg01345.txt.bz2 This is a multi-part message in MIME format. --------------020707080009060207060906 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 3382 This adds the two remaining widening intrinsics, first adding patterns in=20 aarch64-simd.md, then entries in aarch64-simd-builtins.def, and finally=20 intrinsics in arm_neon.h . Note this changes the vector indices present in the RTL on bigendian for fl= oat=20 vec_unpacks, to be the same as for integer vec_unpacks. This appears consis= tent=20 with the usage of VEC_UNPACK_(FLOAT_)?EXPR in tree-vect-stmts.c, which uses= a=20 different EXPR for the same half of the vector depending on endianness. I w= as=20 not able to construct a testcase where the RTL here mattered (i.e. where th= e RTL=20 was constant-folded, but the tree had not been), but the correctness can be= seen=20 from a testcase: double d[4]; void bar (float *f) { for (int i =3D 0; i < 4; i++) d[i] =3D f[i]; } which used to produced as final RTL (-O3) (insn:TI 8 10 12 (set (reg:V2DF 33 v1 [orig:78 vect__9.19 ] [78]) (float_extend:V2DF (vec_select:V2SF (reg:V4SF 32 v0 [orig:77 MEM[(= float=20 *)f_6(D)] ] [77]) (parallel [ (const_int 2 [0x2]) (const_int 3 [0x3]) ])))) test.c:40 1274 {vec_unpacks_hi_v4sf} (expr_list:REG_EQUIV (mem/c:V2DF (reg/f:DI 0 x0 [79]) [2 MEM[(double= =20 *)&d]+0 S16 A64]) (nil))) (insn:TI 12 8 11 (set (reg:V2DF 32 v0 [orig:81 vect__9.19 ] [81]) (float_extend:V2DF (vec_select:V2SF (reg:V4SF 32 v0 [orig:77 MEM[(= float=20 *)f_6(D)] ] [77]) (parallel [ (const_int 0 [0]) (const_int 1 [0x1]) ])))) test.c:40 1272 {vec_unpacks_lo_v4sf} (expr_list:REG_EQUIV (mem/c:V2DF (plus:DI (reg/f:DI 0 x0 [79]) (const_int 16 [0x10])) [2 MEM[(double *)&d + 16B]+0 S16 A6= 4]) (nil))) (insn:TI 11 12 15 (set (mem/c:V2DF (reg/f:DI 0 x0 [79]) [2 MEM[(double *)&d= ]+0=20 S16 A64]) (reg:V2DF 33 v1 [orig:78 vect__9.19 ] [78])) test.c:40 808=20 {*aarch64_simd_movv2df} (expr_list:REG_DEAD (reg:V2DF 33 v1 [orig:78 vect__9.19 ] [78]) (nil))) (insn:TI 15 11 22 (set (mem/c:V2DF (plus:DI (reg/f:DI 0 x0 [79]) (const_int 16 [0x10])) [2 MEM[(double *)&d + 16B]+0 S16 A6= 4]) (reg:V2DF 32 v0 [orig:81 vect__9.19 ] [81])) test.c:40 808=20 {*aarch64_simd_movv2df} (expr_list:REG_DEAD (reg:V2DF 32 v0 [orig:81 vect__9.19 ] [81]) i.e. apparently storing vector elements 2 and 3 to the address of d, and el= ems=20 0+1 to address (d+16). Of course this was flipped back again to be correct = at=20 assembly time, but following this patch the RTL indices are also correct (e= lems=20 0+1 to address d, elems 2+3 to address d+16). gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_, aarch64_simd_vec_unpacks_hi_): New insn. (vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn. (vec_unpacks_lo_, vec_unpacks_hi_): New expand. (aarch64_float_extend_lo_v2df): Rename to... (aarch64_float_extend_lo_): this, using VDF and so adding V4SF. * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf. (float_extend_lo): Add v4sf. * config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New. * config/aarch64/iterators.md (VQ_HSF): New iterator. (VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF. (Vwide): New mode_attr. --------------020707080009060207060906 Content-Type: text/x-patch; name=10_aarch64_vcvt_high_f32_f16.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="10_aarch64_vcvt_high_f32_f16.patch" Content-length: 6963 diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarc= h64/aarch64-simd-builtins.def index 604bfa20bf838ee04ef0e1dda0b47b55dbdd82a6..1eefb37c2eba37aecee6ccae100= 274c5a8cc5ae3 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -360,11 +360,11 @@ only ever used for the int64x1_t intrinsic, there is no scalar versio= n. */ BUILTIN_VALLDI (UNOP, abs, 2) =20 - VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) + VAR2 (UNOP, vec_unpacks_hi_, 10, v4sf, v8hf) VAR1 (BINOP, float_truncate_hi_, 0, v4sf) VAR1 (BINOP, float_truncate_hi_, 0, v8hf) =20=20=20 - VAR1 (UNOP, float_extend_lo_, 0, v2df) + VAR2 (UNOP, float_extend_lo_, 0, v2df, v4sf) BUILTIN_VDF (UNOP, float_truncate_lo_, 0) =20=20=20 /* Implemented by aarch64_ld1. */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md index 161396a331cab777bb2108f86c39b74557be4abc..17a5d5f8c757833a7ed387083f8= 076af2c8cad66 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1677,36 +1677,57 @@ =20 ;; Float widening operations. =20 -(define_insn "vec_unpacks_lo_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "=3Dw") - (float_extend:V2DF - (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "w") - (parallel [(const_int 0) (const_int 1)]) - )))] +(define_insn "aarch64_simd_vec_unpacks_lo_" + [(set (match_operand: 0 "register_operand" "=3Dw") + (float_extend: (vec_select: + (match_operand:VQ_HSF 1 "register_operand" "w") + (match_operand:VQ_HSF 2 "vect_par_cnst_lo_half" "") + )))] "TARGET_SIMD" - "fcvtl\\t%0.2d, %1.2s" + "fcvtl\\t%0., %1." [(set_attr "type" "neon_fp_cvt_widen_s")] ) =20 -(define_insn "aarch64_float_extend_lo_v2df" - [(set (match_operand:V2DF 0 "register_operand" "=3Dw") - (float_extend:V2DF - (match_operand:V2SF 1 "register_operand" "w")))] +(define_expand "vec_unpacks_lo_" + [(match_operand: 0 "register_operand" "") + (match_operand:VQ_HSF 1 "register_operand" "")] "TARGET_SIMD" - "fcvtl\\t%0.2d, %1.2s" + { + rtx p =3D aarch64_simd_vect_par_cnst_half (mode, false); + emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], + operands[1], p)); + DONE; + } +) + +(define_insn "aarch64_simd_vec_unpacks_hi_" + [(set (match_operand: 0 "register_operand" "=3Dw") + (float_extend: (vec_select: + (match_operand:VQ_HSF 1 "register_operand" "w") + (match_operand:VQ_HSF 2 "vect_par_cnst_hi_half" "") + )))] + "TARGET_SIMD" + "fcvtl2\\t%0., %1." [(set_attr "type" "neon_fp_cvt_widen_s")] ) =20 -(define_insn "vec_unpacks_hi_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "=3Dw") - (float_extend:V2DF - (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "w") - (parallel [(const_int 2) (const_int 3)]) - )))] +(define_expand "vec_unpacks_hi_" + [(match_operand: 0 "register_operand" "") + (match_operand:VQ_HSF 1 "register_operand" "")] + "TARGET_SIMD" + { + rtx p =3D aarch64_simd_vect_par_cnst_half (mode, true); + emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], + operands[1], p)); + DONE; + } +) +(define_insn "aarch64_float_extend_lo_" + [(set (match_operand: 0 "register_operand" "=3Dw") + (float_extend: + (match_operand:VDF 1 "register_operand" "w")))] "TARGET_SIMD" - "fcvtl2\\t%0.2d, %1.4s" + "fcvtl\\t%0, %1" [(set_attr "type" "neon_fp_cvt_widen_s")] ) =20 diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 424e2807ca80ea152df94cccba0bf36c7f443c2c..ecfabd2b1282f48150ef5193b55= c6ba2b9cbfce3 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -6026,10 +6026,6 @@ vaddlvq_u32 (uint32x4_t a) result; \ }) =20 -/* vcvt_f32_f16 not supported */ - -/* vcvt_high_f32_f16 not supported */ - #define vcvt_n_f32_s32(a, b) \ __extension__ \ ({ \ @@ -13420,6 +13416,12 @@ vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __= b) =20 /* vcvt (float -> double). */ =20 +__extension__ static __inline float32x4_t __attribute__ ((__always_inline_= _)) +vcvt_f32_f16 (float16x4_t __a) +{ + return __builtin_aarch64_float_extend_lo_v4sf (__a); +} + __extension__ static __inline float64x2_t __attribute__ ((__always_inline_= _)) vcvt_f64_f32 (float32x2_t __a) { @@ -13427,6 +13429,12 @@ vcvt_f64_f32 (float32x2_t __a) return __builtin_aarch64_float_extend_lo_v2df (__a); } =20 +__extension__ static __inline float32x4_t __attribute__ ((__always_inline_= _)) +vcvt_high_f32_f16 (float16x8_t __a) +{ + return __builtin_aarch64_vec_unpacks_hi_v8hf (__a); +} + __extension__ static __inline float64x2_t __attribute__ ((__always_inline_= _)) vcvt_high_f64_f32 (float32x4_t __a) { diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators= .md index ad043931705d10cccaaeb2a74ad8320b0305b435..d3207d3a41d00aba4e67b4319c0= d5a0edbf602b6 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -91,6 +91,9 @@ ;; Vector single Float modes. (define_mode_iterator VDQSF [V2SF V4SF]) =20 +;; Quad vector Float modes with half/single elements. +(define_mode_iterator VQ_HSF [V8HF V4SF]) + ;; Modes suitable to use as the return type of a vcond expression. (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) =20 @@ -490,14 +493,18 @@ (V2SI "V2DI") (V16QI "V8HI")=20 (V8HI "V4SI") (V4SI "V2DI") (HI "SI") (SI "DI") + (V8HF "V4SF") (V4SF "V2DF") (V4HF "V4SF") (V2SF "V2DF")] - ) =20 -;; Widened mode register suffixes for VD_BHSI/VQW. +;; Widened modes of vector modes, lowercase +(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")]) + +;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") (V2SI "2d") (V16QI "8h")=20 - (V8HI "4s") (V4SI "2d")]) + (V8HI "4s") (V4SI "2d") + (V8HF "4s") (V4SF "2d")]) =20 ;; Widened mode register suffixes for VDW/VQW. (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") @@ -506,9 +513,10 @@ (V4HF ".4s") (V2SF ".2d") (SI "") (HI "")]) =20 -;; Lower part register suffixes for VQW. +;; Lower part register suffixes for VQW/VQ_HSF. (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") - (V4SI "2s")]) + (V4SI "2s") (V8HF "4h") + (V4SF "2s")]) =20 ;; Define corresponding core/FP element mode for each vector mode. (define_mode_attr vw [(V8QI "w") (V16QI "w") --------------020707080009060207060906--