From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 121547 invoked by alias); 22 Apr 2015 17:38:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 121520 invoked by uid 89); 22 Apr 2015 17:38:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=AWL,BAYES_50,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Apr 2015 17:38:54 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-6.uk.mimecast.lan; Wed, 22 Apr 2015 18:38:51 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 22 Apr 2015 18:38:50 +0100 Message-ID: <5537DCAA.70001@arm.com> Date: Wed, 22 Apr 2015 17:38:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Christophe Lyon Subject: [PATCH 14/14][ARM/AArch64 testsuite] Test float16_t vcvt_* intrinsics In-Reply-To: <5537D241.1000606@arm.com> X-MC-Unique: JrgeSHjGS1qSEDmeb6ZaBw-1 Content-Type: multipart/mixed; boundary="------------030507030203070603000206" X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg01349.txt.bz2 This is a multi-part message in MIME format. --------------030507030203070603000206 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 805 This adds a test of vcvt_f32_f16 and vcvt_f16_f32, also vcvt_high_f32_f16 a= nd=20 vcvt_high_f16_f32. On ARM, we pass additional option -mfpu=3Dneon-fp16 to the compiler (possib= le=20 following patch 2/3). The compiler is already receiving an option such as=20 -mfpu=3Dneon or -mfpu=3Dcrypto-neon-fp-armv8, but passing neon-fp16 as well= as=20 either of those appears to do no harm, and turns on the superset of all -mf= pu=20 options, as desired. On AArch64, we additionally test vcvt_high_f32_f16 and vcvt_high_f16_f32; t= hese=20 are not tested on ARM as the relevant intrinsics do not exist in 32-bit sta= te. Passing on aarch64_be-none-elf, aarch64-none-elf, arm-none-linux-gnueabi,=20 aarch64-none-linux-gnu. gcc/testsuite/ChangeLog: * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c: New. --------------030507030203070603000206 Content-Type: text/x-patch; name=14_advsimd_vcvt.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="14_advsimd_vcvt.patch" Content-length: 3362 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c= b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..a346b3d72e13d5b2028de5ae7b8= 8f910dcb3f862 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c @@ -0,0 +1,96 @@ +/* { dg-additional-options "-mfpu=3Dneon-fp16" { target { arm*-*-* } } } */ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include + +/* Expected results for vcvt. */ +VECT_VAR_DECL (expected,hfloat,32,4) [] =3D { 0x41800000, 0x41700000, + 0x41600000, 0x41500000 }; +VECT_VAR_DECL (expected,hfloat,16,4) [] =3D { 0x3e00, 0x4100, 0x4300, 0x44= 80 }; + +/* Expected results for vcvt_high_f32_f16. */ +VECT_VAR_DECL (expected_high,hfloat,32,4) [] =3D { 0xc1400000, 0xc1300000, + 0xc1200000, 0xc1100000 }; +/* Expected results for vcvt_high_f16_f32. */ +VECT_VAR_DECL (expected_high,hfloat,16,8) [] =3D { 0x4000, 0x4000, 0x4000,= 0x4000, + 0xcc00, 0xcb80, 0xcb00, 0xca80 }; + +void +exec_vcvt (void) +{ +#define TEST_MSG vcvt_f32_f16 + { + VECT_VAR_DECL (buffer_src, float, 16, 4) [] =3D { 16.0, 15.0, 14.0, 13= .0 }; + + DECL_VARIABLE (vector_src, float, 16, 4); + + VLOAD (vector_src, buffer_src, , float, f, 16, 4); + DECL_VARIABLE (vector_res, float, 32, 4) =3D + vcvt_f32_f16 (VECT_VAR (vector_src, float, 16, 4)); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); + } +#undef TEST_MSG + + clean_results (); + +#define TEST_MSG vcvt_f16_f32 + { + VECT_VAR_DECL (buffer_src, float, 32, 4) [] =3D { 1.5, 2.5, 3.5, 4.5 }; + DECL_VARIABLE (vector_src, float, 32, 4); + + VLOAD (vector_src, buffer_src, q, float, f, 32, 4); + DECL_VARIABLE (vector_res, float, 16, 4) =3D + vcvt_f16_f32 (VECT_VAR (vector_src, float, 32, 4)); + vst1_f16 (VECT_VAR (result, float, 16, 4), + VECT_VAR (vector_res, float, 16 ,4)); + + CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, ""); + } +#undef TEST_MSG + +#ifdef __ARM_64BIT_STATE + clean_results (); + +#define TEST_MSG "vcvt_high_f32_f16" + { + DECL_VARIABLE (vector_src, float, 16, 8); + VLOAD (vector_src, buffer, q, float, f, 16, 8); + DECL_VARIABLE (vector_res, float, 32, 4); + VECT_VAR (vector_res, float, 32, 4) =3D + vcvt_high_f32_f16 (VECT_VAR (vector_src, float, 16, 8)); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected_high, ""); + } +#undef TEST_MSG + clean_results (); + +#define TEST_MSG "vcvt_high_f16_f32" + { + DECL_VARIABLE (vector_low, float, 16, 4); + VDUP (vector_low, , float, f, 16, 4, 2.0); + + DECL_VARIABLE (vector_src, float, 32, 4); + VLOAD (vector_src, buffer, q, float, f, 32, 4); + + DECL_VARIABLE (vector_res, float, 16, 8) =3D + vcvt_high_f16_f32 (VECT_VAR (vector_low, float, 16, 4), + VECT_VAR (vector_src, float, 32, 4)); + vst1q_f16 (VECT_VAR (result, float, 16, 8), + VECT_VAR (vector_res, float, 16, 8)); + + CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_high, ""); + } +#endif +} + +int +main (void) +{ + exec_vcvt (); + return 0; +} --------------030507030203070603000206--