From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10881 invoked by alias); 24 Apr 2015 15:41:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 10870 invoked by uid 89); 24 Apr 2015 15:41:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 24 Apr 2015 15:41:41 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-24.uk.mimecast.lan; Fri, 24 Apr 2015 16:41:38 +0100 Received: from [10.2.207.6] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 24 Apr 2015 16:41:38 +0100 Message-ID: <553A6431.8000101@arm.com> Date: Fri, 24 Apr 2015 15:41:00 -0000 From: Alex Velenko User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Kyrylo Tkachov , "gcc-patches@gcc.gnu.org" CC: Ramana Radhakrishnan Subject: Re: [PATCH] [AArch32] Additional bics patterns. References: <1429708361-25668-1-git-send-email-alex.velenko@arm.com> <000001d07d00$10179f80$3046de80$@arm.com> In-Reply-To: <000001d07d00$10179f80$3046de80$@arm.com> X-MC-Unique: wlYlIwW1QdKT6NTF1M_pBg-1 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg01516.txt.bz2 Hi, This patch adds rtl patterns to generate bics instructions with shift. Added attribute predicable_short_it since last respin. Done full regression run on arm-none-eabi and arm-none-gnueabihf. Bootstrapped on arm-none-gnueabihf. Is this patch ok? gcc/config 2015-04-24 Alex Velenko * arm/arm.md (andsi_not_shiftsi_si_scc): New pattern. * (andsi_not_shiftsi_si_scc_no_reuse): New pattern. gcc/testsuite 2015-04-24 Alex Velenko * gcc.target/arm/bics_1.c : New testcase. * gcc.target/arm/bics_2.c : New testcase. * gcc.target/arm/bics_3.c : New testcase. * gcc.target/arm/bics_4.c : New testcase. --- gcc/config/arm/arm.md | 44 +++++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/bics_1.c | 54=20 +++++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/bics_2.c | 57=20 +++++++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/bics_3.c | 41 +++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/bics_4.c | 49 ++++++++++++++++++++++++++++++ 5 files changed, 245 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/bics_1.c create mode 100644 gcc/testsuite/gcc.target/arm/bics_2.c create mode 100644 gcc/testsuite/gcc.target/arm/bics_3.c create mode 100644 gcc/testsuite/gcc.target/arm/bics_4.c diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 164ac13..9e774c1 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -2768,6 +2768,50 @@ (const_string "logic_shift_reg")))] ) +(define_insn "andsi_not_shiftsi_si_scc_no_reuse" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + (and:SI (not:SI (match_operator:SI 0 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rM")])) + (match_operand:SI 3 "s_register_operand" "r")) + (const_int 0))) + (clobber (match_scratch:SI 4 "=3Dr"))] + "TARGET_32BIT" + "bic%.%?\\t%4, %3, %1%S0" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "conds" "set") + (set_attr "shift" "1") + (set (attr "type") (if_then_else (match_operand 2=20 "const_int_operand" "") + (const_string "logic_shift_imm") + (const_string "logic_shift_reg")))] +) + +(define_insn "andsi_not_shiftsi_si_scc" + [(parallel [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + (and:SI (not:SI (match_operator:SI 0 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rM")])) + (match_operand:SI 3 "s_register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 4 "s_register_operand" "=3Dr") + (and:SI (not:SI (match_op_dup 0 + [(match_dup 1) + (match_dup 2)])) + (match_dup 3)))])] + "TARGET_32BIT" + "bic%.%?\\t%4, %3, %1%S0" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "conds" "set") + (set_attr "shift" "1") + (set (attr "type") (if_then_else (match_operand 2=20 "const_int_operand" "") + (const_string "logic_shift_imm") + (const_string "logic_shift_reg")))] +) + (define_insn "*andsi_notsi_si_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV diff --git a/gcc/testsuite/gcc.target/arm/bics_1.c=20 b/gcc/testsuite/gcc.target/arm/bics_1.c new file mode 100644 index 0000000..173eb89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bics_1.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ +/* { dg-require-effective-target arm32 } */ + +extern void abort (void); + +int +bics_si_test1 (int a, int b, int c) +{ + int d =3D a & ~b; + + /* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+" 2 } } */ + if (d =3D=3D 0) + return a + c; + else + return b + d + c; +} + +int +bics_si_test2 (int a, int b, int c) +{ + int d =3D a & ~(b << 3); + + /* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+, .sl \#3" 1 } } */ + if (d =3D=3D 0) + return a + c; + else + return b + d + c; +} + +int +main () +{ + int x; + + x =3D bics_si_test1 (29, ~4, 5); + if (x !=3D ((29 & 4) + ~4 + 5)) + abort (); + + x =3D bics_si_test1 (5, ~2, 20); + if (x !=3D 25) + abort (); + + x =3D bics_si_test2 (35, ~4, 5); + if (x !=3D ((35 & ~(~4 << 3)) + ~4 + 5)) + abort (); + + x =3D bics_si_test2 (96, ~2, 20); + if (x !=3D 116) + abort (); + + return 0; +} +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/bics_2.c=20 b/gcc/testsuite/gcc.target/arm/bics_2.c new file mode 100644 index 0000000..740d7c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bics_2.c @@ -0,0 +1,57 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ +/* { dg-require-effective-target arm32 } */ + +extern void abort (void); + +int +bics_si_test1 (int a, int b, int c) +{ + int d =3D a & ~b; + + /* { dg-final { scan-assembler-not "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+" } } */ + /* { dg-final { scan-assembler-times "bic\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+" 2 } } */ + if (d <=3D 0) + return a + c; + else + return b + d + c; +} + +int +bics_si_test2 (int a, int b, int c) +{ + int d =3D a & ~(b << 3); + + /* { dg-final { scan-assembler-not "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+, .sl \#3" } } */ + /* { dg-final { scan-assembler "bic\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+,=20 .sl \#3" } } */ + if (d <=3D 0) + return a + c; + else + return b + d + c; +} + +int +main () +{ + int x; + + x =3D bics_si_test1 (29, ~4, 5); + if (x !=3D ((29 & 4) + ~4 + 5)) + abort (); + + x =3D bics_si_test1 (5, ~2, 20); + if (x !=3D 25) + abort (); + + x =3D bics_si_test2 (35, ~4, 5); + if (x !=3D ((35 & ~(~4 << 3)) + ~4 + 5)) + abort (); + + x =3D bics_si_test2 (96, ~2, 20); + if (x !=3D 116) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/bics_3.c=20 b/gcc/testsuite/gcc.target/arm/bics_3.c new file mode 100644 index 0000000..e2b1c72 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bics_3.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ +/* { dg-require-effective-target arm32 } */ + +extern void abort (void); + +int +bics_si_test (int a, int b) +{ + if (a & ~b) + return 1; + else + return 0; +} + +int +bics_si_test2 (int a, int b) +{ + if (a & ~ (b << 2)) + return 1; + else + return 0; +} + +int +main (void) +{ + int a =3D 5; + int b =3D 5; + int c =3D 20; + if (bics_si_test (a, b)) + abort (); + if (bics_si_test2 (c, b)) + abort (); + return 0; +} + +/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+, .sl #2" 1 } } */ + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/bics_4.c=20 b/gcc/testsuite/gcc.target/arm/bics_4.c new file mode 100644 index 0000000..8f2faf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bics_4.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ +/* { dg-require-effective-target arm32 } */ + +extern void abort (void); + +int +bics_si_test1 (int a, int b, int c) +{ + if ((a & b) =3D=3D a) + return a; + else + return c; +} + +int +bics_si_test2 (int a, int b, int c) +{ + if ((a & b) =3D=3D b) + return b; + else + return c; +} + +int +main () +{ + int x; + x =3D bics_si_test1 (0xf00d, 0xf11f, 0); + if (x !=3D 0xf00d) + abort (); + + x =3D bics_si_test1 (0xf11f, 0xf00d, 0); + if (x !=3D 0) + abort (); + + x =3D bics_si_test2 (0xf00d, 0xf11f, 0); + if (x !=3D 0) + abort (); + + x =3D bics_si_test2 (0xf11f, 0xf00d, 0); + if (x !=3D 0xf00d) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+,=20 r\[0-9\]+" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ --=20 1.8.1.2