Hi all,

We currently have a pattern that will recognise a particular combination of shifts and bitwise-or
as an extr instruction. However, the order of the shifts inside the IOR doesn't have
canonicalisation rules (see rev16 pattern for similar stuff).
This means that for code like:

unsigned long
foo (unsigned long a, unsigned long b)
{
   return (a << 16) |  (b >> 48);
}

we will recognise the extr, but for the equivalent:
unsigned long
foo (unsigned long a, unsigned long b)
{
   return (b >> 48) | (a << 16);
}

we won't, and we'll emit three instructions.
This patch adds the pattern for the alternative order of shifts and allows us to generate
for the above the code:
foo:
         extr    x0, x0, x1, 48
         ret

The zero-extended version is added as well and the rtx costs function is updated to handle
all of these cases.

I've seen this pattern trigger in the gcc code itself in expmed.c where it eliminated a sequence
of orrs and shifts into an extr instruction!

Bootstrapped and tested on aarch64-linux.

Ok for trunk?

Thanks,
Kyrill

2015-04-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64.md (*extr<mode>5_insn_alt): New pattern.
     (*extrsi5_insn_uxtw_alt): Likewise.
     * config/aarch64/aarch64.c (aarch64_extr_rtx_p): New function.
     (aarch64_rtx_costs, IOR case): Use above to properly cost extr
     operations.