[PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

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Hi all,

This is the first of a series to clean up and simplify the arm rtx costs function.
This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
switch statement.

Bootstrapped and tested arm-none-linux-gnueabihf.
Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
baseline COSTS_N_INSNS (1)).

Ok for trunk?

Thanks,
Kyrill

2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
     COSTS_N_INSNS (1) and increment it appropriately throughout the
     function.

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commit 8c4d923b6a2fc902a1a195e2e8c5f934e571d8dd
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Apr 2 11:44:54 2015 +0100

    [ARM] Initialise rtx cost to COSTS_N_INSNS (1) once at the beginning

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4dfe4a7..00da2b7 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -9704,6 +9704,8 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 {
   machine_mode mode = GET_MODE (x);
 
+  *cost = COSTS_N_INSNS (1);
+
   if (TARGET_THUMB1)
     {
       if (speed_p)
@@ -9804,8 +9806,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       bool is_ldm = load_multiple_operation (x, SImode);
       bool is_stm = store_multiple_operation (x, SImode);
 
-      *cost = COSTS_N_INSNS (1);
-
       if (is_ldm || is_stm)
         {
 	  if (speed_p)
@@ -9832,10 +9832,10 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case UDIV:
       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
 	  && (mode == SFmode || !TARGET_VFP_SINGLE))
-	*cost = COSTS_N_INSNS (speed_p
-			       ? extra_cost->fp[mode != SFmode].div : 1);
+	*cost += COSTS_N_INSNS (speed_p
+			       ? extra_cost->fp[mode != SFmode].div : 0);
       else if (mode == SImode && TARGET_IDIV)
-	*cost = COSTS_N_INSNS (speed_p ? extra_cost->mult[0].idiv : 1);
+	*cost += COSTS_N_INSNS (speed_p ? extra_cost->mult[0].idiv : 0);
       else
 	*cost = LIBCALL_COST (2);
       return false;	/* All arguments must be in registers.  */
@@ -9848,7 +9848,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case ROTATE:
       if (mode == SImode && REG_P (XEXP (x, 1)))
 	{
-	  *cost = (COSTS_N_INSNS (2)
+	  *cost += (COSTS_N_INSNS (1)
 		   + rtx_cost (XEXP (x, 0), code, 0, speed_p));
 	  if (speed_p)
 	    *cost += extra_cost->alu.shift_reg;
@@ -9861,7 +9861,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case ASHIFTRT:
       if (mode == DImode && CONST_INT_P (XEXP (x, 1)))
 	{
-	  *cost = (COSTS_N_INSNS (3)
+	  *cost += (COSTS_N_INSNS (2)
 		   + rtx_cost (XEXP (x, 0), code, 0, speed_p));
 	  if (speed_p)
 	    *cost += 2 * extra_cost->alu.shift;
@@ -9869,8 +9869,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	}
       else if (mode == SImode)
 	{
-	  *cost = (COSTS_N_INSNS (1)
-		   + rtx_cost (XEXP (x, 0), code, 0, speed_p));
+	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	  /* Slightly disparage register shifts at -Os, but not by much.  */
 	  if (!CONST_INT_P (XEXP (x, 1)))
 	    *cost += (speed_p ? extra_cost->alu.shift_reg : 1
@@ -9882,8 +9881,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  if (code == ASHIFT)
 	    {
-	      *cost = (COSTS_N_INSNS (1)
-		       + rtx_cost (XEXP (x, 0), code, 0, speed_p));
+	      *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	      /* Slightly disparage register shifts at -Os, but not by
 	         much.  */
 	      if (!CONST_INT_P (XEXP (x, 1)))
@@ -9895,14 +9893,13 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	      if (arm_arch_thumb2 && CONST_INT_P (XEXP (x, 1)))
 		{
 		  /* Can use SBFX/UBFX.  */
-		  *cost = COSTS_N_INSNS (1);
 		  if (speed_p)
 		    *cost += extra_cost->alu.bfx;
 		  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 		}
 	      else
 		{
-		  *cost = COSTS_N_INSNS (2);
+		  *cost += COSTS_N_INSNS (1);
 		  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 		  if (speed_p)
 		    {
@@ -9919,7 +9916,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	    }
 	  else /* Rotates.  */
 	    {
-	      *cost = COSTS_N_INSNS (3 + !CONST_INT_P (XEXP (x, 1)));
+	      *cost += COSTS_N_INSNS (2 + !CONST_INT_P (XEXP (x, 1)));
 	      *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	      if (speed_p)
 		{
@@ -9943,7 +9940,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
         {
           if (mode == SImode)
             {
-              *cost = COSTS_N_INSNS (1);
               if (speed_p)
                 *cost += extra_cost->alu.rev;
 
@@ -9956,7 +9952,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
            and thumb_legacy_rev for the form of RTL used then.  */
           if (TARGET_THUMB)
             {
-              *cost = COSTS_N_INSNS (10);
+              *cost += COSTS_N_INSNS (9);
 
               if (speed_p)
                 {
@@ -9966,7 +9962,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
             }
           else
             {
-              *cost = COSTS_N_INSNS (5);
+              *cost += COSTS_N_INSNS (4);
 
               if (speed_p)
                 {
@@ -9983,7 +9979,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
 	  && (mode == SFmode || !TARGET_VFP_SINGLE))
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (GET_CODE (XEXP (x, 0)) == MULT
 	      || GET_CODE (XEXP (x, 1)) == MULT)
 	    {
@@ -10028,8 +10023,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  rtx shift_op;
 	  rtx non_shift_op;
 
-	  *cost = COSTS_N_INSNS (1);
-
 	  shift_op = shifter_op_p (XEXP (x, 0), &shift_by_reg);
 	  if (shift_op == NULL)
 	    {
@@ -10097,7 +10090,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  HANDLE_NARROW_SHIFT_ARITH (MINUS, 1)
 
 	  /* Slightly disparage, as we might need to widen the result.  */
-	  *cost = 1 + COSTS_N_INSNS (1);
+	  *cost += 1;
 	  if (speed_p)
 	    *cost += extra_cost->alu.arith;
 
@@ -10112,7 +10105,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
       if (mode == DImode)
 	{
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 
 	  if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
 	    {
@@ -10166,7 +10159,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
 	  && (mode == SFmode || !TARGET_VFP_SINGLE))
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (GET_CODE (XEXP (x, 0)) == MULT)
 	    {
 	      rtx mul_op0, mul_op1, add_op;
@@ -10223,7 +10215,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
 	  /* Slightly penalize a narrow operation as the result may
 	     need widening.  */
-	  *cost = 1 + COSTS_N_INSNS (1);
+	  *cost += 1;
 	  if (speed_p)
 	    *cost += extra_cost->alu.arith;
 
@@ -10234,7 +10226,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  rtx shift_op, shift_reg;
 
-	  *cost = COSTS_N_INSNS (1);
 	  if (TARGET_INT_SIMD
 	      && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
 		  || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
@@ -10269,8 +10260,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	    {
 	      rtx mul_op = XEXP (x, 0);
 
-	      *cost = COSTS_N_INSNS (1);
-
 	      if (TARGET_DSP_MULTIPLY
 		  && ((GET_CODE (XEXP (mul_op, 0)) == SIGN_EXTEND
 		       && (GET_CODE (XEXP (mul_op, 1)) == SIGN_EXTEND
@@ -10330,7 +10319,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		  || (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
 		      && GET_CODE (XEXP (XEXP (x, 0), 1)) == SIGN_EXTEND)))
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->mult[1].extend_add;
 	      *cost += (rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
@@ -10341,7 +10329,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	      return true;
 	    }
 
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 
 	  if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
 	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
@@ -10371,7 +10359,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
         rtx inner;
         if (mode == SImode && arm_arch6 && aarch_rev16_p (x, &inner))
           {
-            *cost = COSTS_N_INSNS (1);
             *cost += rtx_cost (inner, BSWAP, 0 , speed_p);
 
             if (speed_p)
@@ -10388,8 +10375,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  rtx op0 = XEXP (x, 0);
 	  rtx shift_op, shift_reg;
 
-	  *cost = COSTS_N_INSNS (1);
-
 	  if (subcode == NOT
 	      && (code == AND
 		  || (code == IOR && TARGET_THUMB2)))
@@ -10438,7 +10423,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  rtx op0 = XEXP (x, 0);
 	  enum rtx_code subcode = GET_CODE (op0);
 
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 
 	  if (subcode == NOT
 	      && (code == AND
@@ -10480,8 +10465,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  rtx op0 = XEXP (x, 0);
 
-	  *cost = COSTS_N_INSNS (1);
-
 	  if (GET_CODE (op0) == NEG)
 	    op0 = XEXP (op0, 0);
 
@@ -10500,7 +10483,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
       if (mode == SImode)
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (TARGET_DSP_MULTIPLY
 	      && ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
 		   && (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
@@ -10536,7 +10518,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		  || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
 		      && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)))
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->mult[1].extend;
 	      *cost += (rtx_cost (XEXP (XEXP (x, 0), 0),
@@ -10558,7 +10539,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
 	  && (mode == SFmode || !TARGET_VFP_SINGLE))
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->fp[mode != SFmode].neg;
 
@@ -10574,7 +10554,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  if (GET_CODE (XEXP (x, 0)) == ABS)
 	    {
-	      *cost = COSTS_N_INSNS (2);
+	      *cost += COSTS_N_INSNS (1);
 	      /* Assume the non-flag-changing variant.  */
 	      if (speed_p)
 		*cost += (extra_cost->alu.log_shift
@@ -10586,7 +10566,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE
 	      || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
 	    {
-	      *cost = COSTS_N_INSNS (2);
+	      *cost += COSTS_N_INSNS (1);
 	      /* No extra cost for MOV imm and MVN imm.  */
 	      /* If the comparison op is using the flags, there's no further
 		 cost, otherwise we need to add the cost of the comparison.  */
@@ -10604,7 +10584,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		}
 	      return true;
 	    }
-	  *cost = COSTS_N_INSNS (1);
+
 	  if (speed_p)
 	    *cost += extra_cost->alu.arith;
 	  return false;
@@ -10614,7 +10594,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  && GET_MODE_SIZE (mode) < 4)
 	{
 	  /* Slightly disparage, as we might need an extend operation.  */
-	  *cost = 1 + COSTS_N_INSNS (1);
+	  *cost += 1;
 	  if (speed_p)
 	    *cost += extra_cost->alu.arith;
 	  return false;
@@ -10622,7 +10602,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
       if (mode == DImode)
 	{
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += 2 * extra_cost->alu.arith;
 	  return false;
@@ -10638,7 +10618,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  rtx shift_op;
 	  rtx shift_reg = NULL;
 
-	  *cost = COSTS_N_INSNS (1);
 	  shift_op = shifter_op_p (XEXP (x, 0), &shift_reg);
 
 	  if (shift_op)
@@ -10661,7 +10640,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	}
       if (mode == DImode)
 	{
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 	  return false;
 	}
 
@@ -10674,7 +10653,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       {
         if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
 	  {
-	    *cost = COSTS_N_INSNS (4);
+	    *cost += COSTS_N_INSNS (3);
 	    return true;
 	  }
 	int op1cost = rtx_cost (XEXP (x, 1), SET, 1, speed_p);
@@ -10717,7 +10696,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  if (TARGET_HARD_FLOAT && GET_MODE_CLASS (op0mode) == MODE_FLOAT
 	      && (op0mode == SFmode || !TARGET_VFP_SINGLE))
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->fp[op0mode != SFmode].compare;
 
@@ -10738,7 +10716,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  /* DImode compares normally take two insns.  */
 	  if (op0mode == DImode)
 	    {
-	      *cost = COSTS_N_INSNS (2);
+	      *cost += COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += 2 * extra_cost->alu.arith;
 	      return false;
@@ -10776,7 +10754,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	      shift_op = shifter_op_p (XEXP (x, 0), &shift_reg);
 	      if (shift_op != NULL)
 		{
-		  *cost = COSTS_N_INSNS (1);
 		  if (shift_reg != NULL)
 		    {
 		      *cost += rtx_cost (shift_reg, ASHIFT, 1, speed_p);
@@ -10790,7 +10767,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		  return true;
 		}
 
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->alu.arith;
 	      if (CONST_INT_P (XEXP (x, 1))
@@ -10834,7 +10810,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	      && XEXP (x, 1) == const0_rtx)
 	    {
 	      /* Thumb also needs an IT insn.  */
-	      *cost = COSTS_N_INSNS (TARGET_THUMB ? 3 : 2);
+	      *cost += COSTS_N_INSNS (TARGET_THUMB ? 2 : 1);
 	      return true;
 	    }
 	  if (XEXP (x, 1) == const0_rtx)
@@ -10843,7 +10819,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		{
 		case LT:
 		  /* LSR Rd, Rn, #31.  */
-		  *cost = COSTS_N_INSNS (1);
 		  if (speed_p)
 		    *cost += extra_cost->alu.shift;
 		  break;
@@ -10855,13 +10830,13 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		case NE:
 		  /* SUBS T1, Rn, #1
 		     SBC  Rd, Rn, T1.  */
-		  *cost = COSTS_N_INSNS (2);
+		  *cost += COSTS_N_INSNS (1);
 		  break;
 
 		case LE:
 		  /* RSBS T1, Rn, Rn, LSR #31
 		     ADC  Rd, Rn, T1. */
-		  *cost = COSTS_N_INSNS (2);
+		  *cost += COSTS_N_INSNS (1);
 		  if (speed_p)
 		    *cost += extra_cost->alu.arith_shift;
 		  break;
@@ -10869,7 +10844,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		case GT:
 		  /* RSB  Rd, Rn, Rn, ASR #1
 		     LSR  Rd, Rd, #31.  */
-		  *cost = COSTS_N_INSNS (2);
+		  *cost += COSTS_N_INSNS (1);
 		  if (speed_p)
 		    *cost += (extra_cost->alu.arith_shift
 			      + extra_cost->alu.shift);
@@ -10878,7 +10853,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		case GE:
 		  /* ASR  Rd, Rn, #31
 		     ADD  Rd, Rn, #1.  */
-		  *cost = COSTS_N_INSNS (2);
+		  *cost += COSTS_N_INSNS (1);
 		  if (speed_p)
 		    *cost += extra_cost->alu.shift;
 		  break;
@@ -10894,7 +10869,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	    }
 	  else
 	    {
-	      *cost = COSTS_N_INSNS (TARGET_THUMB ? 4 : 3);
+	      *cost += COSTS_N_INSNS (TARGET_THUMB ? 3 : 2);
 	      if (CONST_INT_P (XEXP (x, 1))
 		  && const_ok_for_op (INTVAL (XEXP (x, 1)), COMPARE))
 		{
@@ -10922,7 +10897,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
 	  && (mode == SFmode || !TARGET_VFP_SINGLE))
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->fp[mode != SFmode].neg;
 
@@ -10936,7 +10910,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
       if (mode == SImode)
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->alu.log_shift + extra_cost->alu.arith_shift;
 	  return false;
@@ -10972,7 +10945,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       if (GET_MODE (XEXP (x, 0)) != SImode && arm_arch6)
 	{
 	  /* We have SXTB/SXTH.  */
-	  *cost = COSTS_N_INSNS (1);
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	  if (speed_p)
 	    *cost += extra_cost->alu.extend;
@@ -10980,7 +10952,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       else if (GET_MODE (XEXP (x, 0)) != SImode)
 	{
 	  /* Needs two shifts.  */
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	  if (speed_p)
 	    *cost += 2 * extra_cost->alu.shift;
@@ -11018,14 +10990,12 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	     optimizing for speed it should never be slower to use
 	     AND, and we don't really model 16-bit vs 32-bit insns
 	     here.  */
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->alu.logical;
 	}
       else if (GET_MODE (XEXP (x, 0)) != SImode && arm_arch6)
 	{
 	  /* We have UXTB/UXTH.  */
-	  *cost = COSTS_N_INSNS (1);
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	  if (speed_p)
 	    *cost += extra_cost->alu.extend;
@@ -11036,13 +11006,11 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	     shifts rather than two BIC instructions as the second
 	     shift may merge with a subsequent insn as a shifter
 	     op.  */
-	  *cost = COSTS_N_INSNS (2);
+	  *cost += COSTS_N_INSNS (1);
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	  if (speed_p)
 	    *cost += 2 * extra_cost->alu.shift;
 	}
-      else  /* GET_MODE (XEXP (x, 0)) == SImode.  */
-        *cost = COSTS_N_INSNS (1);
 
       /* Widening beyond 32-bits requires one more insn.  */
       if (mode == DImode)
@@ -11100,12 +11068,12 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       if (speed_p)
 	{
 	  if (arm_arch_thumb2 && !flag_pic)
-	    *cost = COSTS_N_INSNS (2);
+	    *cost += COSTS_N_INSNS (1);
 	  else
-	    *cost = COSTS_N_INSNS (1) + extra_cost->ldst.load;
+	    *cost += extra_cost->ldst.load;
 	}
       else
-	*cost = COSTS_N_INSNS (2);
+	*cost += COSTS_N_INSNS (1);
 
       if (flag_pic)
 	{
@@ -11127,7 +11095,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  if (vfp3_const_double_rtx (x))
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->fp[mode == DFmode].fpconst;
 	      return true;
@@ -11135,14 +11102,13 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
 	  if (speed_p)
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (mode == DFmode)
 		*cost += extra_cost->ldst.loadd;
 	      else
 		*cost += extra_cost->ldst.loadf;
 	    }
 	  else
-	    *cost = COSTS_N_INSNS (2 + (mode == DFmode));
+	    *cost += COSTS_N_INSNS (1 + (mode == DFmode));
 
 	  return true;
 	}
@@ -11162,7 +11128,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 
     case HIGH:
     case LO_SUM:
-      *cost = COSTS_N_INSNS (1);
       /* When optimizing for size, we prefer constant pool entries to
 	 MOVW/MOVT pairs, so bump the cost of these slightly.  */
       if (!speed_p)
@@ -11170,7 +11135,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       return true;
 
     case CLZ:
-      *cost = COSTS_N_INSNS (1);
       if (speed_p)
 	*cost += extra_cost->alu.clz;
       return false;
@@ -11178,7 +11142,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case SMIN:
       if (XEXP (x, 1) == const0_rtx)
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->alu.log_shift;
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
@@ -11188,7 +11151,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case SMAX:
     case UMIN:
     case UMAX:
-      *cost = COSTS_N_INSNS (2);
+      *cost += COSTS_N_INSNS (1);
       return false;
 
     case TRUNCATE:
@@ -11202,7 +11165,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 		  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))
 		      == ZERO_EXTEND))))
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->mult[1].extend;
 	  *cost += (rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0), ZERO_EXTEND, 0,
@@ -11232,14 +11194,13 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  && CONST_INT_P (XEXP (x, 1))
 	  && CONST_INT_P (XEXP (x, 2)))
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->alu.bfx;
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
 	  return true;
 	}
       /* Without UBFX/SBFX, need to resort to shift operations.  */
-      *cost = COSTS_N_INSNS (2);
+      *cost += COSTS_N_INSNS (1);
       if (speed_p)
 	*cost += 2 * extra_cost->alu.shift;
       *cost += rtx_cost (XEXP (x, 0), ASHIFT, 0, speed_p);
@@ -11248,7 +11209,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case FLOAT_EXTEND:
       if (TARGET_HARD_FLOAT)
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->fp[mode == DFmode].widen;
 	  if (!TARGET_FPU_ARMV8
@@ -11270,7 +11230,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
     case FLOAT_TRUNCATE:
       if (TARGET_HARD_FLOAT)
 	{
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->fp[mode == DFmode].narrow;
 	  *cost += rtx_cost (XEXP (x, 0), code, 0, speed_p);
@@ -11287,7 +11246,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
           rtx op1 = XEXP (x, 1);
           rtx op2 = XEXP (x, 2);
 
-          *cost = COSTS_N_INSNS (1);
 
           /* vfms or vfnma.  */
           if (GET_CODE (op0) == NEG)
@@ -11316,7 +11274,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  if (GET_MODE_CLASS (mode) == MODE_INT)
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->fp[GET_MODE (XEXP (x, 0)) == DFmode].toint;
 	      /* Strip of the 'cost' of rounding towards zero.  */
@@ -11331,7 +11288,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	  else if (GET_MODE_CLASS (mode) == MODE_FLOAT
 		   && TARGET_FPU_ARMV8)
 	    {
-	      *cost = COSTS_N_INSNS (1);
 	      if (speed_p)
 		*cost += extra_cost->fp[mode == DFmode].roundint;
 	      return false;
@@ -11347,7 +11303,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  /* ??? Increase the cost to deal with transferring from CORE
 	     -> FP registers?  */
-	  *cost = COSTS_N_INSNS (1);
 	  if (speed_p)
 	    *cost += extra_cost->fp[mode == DFmode].fromint;
 	  return false;
@@ -11356,7 +11311,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
       return false;
 
     case CALL:
-      *cost = COSTS_N_INSNS (1);
       return true;
 
     case ASM_OPERANDS:

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html

Thanks,
Kyrill

On 21/04/15 10:11, Kyrill Tkachov wrote:
> Hi all,
>
> This is the first of a series to clean up and simplify the arm rtx costs function.
> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
> switch statement.
>
> Bootstrapped and tested arm-none-linux-gnueabihf.
> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
> baseline COSTS_N_INSNS (1)).
>
> Ok for trunk?
>
> Thanks,
> Kyrill
>
> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>       * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>       COSTS_N_INSNS (1) and increment it appropriately throughout the
>       function.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping^2.

Thanks,
Kyrill

On 30/04/15 13:00, Kyrill Tkachov wrote:
> Ping.
> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html
>
> Thanks,
> Kyrill
>
> On 21/04/15 10:11, Kyrill Tkachov wrote:
>> Hi all,
>>
>> This is the first of a series to clean up and simplify the arm rtx costs function.
>> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
>> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
>> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
>> switch statement.
>>
>> Bootstrapped and tested arm-none-linux-gnueabihf.
>> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
>> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
>> baseline COSTS_N_INSNS (1)).
>>
>> Ok for trunk?
>>
>> Thanks,
>> Kyrill
>>
>> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>        * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>>        COSTS_N_INSNS (1) and increment it appropriately throughout the
>>        function.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping^3.

Thanks,
Kyrill

On 12/05/15 10:09, Kyrill Tkachov wrote:
> Ping^2.
>
> Thanks,
> Kyrill
>
> On 30/04/15 13:00, Kyrill Tkachov wrote:
>> Ping.
>> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html
>>
>> Thanks,
>> Kyrill
>>
>> On 21/04/15 10:11, Kyrill Tkachov wrote:
>>> Hi all,
>>>
>>> This is the first of a series to clean up and simplify the arm rtx costs function.
>>> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
>>> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
>>> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
>>> switch statement.
>>>
>>> Bootstrapped and tested arm-none-linux-gnueabihf.
>>> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
>>> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
>>> baseline COSTS_N_INSNS (1)).
>>>
>>> Ok for trunk?
>>>
>>> Thanks,
>>> Kyrill
>>>
>>> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>>
>>>         * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>>>         COSTS_N_INSNS (1) and increment it appropriately throughout the
>>>         function.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping^4.

Thanks,
Kyrill

On 21/05/15 18:00, Kyrill Tkachov wrote:
> Ping^3.
>
> Thanks,
> Kyrill
>
> On 12/05/15 10:09, Kyrill Tkachov wrote:
>> Ping^2.
>>
>> Thanks,
>> Kyrill
>>
>> On 30/04/15 13:00, Kyrill Tkachov wrote:
>>> Ping.
>>> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html
>>>
>>> Thanks,
>>> Kyrill
>>>
>>> On 21/04/15 10:11, Kyrill Tkachov wrote:
>>>> Hi all,
>>>>
>>>> This is the first of a series to clean up and simplify the arm rtx costs function.
>>>> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
>>>> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
>>>> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
>>>> switch statement.
>>>>
>>>> Bootstrapped and tested arm-none-linux-gnueabihf.
>>>> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
>>>> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
>>>> baseline COSTS_N_INSNS (1)).
>>>>
>>>> Ok for trunk?
>>>>
>>>> Thanks,
>>>> Kyrill
>>>>
>>>> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>>>
>>>>          * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>>>>          COSTS_N_INSNS (1) and increment it appropriately throughout the
>>>>          function.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping^5.

https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html

Thanks,
Kyrill

On 02/06/15 09:16, Kyrill Tkachov wrote:
> Ping^4.
>
> Thanks,
> Kyrill
>
> On 21/05/15 18:00, Kyrill Tkachov wrote:
>> Ping^3.
>>
>> Thanks,
>> Kyrill
>>
>> On 12/05/15 10:09, Kyrill Tkachov wrote:
>>> Ping^2.
>>>
>>> Thanks,
>>> Kyrill
>>>
>>> On 30/04/15 13:00, Kyrill Tkachov wrote:
>>>> Ping.
>>>> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html
>>>>
>>>> Thanks,
>>>> Kyrill
>>>>
>>>> On 21/04/15 10:11, Kyrill Tkachov wrote:
>>>>> Hi all,
>>>>>
>>>>> This is the first of a series to clean up and simplify the arm rtx costs function.
>>>>> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
>>>>> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
>>>>> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
>>>>> switch statement.
>>>>>
>>>>> Bootstrapped and tested arm-none-linux-gnueabihf.
>>>>> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
>>>>> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
>>>>> baseline COSTS_N_INSNS (1)).
>>>>>
>>>>> Ok for trunk?
>>>>>
>>>>> Thanks,
>>>>> Kyrill
>>>>>
>>>>> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>>>>
>>>>>           * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>>>>>           COSTS_N_INSNS (1) and increment it appropriately throughout the
>>>>>           function.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Kyrill Tkachov]

Ping.

Thanks,
Kyrill

On 17/06/15 11:16, Kyrill Tkachov wrote:
> Ping^5.
>
> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html
>
> Thanks,
> Kyrill
>
> On 02/06/15 09:16, Kyrill Tkachov wrote:
>> Ping^4.
>>
>> Thanks,
>> Kyrill
>>
>> On 21/05/15 18:00, Kyrill Tkachov wrote:
>>> Ping^3.
>>>
>>> Thanks,
>>> Kyrill
>>>
>>> On 12/05/15 10:09, Kyrill Tkachov wrote:
>>>> Ping^2.
>>>>
>>>> Thanks,
>>>> Kyrill
>>>>
>>>> On 30/04/15 13:00, Kyrill Tkachov wrote:
>>>>> Ping.
>>>>> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01130.html
>>>>>
>>>>> Thanks,
>>>>> Kyrill
>>>>>
>>>>> On 21/04/15 10:11, Kyrill Tkachov wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> This is the first of a series to clean up and simplify the arm rtx costs function.
>>>>>> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
>>>>>> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
>>>>>> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
>>>>>> switch statement.
>>>>>>
>>>>>> Bootstrapped and tested arm-none-linux-gnueabihf.
>>>>>> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
>>>>>> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
>>>>>> baseline COSTS_N_INSNS (1)).
>>>>>>
>>>>>> Ok for trunk?
>>>>>>
>>>>>> Thanks,
>>>>>> Kyrill
>>>>>>
>>>>>> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>>>>>
>>>>>>            * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>>>>>>            COSTS_N_INSNS (1) and increment it appropriately throughout the
>>>>>>            function.

Re: [PATCH][ARM][stage-1] Initialise cost to COSTS_N_INSNS (1) and increment in arm rtx costs

[Ramana Radhakrishnan]

On 21/04/15 10:11, Kyrill Tkachov wrote:
> Hi all,
> 
> This is the first of a series to clean up and simplify the arm rtx costs function.
> This patch initialises the cost to COSTS_N_INSNS (1) at the top and increments it when appropriate
> in the rest of the function. This makes it more similar to the aarch64 rtx costs function and saves
> us the trouble of having to remember to initialise the cost to COSTS_N_INSNS (1) in each case of the
> switch statement.
> 
> Bootstrapped and tested arm-none-linux-gnueabihf.
> Compiled some large programs with no codegen difference, except some DIV synthesis algorithms were changed,
> presumably due to the cost of SDIV/UDIV, which is now being correctly calculated (before it was missing the
> baseline COSTS_N_INSNS (1)).
> 
> Ok for trunk?
> 
> Thanks,
> Kyrill
> 
> 2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
> 
>     * config/arm/arm.c (arm_new_rtx_costs): Initialise cost to
>     COSTS_N_INSNS (1) and increment it appropriately throughout the
>     function.


OK  - (shudder at ping ^ 6), sorry about the delay.

Ramana