[PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[Kyrill Tkachov]

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Hi all,

The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
argument.
The aarch64 backend erroneously classifies it as a composite type when in
fact it
is a short vector according to AAPCS64
(section 4.1.2 from
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
df).

The solution in this patch is to check aarch64_composite_type_p for a short
vector with
aarch64_short_vector_p rather than the other way around (check for
aarch64_short_vector_p
in aarch64_composite_type_p).

With this patch the testcase compiles fine and in the generated code the
argument is passed
in the simd registers like the ABI requires.

Bootstrapped and tested on aarch64-linux.

This bug appears on all release branches so it's not a regression.
Ok for trunk?
Do we want this in the release branches eventually?

Thanks,
Kyrill

2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    PR target/65491
    * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
    aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
    (aarch64_composite_type_p): Return false if given type and mode are
    for a short vector.

2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    PR target/65491
    * gcc.target/aarch64/pr65491_1.c: New test.
    * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
    * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.

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commit 96913fdb9fd1a3cf53a7e5fc0ee2039f3de980bf
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Mar 20 16:26:35 2015 +0000

    [AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 747bf6a..5a7efbd 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -8027,6 +8027,26 @@ aapcs_vfp_sub_candidate (const_tree type, machine_mode *modep)
   return -1;
 }
 
+/* Return TRUE if the type, as described by TYPE and MODE, is a short vector
+   type as described in AAPCS64 \S 4.1.2.
+
+   See the comment above aarch64_composite_type_p for the notes on MODE.  */
+
+static bool
+aarch64_short_vector_p (const_tree type,
+			machine_mode mode)
+{
+  HOST_WIDE_INT size = -1;
+
+  if (type && TREE_CODE (type) == VECTOR_TYPE)
+    size = int_size_in_bytes (type);
+  else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+	    || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
+    size = GET_MODE_SIZE (mode);
+
+  return (size == 8 || size == 16);
+}
+
 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
    type as described in AAPCS64 \S 4.3.  This includes aggregate, union and
    array types.  The C99 floating-point complex types are also considered
@@ -8048,6 +8068,9 @@ static bool
 aarch64_composite_type_p (const_tree type,
 			  machine_mode mode)
 {
+  if (aarch64_short_vector_p (type, mode))
+    return false;
+
   if (type && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE))
     return true;
 
@@ -8059,27 +8082,6 @@ aarch64_composite_type_p (const_tree type,
   return false;
 }
 
-/* Return TRUE if the type, as described by TYPE and MODE, is a short vector
-   type as described in AAPCS64 \S 4.1.2.
-
-   See the comment above aarch64_composite_type_p for the notes on MODE.  */
-
-static bool
-aarch64_short_vector_p (const_tree type,
-			machine_mode mode)
-{
-  HOST_WIDE_INT size = -1;
-
-  if (type && TREE_CODE (type) == VECTOR_TYPE)
-    size = int_size_in_bytes (type);
-  else if (!aarch64_composite_type_p (type, mode)
-	   && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
-	       || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT))
-    size = GET_MODE_SIZE (mode);
-
-  return (size == 8 || size == 16) ? true : false;
-}
-
 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
    shall be passed or returned in simd/fp register(s) (providing these
    parameter passing registers are available).
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
index 16b5c1e..a21c926 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
@@ -12,6 +12,8 @@
 
 vf2_t vf2 = (vf2_t){ 17.f, 18.f };
 vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+vlf1_t vlf1 = (vlf1_t) { 17.0 };
+
 union int128_t qword;
 
 int *int_ptr = (int *)0xabcdef0123456789ULL;
@@ -41,4 +43,5 @@ FUNC_VAL_CHECK (11,   long double, 98765432123456789.987654321L, Q0, flat)
 FUNC_VAL_CHECK (12,         vf2_t,        vf2, D0, f32in64)
 FUNC_VAL_CHECK (13,         vi4_t,        vi4, Q0, i32in128)
 FUNC_VAL_CHECK (14,         int *,    int_ptr, X0, flat)
+FUNC_VAL_CHECK (15,         vlf1_t,    vlf1, Q0, flat)
 #endif
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h b/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
index 07e56ff..3b9b349 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
@@ -10,6 +10,9 @@ typedef float vf4_t __attribute__((vector_size (16)));
 /* 128-bit vector of 4 ints.  */
 typedef int vi4_t __attribute__((vector_size (16)));
 
+/* 128-bit vector of 1 quad precision float.  */
+typedef long double vlf1_t __attribute__((vector_size (16)));
+
 /* signed quad-word (in an union for the convenience of initialization).  */
 union int128_t
 {
diff --git a/gcc/testsuite/gcc.target/aarch64/pr65491_1.c b/gcc/testsuite/gcc.target/aarch64/pr65491_1.c
new file mode 100644
index 0000000..a548afb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr65491_1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef long double a __attribute__((vector_size (16)));
+
+a
+sum (a first, a second)
+{
+  return first + second;
+}
+

Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[Kyrill Tkachov]

Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01004.html

Thanks,
Kyrill

On 20/04/15 11:16, Kyrill Tkachov wrote:
> Hi all,
>
> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
> argument.
> The aarch64 backend erroneously classifies it as a composite type when in
> fact it
> is a short vector according to AAPCS64
> (section 4.1.2 from
> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
> df).
>
> The solution in this patch is to check aarch64_composite_type_p for a short
> vector with
> aarch64_short_vector_p rather than the other way around (check for
> aarch64_short_vector_p
> in aarch64_composite_type_p).
>
> With this patch the testcase compiles fine and in the generated code the
> argument is passed
> in the simd registers like the ABI requires.
>
> Bootstrapped and tested on aarch64-linux.
>
> This bug appears on all release branches so it's not a regression.
> Ok for trunk?
> Do we want this in the release branches eventually?
>
> Thanks,
> Kyrill
>
> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>      PR target/65491
>      * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
>      aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
>      (aarch64_composite_type_p): Return false if given type and mode are
>      for a short vector.
>
> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
>      PR target/65491
>      * gcc.target/aarch64/pr65491_1.c: New test.
>      * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
>      * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.

Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[Kyrill Tkachov]

Ping^2.

Thanks,
Kyrill

On 06/05/15 10:57, Kyrill Tkachov wrote:
> Ping.
> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01004.html
>
> Thanks,
> Kyrill
>
> On 20/04/15 11:16, Kyrill Tkachov wrote:
>> Hi all,
>>
>> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
>> argument.
>> The aarch64 backend erroneously classifies it as a composite type when in
>> fact it
>> is a short vector according to AAPCS64
>> (section 4.1.2 from
>> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
>> df).
>>
>> The solution in this patch is to check aarch64_composite_type_p for a short
>> vector with
>> aarch64_short_vector_p rather than the other way around (check for
>> aarch64_short_vector_p
>> in aarch64_composite_type_p).
>>
>> With this patch the testcase compiles fine and in the generated code the
>> argument is passed
>> in the simd registers like the ABI requires.
>>
>> Bootstrapped and tested on aarch64-linux.
>>
>> This bug appears on all release branches so it's not a regression.
>> Ok for trunk?
>> Do we want this in the release branches eventually?
>>
>> Thanks,
>> Kyrill
>>
>> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>       PR target/65491
>>       * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
>>       aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
>>       (aarch64_composite_type_p): Return false if given type and mode are
>>       for a short vector.
>>
>> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>       PR target/65491
>>       * gcc.target/aarch64/pr65491_1.c: New test.
>>       * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
>>       * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.

Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[Kyrill Tkachov]

Ping^3.

Thanks,
Kyrill

On 12/05/15 10:06, Kyrill Tkachov wrote:
> Ping^2.
>
> Thanks,
> Kyrill
>
> On 06/05/15 10:57, Kyrill Tkachov wrote:
>> Ping.
>> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01004.html
>>
>> Thanks,
>> Kyrill
>>
>> On 20/04/15 11:16, Kyrill Tkachov wrote:
>>> Hi all,
>>>
>>> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
>>> argument.
>>> The aarch64 backend erroneously classifies it as a composite type when in
>>> fact it
>>> is a short vector according to AAPCS64
>>> (section 4.1.2 from
>>> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
>>> df).
>>>
>>> The solution in this patch is to check aarch64_composite_type_p for a short
>>> vector with
>>> aarch64_short_vector_p rather than the other way around (check for
>>> aarch64_short_vector_p
>>> in aarch64_composite_type_p).
>>>
>>> With this patch the testcase compiles fine and in the generated code the
>>> argument is passed
>>> in the simd registers like the ABI requires.
>>>
>>> Bootstrapped and tested on aarch64-linux.
>>>
>>> This bug appears on all release branches so it's not a regression.
>>> Ok for trunk?
>>> Do we want this in the release branches eventually?
>>>
>>> Thanks,
>>> Kyrill
>>>
>>> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>>
>>>        PR target/65491
>>>        * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
>>>        aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
>>>        (aarch64_composite_type_p): Return false if given type and mode are
>>>        for a short vector.
>>>
>>> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>>
>>>        PR target/65491
>>>        * gcc.target/aarch64/pr65491_1.c: New test.
>>>        * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
>>>        * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.

Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[James Greenhalgh]

On Mon, Apr 20, 2015 at 11:16:02AM +0100, Kyrylo Tkachov wrote:
> Hi all,
> 
> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
> argument.
> The aarch64 backend erroneously classifies it as a composite type when in
> fact it
> is a short vector according to AAPCS64
> (section 4.1.2 from
> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
> df).

Agreed.

> 
> The solution in this patch is to check aarch64_composite_type_p for a short
> vector with
> aarch64_short_vector_p rather than the other way around (check for
> aarch64_short_vector_p
> in aarch64_composite_type_p).

I think I understand what you are saying, but your patch does the
opposite (ADDS a check for aarch64_short_vector_p in
aarch64_composite_type_p, REMOVES a check for aarch64_composite_type_p,
in aarch64_short_vector_p)...

This logic is pretty hairy, and I'm struggling to convince myself that
your change only hits the bug you described above. I think I've worked
it through and it does, but if you can find any additional ABI tests
which stress the Vector/Floating-Point passing rules that would help
settle my nerves.

The patch is OK. I wouldn't think we would want to backport it to
release branches as there is no regression to fix.

Thanks,
James

> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
> 
>     PR target/65491
>     * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
>     aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
>     (aarch64_composite_type_p): Return false if given type and mode are
>     for a short vector.
> 
> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
> 
>     PR target/65491
>     * gcc.target/aarch64/pr65491_1.c: New test.
>     * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
>     * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.

Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

[Kyrill Tkachov]

Hi James,

On 19/05/15 12:18, James Greenhalgh wrote:
> On Mon, Apr 20, 2015 at 11:16:02AM +0100, Kyrylo Tkachov wrote:
>> Hi all,
>>
>> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
>> argument.
>> The aarch64 backend erroneously classifies it as a composite type when in
>> fact it
>> is a short vector according to AAPCS64
>> (section 4.1.2 from
>> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
>> df).
> Agreed.
>
>> The solution in this patch is to check aarch64_composite_type_p for a short
>> vector with
>> aarch64_short_vector_p rather than the other way around (check for
>> aarch64_short_vector_p
>> in aarch64_composite_type_p).
> I think I understand what you are saying, but your patch does the
> opposite (ADDS a check for aarch64_short_vector_p in
> aarch64_composite_type_p, REMOVES a check for aarch64_composite_type_p,
> in aarch64_short_vector_p)...

Yeah, I just worded it wrong in the cover letter, sorry about that.
As you say, the logic is pretty hairy.

>
> This logic is pretty hairy, and I'm struggling to convince myself that
> your change only hits the bug you described above. I think I've worked
> it through and it does, but if you can find any additional ABI tests
> which stress the Vector/Floating-Point passing rules that would help
> settle my nerves.

The aapcs64.exp stuff seems to test the existing rules
quite well...

>
> The patch is OK. I wouldn't think we would want to backport it to
> release branches as there is no regression to fix.

Ok, I've committed it with r223577.
I agree that it's not a regression fix, so messing with ABI code
in the release branches is not desirable.

Thanks for the review.

Kyrill

>
> Thanks,
> James
>
>> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>      PR target/65491
>>      * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
>>      aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
>>      (aarch64_composite_type_p): Return false if given type and mode are
>>      for a short vector.
>>
>> 2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>>
>>      PR target/65491
>>      * gcc.target/aarch64/pr65491_1.c: New test.
>>      * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
>>      * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.