From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 57580 invoked by alias); 12 May 2015 09:06:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 57561 invoked by uid 89); 12 May 2015 09:06:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 May 2015 09:06:04 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-22.uk.mimecast.lan; Tue, 12 May 2015 10:06:01 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 12 May 2015 10:06:00 +0100 Message-ID: <5551C278.8010701@arm.com> Date: Tue, 12 May 2015 09:07:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types References: <000001d07b53$012f1830$038d4890$@arm.com> <5549E580.9050408@arm.com> In-Reply-To: <5549E580.9050408@arm.com> X-MC-Unique: XI47j-gtTSG1pE4AvcEsQQ-1 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg01052.txt.bz2 Ping^2. Thanks, Kyrill On 06/05/15 10:57, Kyrill Tkachov wrote: > Ping. > https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01004.html > > Thanks, > Kyrill > > On 20/04/15 11:16, Kyrill Tkachov wrote: >> Hi all, >> >> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an >> argument. >> The aarch64 backend erroneously classifies it as a composite type when in >> fact it >> is a short vector according to AAPCS64 >> (section 4.1.2 from >> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs= 64.p >> df). >> >> The solution in this patch is to check aarch64_composite_type_p for a sh= ort >> vector with >> aarch64_short_vector_p rather than the other way around (check for >> aarch64_short_vector_p >> in aarch64_composite_type_p). >> >> With this patch the testcase compiles fine and in the generated code the >> argument is passed >> in the simd registers like the ABI requires. >> >> Bootstrapped and tested on aarch64-linux. >> >> This bug appears on all release branches so it's not a regression. >> Ok for trunk? >> Do we want this in the release branches eventually? >> >> Thanks, >> Kyrill >> >> 2015-04-20 Kyrylo Tkachov >> >> PR target/65491 >> * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above >> aarch64_composite_type_p. Remove check for aarch64_composite_type= _p. >> (aarch64_composite_type_p): Return false if given type and mode are >> for a short vector. >> >> 2015-04-20 Kyrylo Tkachov >> >> PR target/65491 >> * gcc.target/aarch64/pr65491_1.c: New test. >> * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef. >> * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.