From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 107517 invoked by alias); 22 May 2015 11:21:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 107505 invoked by uid 89); 22 May 2015 11:21:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 22 May 2015 11:21:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0220A28; Fri, 22 May 2015 04:21:35 -0700 (PDT) Received: from [10.2.206.27] (e105545-lin.cambridge.arm.com [10.2.206.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9AC443F30F; Fri, 22 May 2015 04:21:38 -0700 (PDT) Message-ID: <555F1143.4070606@foss.arm.com> Date: Fri, 22 May 2015 11:26:00 -0000 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" , jason@redhat.com CC: David Edelsohn , wilson@tuliptree.org, Steve Ellcey , Richard Henderson Subject: [RFC / CFT] PR c++/66192 - Remove TARGET_RELAXED_ORDERING and use load acquires. Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg02090.txt.bz2 All, This patch removes the special casing for targets with relaxed memory ordering and handles guard accesses with equivalent atomic load acquire operations. In this process we change the algorithm to load the guard variable with an atomic load that has ACQUIRE semantics. I'm not terribly familiar with the C++ front-end so I'm not sure I've used the appropriate interfaces for doing something like this. This then means that on targets which have weak memory models, the fast path is inlined and can directly use a load-acquire instruction where available (and yay! one more hook gone). Currently bootstrapping and regression testing on AArch64 and ARM (prior to the commit that caused PR66241). If this goes in then I'm happy to withdraw part of the patches to trunk for AArch64 / ARM that defines TARGET_RELAXED_ORDERING and only propose those hunks to the branches. I'd also request the other target maintainers CC'd to help by testing this on their platforms as I do not have access to all of them. To help folks see the difference, this is the difference in output for a compiler for AArch64 built with TARGET_RELAXED_ORDERING set to true and this patch for the testcase below. int* f(void) { static int* p = new int; return p; } - adrp x19, .LANCHOR0 - add x20, x19, :lo12:.LANCHOR0 - mov x0, x20 - bl __cxa_guard_acquire - cbnz w0, .L2 - ldr x0, [x20, 8] + adrp x20, .LANCHOR0 + add x19, x20, :lo12:.LANCHOR0 + ldar x0, [x19] + tbz x0, 0, .L11 +.L9: + ldr x0, [x19, 8] regards Ramana 2015-05-22 Ramana Radhakrishnan PR c++/66192 * config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise. * config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise. * config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise. * config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise. * config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise. * config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise. * config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise. * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete. * target.def (TARGET_RELAXED_ORDERING): Delete. gcc/cp/ChangeLog: 2015-05-22 Ramana Radhakrishnan PR c++/66192 * decl.c (expand_static_init): Remove special casing for targets with weak memory model. * decl2.c (build_atomic_load): New function. (get_guard_cond): Adjust for atomic_load.