From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 77154 invoked by alias); 22 May 2015 14:39:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 77138 invoked by uid 89); 22 May 2015 14:39:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 22 May 2015 14:39:28 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-26.uk.mimecast.lan; Fri, 22 May 2015 15:39:25 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 May 2015 15:39:25 +0100 Message-ID: <555F3F9D.8000002@arm.com> Date: Fri, 22 May 2015 14:49:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: James Greenhalgh CC: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types References: <000001d07b53$012f1830$038d4890$@arm.com> <20150519111854.GA31361@arm.com> In-Reply-To: <20150519111854.GA31361@arm.com> X-MC-Unique: z5uRgaeDRx2ttiS8rTbyMg-1 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg02131.txt.bz2 Hi James, On 19/05/15 12:18, James Greenhalgh wrote: > On Mon, Apr 20, 2015 at 11:16:02AM +0100, Kyrylo Tkachov wrote: >> Hi all, >> >> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an >> argument. >> The aarch64 backend erroneously classifies it as a composite type when in >> fact it >> is a short vector according to AAPCS64 >> (section 4.1.2 from >> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs= 64.p >> df). > Agreed. > >> The solution in this patch is to check aarch64_composite_type_p for a sh= ort >> vector with >> aarch64_short_vector_p rather than the other way around (check for >> aarch64_short_vector_p >> in aarch64_composite_type_p). > I think I understand what you are saying, but your patch does the > opposite (ADDS a check for aarch64_short_vector_p in > aarch64_composite_type_p, REMOVES a check for aarch64_composite_type_p, > in aarch64_short_vector_p)... Yeah, I just worded it wrong in the cover letter, sorry about that. As you say, the logic is pretty hairy. > > This logic is pretty hairy, and I'm struggling to convince myself that > your change only hits the bug you described above. I think I've worked > it through and it does, but if you can find any additional ABI tests > which stress the Vector/Floating-Point passing rules that would help > settle my nerves. The aapcs64.exp stuff seems to test the existing rules quite well... > > The patch is OK. I wouldn't think we would want to backport it to > release branches as there is no regression to fix. Ok, I've committed it with r223577. I agree that it's not a regression fix, so messing with ABI code in the release branches is not desirable. Thanks for the review. Kyrill > > Thanks, > James > >> 2015-04-20 Kyrylo Tkachov >> >> PR target/65491 >> * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above >> aarch64_composite_type_p. Remove check for aarch64_composite_type_= p. >> (aarch64_composite_type_p): Return false if given type and mode are >> for a short vector. >> >> 2015-04-20 Kyrylo Tkachov >> >> PR target/65491 >> * gcc.target/aarch64/pr65491_1.c: New test. >> * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef. >> * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.