From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 103181 invoked by alias); 1 Jun 2015 14:37:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 103144 invoked by uid 89); 1 Jun 2015 14:37:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-Spam-User: qpsmtpd, 2 recipients X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Jun 2015 14:37:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 107E728; Mon, 1 Jun 2015 07:37:20 -0700 (PDT) Received: from [192.168.1.21] (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 584D63F251; Mon, 1 Jun 2015 07:37:16 -0700 (PDT) Message-ID: <556C6E1A.3050904@foss.arm.com> Date: Mon, 01 Jun 2015 14:37:00 -0000 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Ramana Radhakrishnan , "gcc-patches@gcc.gnu.org" CC: "libstdc++@gcc.gnu.org" Subject: Re: [Patch ARM] Add cpu_defines.h for ARM References: <555B3103.9040603@foss.arm.com> In-Reply-To: <555B3103.9040603@foss.arm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg00082.txt.bz2 On 19/05/15 13:48, Ramana Radhakrishnan wrote: > Hardware Integer divide instructions do not trap. Define this to be so > for the ARM port. > > Applied to trunk after a build and test across architecture ranges and a > bootstrap and regression run on a Cortex-A15 - a v7ve core that has > hardware divide instructions. > > A patch for AArch64 follows. > > regards > Ramana > > 2015-05-17 Ramana Radhakrishnan > > * configure.host: Define cpu_defines_dir for ARM. > * config/cpu/arm/cpu_defines.h: New file. > +#ifdef __ARM_ARCH_EXT_IDIV__ +#define __glibcxx_integral_traps false +#else +#define __glibcxx_integral_traps true +#endif Hmm, I wonder if we should always define this to false. If we're building on an architecture that doesn't have division, we'll call a library function; but if that is picked at link time, and the link time options suggest that hw division is available, we could end up with a library function that doesn't trap. R.