From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80725 invoked by alias); 4 Jun 2015 08:17:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 80709 invoked by uid 89); 4 Jun 2015 08:17:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 04 Jun 2015 08:17:03 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-14.uk.mimecast.lan; Thu, 04 Jun 2015 09:17:00 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Jun 2015 09:17:00 +0100 Message-ID: <5570097C.2010706@arm.com> Date: Thu, 04 Jun 2015 08:24:00 -0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Shiva Chen CC: Ramana Radhakrishnan , GCC Patches , "nickc@redhat.com" , Richard Earnshaw , "shivac@marvell.com" Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code References: <556EBB3F.7090603@arm.com> <556EBBAC.2020504@arm.com> <556EBC77.3060601@arm.com> In-Reply-To: X-MC-Unique: oaUxZ9aESG6sHWeMuC31Yg-1 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg00379.txt.bz2 Hi Shiva, On 04/06/15 04:13, Shiva Chen wrote: > Hi, Ramana > > Currently, I work for Marvell and the company have copyright assignment o= n file. > > Hi, all > > After adding the attribute and rebuild gcc, I got the assembler error mes= sage > > load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' > > When i look into armv8 ISA document, it seems ldrb Encoding A1 have > conditional code field. > > Does it mean we should also patch assembler or I just miss > understanding something ? > > Following command use to generate load_n.s: > > /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabi= hf-hard/gcc-final/./gcc/cc1 > -fpreprocessed load_n.i -quiet -dumpbase load_n.c -march=3Darmv8-a > -mfloat-abi=3Dhard -mfpu=3Dfp-armv8 -mtls-dialect=3Dgnu -auxbase-strip > .libs/load_1_.o -g3 -O2 -Wall -Werror -version -fPIC -funwind-tables > -o load_n.s > > > The test.c is a simple test case to reproduce missing conditional code > in mmap.c. > > Any suggestion ? I reproduced the assembler failure with your patch. The reason is that for arm mode we use divided syntax, where the condition = field goes in a different place. So, while ldrbeq r0,[r0] is rejected, ldreqb r0, [r0] work= s. Since we always use divided syntax for arm mode, I think you'll need to put= the condition field in the right place depending on arm or thumb mode. Ugh, this is becoming ugly :( Kyrill > > > Shiva > > 2015-06-03 17:29 GMT+08:00 Shiva Chen : >> Hi, Ramana >> >> I'm not sure what copyright assignment means ? >> >> Does it mean the patch have copyright assignment or not ? >> >> I update the patch to add "predicable" and "predicable_short_it" >> attribute as suggestion. >> >> However, I don't have svn write access yet. >> >> Shiva >> >> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov : >>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>> "predicable" attribute set to "yes". >>>>> Therefore the compiler should be trying to branch around here rather = than >>>>> try to do a cond_exec. >>>>> Why does the generated code above look like it's converted to conditi= onal >>>>> execution? >>>>> Could you produce a self-contained reduced testcase for this? >>>> CCFSM state machine in ARM state. >>>> >>>> arm.c (final_prescan_insn). >>> >>> Ah ok. >>> This patch makes sense then. >>> As Ramana mentioned, please mark the pattern with "predicable" and also= set >>> the "predicable_short_it" attribute to "no" so that it will not be >>> conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >>> >>> Thanks, >>> Kyrill >>> >>> >>> >>>> Ramana >>>> >>>>> Thanks, >>>>> Kyrill >>>>> >>>>>> @@ -91,9 +91,9 @@ >>>>>> { >>>>>> enum memmodel model =3D memmodel_from_int (INTVAL (operands= [2])); >>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>> is_mm_acquire (model)) >>>>>> - return \"str\t%1, %0\"; >>>>>> + return \"str%?\t%1, %0\"; >>>>>> else >>>>>> - return \"stl\t%1, %0\"; >>>>>> + return \"stl%?\t%1, %0\"; >>>>>> } >>>>>> ) >>>>>>