From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31944 invoked by alias); 4 Jun 2015 08:42:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 31932 invoked by uid 89); 4 Jun 2015 08:42:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 04 Jun 2015 08:42:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4DA5E28; Thu, 4 Jun 2015 01:42:19 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C494C3F21B; Thu, 4 Jun 2015 01:42:12 -0700 (PDT) Message-ID: <55700F63.2060700@foss.arm.com> Date: Thu, 04 Jun 2015 08:42:00 -0000 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Kyrill Tkachov , Shiva Chen CC: Ramana Radhakrishnan , GCC Patches , "nickc@redhat.com" , "shivac@marvell.com" Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code References: <556EBB3F.7090603@arm.com> <556EBBAC.2020504@arm.com> <556EBC77.3060601@arm.com> <5570097C.2010706@arm.com> In-Reply-To: <5570097C.2010706@arm.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg00385.txt.bz2 On 04/06/15 09:17, Kyrill Tkachov wrote: > Hi Shiva, > > On 04/06/15 04:13, Shiva Chen wrote: >> Hi, Ramana >> >> Currently, I work for Marvell and the company have copyright assignment on file. >> >> Hi, all >> >> After adding the attribute and rebuild gcc, I got the assembler error message >> >> load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]' >> >> When i look into armv8 ISA document, it seems ldrb Encoding A1 have >> conditional code field. >> >> Does it mean we should also patch assembler or I just miss >> understanding something ? >> >> Following command use to generate load_n.s: >> >> /home/shivac/build-system-trunk/Release/build/armv8-marvell-linux-gnueabihf-hard/gcc-final/./gcc/cc1 >> -fpreprocessed load_n.i -quiet -dumpbase load_n.c -march=armv8-a >> -mfloat-abi=hard -mfpu=fp-armv8 -mtls-dialect=gnu -auxbase-strip >> .libs/load_1_.o -g3 -O2 -Wall -Werror -version -fPIC -funwind-tables >> -o load_n.s >> >> >> The test.c is a simple test case to reproduce missing conditional code >> in mmap.c. >> >> Any suggestion ? > > I reproduced the assembler failure with your patch. > > The reason is that for arm mode we use divided syntax, where the condition field goes in a > different place. So, while ldrbeq r0,[r0] is rejected, ldreqb r0, [r0] works. > Since we always use divided syntax for arm mode, I think you'll need to put the condition field > in the right place depending on arm or thumb mode. > Ugh, this is becoming ugly :( > Use %(%)\t%1, %0\"; R. > Kyrill > >> >> >> Shiva >> >> 2015-06-03 17:29 GMT+08:00 Shiva Chen : >>> Hi, Ramana >>> >>> I'm not sure what copyright assignment means ? >>> >>> Does it mean the patch have copyright assignment or not ? >>> >>> I update the patch to add "predicable" and "predicable_short_it" >>> attribute as suggestion. >>> >>> However, I don't have svn write access yet. >>> >>> Shiva >>> >>> 2015-06-03 16:36 GMT+08:00 Kyrill Tkachov : >>>> On 03/06/15 09:32, Ramana Radhakrishnan wrote: >>>>>> This pattern is not predicable though, i.e. it doesn't have the >>>>>> "predicable" attribute set to "yes". >>>>>> Therefore the compiler should be trying to branch around here rather than >>>>>> try to do a cond_exec. >>>>>> Why does the generated code above look like it's converted to conditional >>>>>> execution? >>>>>> Could you produce a self-contained reduced testcase for this? >>>>> CCFSM state machine in ARM state. >>>>> >>>>> arm.c (final_prescan_insn). >>>> >>>> Ah ok. >>>> This patch makes sense then. >>>> As Ramana mentioned, please mark the pattern with "predicable" and also set >>>> the "predicable_short_it" attribute to "no" so that it will not be >>>> conditionalised in Thumb2 mode or when -mrestrict-it is enabled. >>>> >>>> Thanks, >>>> Kyrill >>>> >>>> >>>> >>>>> Ramana >>>>> >>>>>> Thanks, >>>>>> Kyrill >>>>>> >>>>>>> @@ -91,9 +91,9 @@ >>>>>>> { >>>>>>> enum memmodel model = memmodel_from_int (INTVAL (operands[2])); >>>>>>> if (is_mm_relaxed (model) || is_mm_consume (model) || >>>>>>> is_mm_acquire (model)) >>>>>>> - return \"str\t%1, %0\"; >>>>>>> + return \"str%?\t%1, %0\"; >>>>>>> else >>>>>>> - return \"stl\t%1, %0\"; >>>>>>> + return \"stl%?\t%1, %0\"; >>>>>>> } >>>>>>> ) >>>>>>> >