From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11763 invoked by alias); 10 Jun 2015 12:18:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 11735 invoked by uid 89); 10 Jun 2015 12:18:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 10 Jun 2015 12:18:40 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-20.uk.mimecast.lan; Wed, 10 Jun 2015 13:18:37 +0100 Received: from [10.2.207.65] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Jun 2015 13:18:37 +0100 Message-ID: <55782B1D.90005@arm.com> Date: Wed, 10 Jun 2015 13:01:00 -0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: Charles Baylis CC: GCC Patches , Kugan Subject: Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics References: <5575615E.30509@arm.com> In-Reply-To: X-MC-Unique: xS4mXIYoQJO-cpzi93BNmg-1 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg00749.txt.bz2 Charles Baylis wrote: > On 8 June 2015 at 10:33, Alan Lawrence wrote: >> Thanks for working on this! >> >> I'd been fiddling around with a patch with some similar elements to this, >> but many trials with union types, subregs, etc., all worsened the regist= er >> allocation and led to more unnecessary shuffling / moves. >=20 > Kugan has been looking into this at Linaro. We should avoid > duplicating effort here. Yes. I stopped short of looking into the internals of the register allocato= r,=20 although I believe any proper solution is going to have to make changes her= e.=20 However, I am working on (/nearly finished, just some tidying!) a patch ser= ies=20 to add D-registers to TARGET_ARRAY_MODE_SUPPORTED_P, which may help matters. >> The only real >> thing I tried which you don't do here, was to introduce a set_dreg expan= der >> to clean up some of those macro definitions in arm_neon.h. That could ea= sily >> follow in a separate patch if desired! >=20 > I'd prefer that to be a separate step. Sure. (*If* we go that route - I hope to have another look after=20 aarch64_array_mode_supported_p). Cheers, Alan