From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 56041 invoked by alias); 22 Jun 2015 15:18:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 56029 invoked by uid 89); 22 Jun 2015 15:18:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 22 Jun 2015 15:18:09 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-16ED4pEMTbeXeXz_Ce7fPA-1 Received: from e106327-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Jun 2015 16:18:04 +0100 Message-ID: <5588272C.8060306@arm.com> Date: Mon, 22 Jun 2015 15:18:00 -0000 From: Matthew Wahab User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/2][ARM] Use new FPU features representation References: <558826B0.401@arm.com> In-Reply-To: <558826B0.401@arm.com> X-MC-Unique: 16ED4pEMTbeXeXz_Ce7fPA-1 Content-Type: multipart/mixed; boundary="------------020507080006070304020801" X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg01443.txt.bz2 This is a multi-part message in MIME format. --------------020507080006070304020801 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 712 Hello, This patch series changes the representation of FPU features to use a simple bit-set and flags, as is done elsewhere. This patch uses the new representation of FPU feature sets. Tested the series for arm-none-linux-gnueabihf with check-gcc Ok for trunk? Matthew gcc/ 2015-06-22 Matthew Wahab * config/arm/arm-fpus.def: Replace neon, fp16 and crypto boolean fields with feature flags. Update comment. * config/arm/arm.c (ARM_FPU): Update macro. * config/arm/arm.h (TARGET_NEON_FP16): Update feature test. (TARGET_FP16): Likewise. (TARGET_CRYPTO): Likewise. (TARGET_NEON): Likewise. (struct arm_fpu_desc): Remove fields neon, fp16 and crypto. Add field features. --------------020507080006070304020801 Content-Type: text/x-patch; name=0002-Use-new-FPU-feature-definitions.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0002-Use-new-FPU-feature-definitions.patch" Content-length: 6568 =46rom 6f9cd1b41d7597d95bd80aa21344f8e6e011e168 Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Wed, 10 Jun 2015 10:11:56 +0100 Subject: [PATCH 2/2] Use new FPU feature definitions. Change-Id: I0c45e52b08b31433ec2b30fcb666584cabcb826b --- gcc/config/arm/arm-fpus.def | 40 ++++++++++++++++++++-------------------- gcc/config/arm/arm.c | 4 ++-- gcc/config/arm/arm.h | 22 +++++++++++++--------- 3 files changed, 35 insertions(+), 31 deletions(-) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index 2dfefd6..efd5896 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,30 +19,30 @@ =20 /* Before using #include to read this file, define a macro: =20 - ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) + ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) =20 The arguments are the fields of struct arm_fpu_desc. =20 genopt.sh assumes no whitespace up to the first "," in each entry. */ =20 -ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false, false) -ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false, false) -ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true, false) -ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false, false) -ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true, f= alse) -ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false, fals= e) -ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true, = false) -ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false, false) -ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false) -ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false) -ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false) -ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, f= alse) -ARM_FPU("fpv5-sp-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, false, true, f= alse) -ARM_FPU("fpv5-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_D16, false, true, false) -ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false) -ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false) -ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, fals= e) +ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, FPU_FL_NONE) +ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE) +ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_FP16) +ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_NONE) +ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_FP16) +ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_NONE) +ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_FP16) +ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON) +ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON | FPU_F= L_FP16) +ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_FP16) +ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, FPU_FL_FP16) +ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, FPU_FL_FP16) +ARM_FPU("fpv5-sp-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, FPU_FL_FP16) +ARM_FPU("fpv5-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_D16, FPU_FL_FP16) +ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_NEON | FPU_= FL_FP16) +ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_FP16) +ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FP= U_FL_FP16) ARM_FPU("crypto-neon-fp-armv8", - ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, true) + ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CR= YPTO) /* Compatibility aliases. */ -ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false, false) +ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e79a369..e104d2f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2231,8 +2231,8 @@ char arm_arch_name[] =3D "__ARM_ARCH_0UNK__"; =20 static const struct arm_fpu_desc all_fpus[] =3D { -#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) \ - { NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO }, +#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) \ + { NAME, MODEL, REV, VFP_REGS, FEATURES }, #include "arm-fpus.def" #undef ARM_FPU }; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index eadbcec..26d48a7 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -193,11 +193,13 @@ extern void (*arm_lang_output_object_attributes_hook)= (void); #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs !=3D VFP_REG_S= INGLE) =20 /* FPU supports half-precision floating-point with NEON element load/store= . */ -#define TARGET_NEON_FP16 \ - (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) +#define TARGET_NEON_FP16 \ + (TARGET_VFP \ + && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_NEON | FPU_FL_FP16)) =20 /* FPU supports VFP half-precision floating-point. */ -#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) +#define TARGET_FP16 \ + (TARGET_VFP && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_FP16)) =20 /* FPU supports fused-multiply-add operations. */ #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >=3D 4) @@ -206,14 +208,18 @@ extern void (*arm_lang_output_object_attributes_hook)= (void); #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >=3D 8) =20 /* FPU supports Crypto extensions. */ -#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) +#define TARGET_CRYPTO \ + (TARGET_VFP && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_CRYPTO)) + =20 /* FPU supports Neon instructions. The setting of this macro gets revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT and TARGET_HARD_FLOAT to ensure that NEON instructions are available. */ -#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ - && TARGET_VFP && arm_fpu_desc->neon) +#define TARGET_NEON \ + (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \ + && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_NEON)) + =20 /* Q-bit is present. */ #define TARGET_ARM_QBIT_P(flags) \ @@ -353,9 +359,7 @@ extern const struct arm_fpu_desc enum arm_fp_model model; int rev; enum vfp_reg_type regs; - int neon; - int fp16; - int crypto; + arm_fpu_fset features; } *arm_fpu_desc; =20 /* Which floating point hardware to schedule for. */ --=20 1.9.1 --------------020507080006070304020801--