From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80455 invoked by alias); 22 Jun 2015 15:54:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 80445 invoked by uid 89); 22 Jun 2015 15:54:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS,UPPERCASE_50_75 autolearn=no version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 22 Jun 2015 15:54:29 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-27-NJ5mYJ4SRWWx07f9fb-iOQ-1 Received: from e106327-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Jun 2015 16:54:25 +0100 Message-ID: <55882FB2.8030702@arm.com> Date: Mon, 22 Jun 2015 16:07:00 -0000 From: Matthew Wahab User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def References: <55882CA4.5050102@arm.com> In-Reply-To: <55882CA4.5050102@arm.com> X-MC-Unique: NJ5mYJ4SRWWx07f9fb-iOQ-1 Content-Type: multipart/mixed; boundary="------------090806010008020501000103" X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg01455.txt.bz2 This is a multi-part message in MIME format. --------------090806010008020501000103 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 985 Hello, The ARM backend uses an unsigned long to record CPU feature flags and there= are currently 30 bits in use. This series of patches replaces the single unsign= ed long with a representation based on an array of values. This patch updates the entries in the arm-core.def and arm-arches.def files for the new arm_feature_set representation, moving the initializers from a = macro expansion and making them explicit in the file entries. Tested for arm-none-linux-gnueabihf with check-gcc. Ok for trunk? Matthew gcc/ 2015-08-22 Matthew Wahab * config/arm/arm-arches.def: Replace single value flags with initializer built from ARM_FSET_MAKE_CPU1. * config/arm/arm-cores.def: Likewise. * config/arm/arm.c: (all_cores): Remove ARM_FSET_MAKE_CPU1 derivation from the ARM_CORE macro definition, use the given value instead. (all_architectures): Remove ARM_FSET_MAKE_CPU1 derivation from the ARM_ARCH macro definition, use the given value instead. --------------090806010008020501000103 Content-Type: text/x-patch; name=0004-Move-feature-sets-into-core-and-arch-def-files.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename*0="0004-Move-feature-sets-into-core-and-arch-def-files.patch" Content-length: 29144 =46rom 389cfb0e1046b1d84dd3d8920aa5bed50dc19164 Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Mon, 8 Jun 2015 16:15:52 +0100 Subject: [PATCH 4/4] Move feature sets into core and arch def files. Change-Id: Ica484c7d9f46413c196b26a630ff49413b10289b --- gcc/config/arm/arm-arches.def | 56 ++++++------ gcc/config/arm/arm-cores.def | 200 +++++++++++++++++++++-----------------= ---- gcc/config/arm/arm.c | 4 +- 3 files changed, 130 insertions(+), 130 deletions(-) diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index 840c1ff..6d0374a 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -28,33 +28,33 @@ =20 genopt.sh assumes no whitespace up to the first "," in each entry. */ =20 -ARM_ARCH("armv2", arm2, 2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2) -ARM_ARCH("armv2a", arm2, 2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2) -ARM_ARCH("armv3", arm6, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3) -ARM_ARCH("armv3m", arm7m, 3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3= M) -ARM_ARCH("armv4", arm7tdmi, 4, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4) +ARM_ARCH("armv2", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MOD= E26 | FL_FOR_ARCH2)) +ARM_ARCH("armv2a", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MOD= E26 | FL_FOR_ARCH2)) +ARM_ARCH("armv3", arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MOD= E26 | FL_FOR_ARCH3)) +ARM_ARCH("armv3m", arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MO= DE26 | FL_FOR_ARCH3M)) +ARM_ARCH("armv4", arm7tdmi, 4, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MOD= E26 | FL_FOR_ARCH4)) /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no implementations that support it, so we will leave it out for now. */ -ARM_ARCH("armv4t", arm7tdmi, 4T, FL_CO_PROC | FL_FOR_ARCH4= T) -ARM_ARCH("armv5", arm10tdmi, 5, FL_CO_PROC | FL_FOR_ARCH5) -ARM_ARCH("armv5t", arm10tdmi, 5T, FL_CO_PROC | FL_FOR_ARCH5= T) -ARM_ARCH("armv5e", arm1026ejs, 5E, FL_CO_PROC | FL_FOR_ARCH5= E) -ARM_ARCH("armv5te", arm1026ejs, 5TE, FL_CO_PROC | FL_FOR_ARCH5= TE) -ARM_ARCH("armv6", arm1136js, 6, FL_CO_PROC | FL_FOR_ARCH6) -ARM_ARCH("armv6j", arm1136js, 6J, FL_CO_PROC | FL_FOR_ARCH6= J) -ARM_ARCH("armv6k", mpcore, 6K, FL_CO_PROC | FL_FOR_ARCH6K) -ARM_ARCH("armv6z", arm1176jzs, 6Z, FL_CO_PROC | FL_FOR_ARCH6= Z) -ARM_ARCH("armv6zk", arm1176jzs, 6ZK, FL_CO_PROC | FL_FOR_ARCH6= ZK) -ARM_ARCH("armv6t2", arm1156t2s, 6T2, FL_CO_PROC | FL_FOR_ARCH6= T2) -ARM_ARCH("armv6-m", cortexm1, 6M, FL_FOR_ARCH6M) -ARM_ARCH("armv6s-m", cortexm1, 6M, FL_FOR_ARCH6M) -ARM_ARCH("armv7", cortexa8, 7, FL_CO_PROC | FL_FOR_ARCH7) -ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A) -ARM_ARCH("armv7ve", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7VE) -ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R) -ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M) -ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM) -ARM_ARCH("armv8-a", cortexa53, 8A, FL_CO_PROC | FL_FOR_ARCH8= A) -ARM_ARCH("armv8-a+crc",cortexa53, 8A,FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8= A) -ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5= TE | FL_XSCALE | FL_IWMMXT) -ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5= TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2) +ARM_ARCH("armv4t", arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH4T)) +ARM_ARCH("armv5", arm10tdmi, 5, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH5)) +ARM_ARCH("armv5t", arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH5T)) +ARM_ARCH("armv5e", arm1026ejs, 5E, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH5E)) +ARM_ARCH("armv5te", arm1026ejs, 5TE, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH5TE)) +ARM_ARCH("armv6", arm1136js, 6, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH6)) +ARM_ARCH("armv6j", arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH6J)) +ARM_ARCH("armv6k", mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH6K)) +ARM_ARCH("armv6z", arm1176jzs, 6Z, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH6Z)) +ARM_ARCH("armv6zk", arm1176jzs, 6ZK, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH6ZK)) +ARM_ARCH("armv6t2", arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH6T2)) +ARM_ARCH("armv6-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M)) +ARM_ARCH("armv6s-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M)) +ARM_ARCH("armv7", cortexa8, 7, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL= _FOR_ARCH7)) +ARM_ARCH("armv7-a", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | F= L_FOR_ARCH7A)) +ARM_ARCH("armv7ve", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | F= L_FOR_ARCH7VE)) +ARM_ARCH("armv7-r", cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | F= L_FOR_ARCH7R)) +ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | F= L_FOR_ARCH7M)) +ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH7EM)) +ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_FOR_ARCH8A)) +ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | F= L_CRC32 | FL_FOR_ARCH8A)) +ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_S= TRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)) +ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_S= TRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index f362c27..a68404e 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -43,134 +43,134 @@ Some tools assume no whitespace up to the first "," in each entry. */ =20 /* V2/V2A Architecture Processors */ -ARM_CORE("arm2", arm2, arm2, 2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slo= wmul) -ARM_CORE("arm250", arm250, arm250, 2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH= 2, slowmul) -ARM_CORE("arm3", arm3, arm3, 2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slo= wmul) +ARM_CORE("arm2", arm2, arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26= | FL_FOR_ARCH2), slowmul) +ARM_CORE("arm250", arm250, arm250, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_= MODE26 | FL_FOR_ARCH2), slowmul) +ARM_CORE("arm3", arm3, arm3, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26= | FL_FOR_ARCH2), slowmul) =20 /* V3 Architecture Processors */ -ARM_CORE("arm6", arm6, arm6, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, sl= owmul) -ARM_CORE("arm60", arm60, arm60, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3,= slowmul) -ARM_CORE("arm600", arm600, arm600, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF | = FL_FOR_ARCH3, slowmul) -ARM_CORE("arm610", arm610, arm610, 3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3,= slowmul) -ARM_CORE("arm620", arm620, arm620, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF | = FL_FOR_ARCH3, slowmul) -ARM_CORE("arm7", arm7, arm7, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, sl= owmul) -ARM_CORE("arm7d", arm7d, arm7d, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3,= slowmul) -ARM_CORE("arm7di", arm7di, arm7di, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARC= H3, slowmul) -ARM_CORE("arm70", arm70, arm70, 3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3,= slowmul) -ARM_CORE("arm700", arm700, arm700, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF | = FL_FOR_ARCH3, slowmul) -ARM_CORE("arm700i", arm700i, arm700i, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF = | FL_FOR_ARCH3, slowmul) -ARM_CORE("arm710", arm710, arm710, 3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3,= slowmul) -ARM_CORE("arm720", arm720, arm720, 3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3,= slowmul) -ARM_CORE("arm710c", arm710c, arm710c, 3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH= 3, slowmul) -ARM_CORE("arm7100", arm7100, arm7100, 3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH= 3, slowmul) -ARM_CORE("arm7500", arm7500, arm7500, 3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH= 3, slowmul) +ARM_CORE("arm6", arm6, arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE2= 6 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm60", arm60, arm60, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MO= DE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm600", arm600, arm600, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL= _MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm610", arm610, arm610, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_= WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm620", arm620, arm620, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL= _MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7", arm7, arm7, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE2= 6 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7d", arm7d, arm7d, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MO= DE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7di", arm7di, arm7di, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL= _MODE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm70", arm70, arm70, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MO= DE26 | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm700", arm700, arm700, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL= _MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm700i", arm700i, arm700i, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | = FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm710", arm710, arm710, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_= WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm720", arm720, arm720, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_= WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm710c", arm710c, arm710c, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | F= L_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7100", arm7100, arm7100, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | F= L_WBUF | FL_FOR_ARCH3), slowmul) +ARM_CORE("arm7500", arm7500, arm7500, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | F= L_WBUF | FL_FOR_ARCH3), slowmul) /* Doesn't have an external co-proc, but does have embedded fpa. */ -ARM_CORE("arm7500fe", arm7500fe, arm7500fe, 3, FL_CO_PROC | FL_MODE26 | FL= _WBUF | FL_FOR_ARCH3, slowmul) +ARM_CORE("arm7500fe", arm7500fe, arm7500fe, 3, ARM_FSET_MAKE_CPU1 (FL_CO_P= ROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul) =20 /* V3M Architecture Processors */ /* arm7m doesn't exist on its own, but only with D, ("and", and I), but those don't alter the code, so arm7m is sometimes used. */ -ARM_CORE("arm7m", arm7m, arm7m, 3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH= 3M, fastmul) -ARM_CORE("arm7dm", arm7dm, arm7dm, 3M, FL_CO_PROC | FL_MODE26 | FL_FOR_AR= CH3M, fastmul) -ARM_CORE("arm7dmi", arm7dmi, arm7dmi, 3M, FL_CO_PROC | FL_MODE26 | FL_FOR_= ARCH3M, fastmul) +ARM_CORE("arm7m", arm7m, arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_= MODE26 | FL_FOR_ARCH3M), fastmul) +ARM_CORE("arm7dm", arm7dm, arm7dm, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | F= L_MODE26 | FL_FOR_ARCH3M), fastmul) +ARM_CORE("arm7dmi", arm7dmi, arm7dmi, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC |= FL_MODE26 | FL_FOR_ARCH3M), fastmul) =20 /* V4 Architecture Processors */ -ARM_CORE("arm8", arm8, arm8, 4, FL_MODE26 | FL_LDSCHED | FL_FOR= _ARCH4, fastmul) -ARM_CORE("arm810", arm810, arm810, 4, FL_MODE26 | FL_LDSCHED | FL_= FOR_ARCH4, fastmul) -ARM_CORE("strongarm", strongarm, strongarm, 4, FL_MODE26 | FL_LDSCHED= | FL_STRONG | FL_FOR_ARCH4, strongarm) -ARM_CORE("strongarm110", strongarm110, strongarm110, 4, FL_MODE26 | FL_LD= SCHED | FL_STRONG | FL_FOR_ARCH4, strongarm) -ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_= LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm) -ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_= LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm) -ARM_CORE("fa526", fa526, fa526, 4, FL_LDSCHED | FL_FOR_ARCH4, fa= stmul) -ARM_CORE("fa626", fa626, fa626, 4, FL_LDSCHED | FL_FOR_ARCH4, fa= stmul) +ARM_CORE("arm8", arm8, arm8, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 |= FL_LDSCHED | FL_FOR_ARCH4), fastmul) +ARM_CORE("arm810", arm810, arm810, 4, ARM_FSET_MAKE_CPU1 (FL_MODE2= 6 | FL_LDSCHED | FL_FOR_ARCH4), fastmul) +ARM_CORE("strongarm", strongarm, strongarm, 4, ARM_FSET_MAKE_CPU1 (FL= _MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) +ARM_CORE("strongarm110", strongarm110, strongarm110, 4, ARM_FSET_MAKE_CPU= 1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) +ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, ARM_FSET_MAKE_C= PU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) +ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, ARM_FSET_MAKE_C= PU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm) +ARM_CORE("fa526", fa526, fa526, 4, ARM_FSET_MAKE_CPU1 (FL_LDSCHE= D | FL_FOR_ARCH4), fastmul) +ARM_CORE("fa626", fa626, fa626, 4, ARM_FSET_MAKE_CPU1 (FL_LDSCHE= D | FL_FOR_ARCH4), fastmul) =20 /* V4T Architecture Processors */ -ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, 4T, FL_CO_PROC | FL_FOR_ARCH4T, f= astmul) -ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, 4T, FL_CO_PROC | FL_FOR_ARCH4= T, fastmul) -ARM_CORE("arm710t", arm710t, arm710t, 4T, FL_WBUF | FL_FOR_ARCH4T, fast= mul) -ARM_CORE("arm720t", arm720t, arm720t, 4T, FL_WBUF | FL_FOR_ARCH4T, fast= mul) -ARM_CORE("arm740t", arm740t, arm740t, 4T, FL_WBUF | FL_FOR_ARCH4T, fast= mul) -ARM_CORE("arm9", arm9, arm9, 4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul) -ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, 4T, FL_LDSCHED | FL_FOR_ARCH4T, f= astmul) -ARM_CORE("arm920", arm920, arm920, 4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmu= l) -ARM_CORE("arm920t", arm920t, arm920t, 4T, FL_LDSCHED | FL_FOR_ARCH4T, fast= mul) -ARM_CORE("arm922t", arm922t, arm922t, 4T, FL_LDSCHED | FL_FOR_ARCH4T, fast= mul) -ARM_CORE("arm940t", arm940t, arm940t, 4T, FL_LDSCHED | FL_FOR_ARCH4T, fast= mul) -ARM_CORE("ep9312", ep9312, ep9312, 4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmu= l) +ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PRO= C | FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, 4T, ARM_FSET_MAKE_CPU1 (FL_CO= _PROC | FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm710t", arm710t, arm710t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL= _FOR_ARCH4T), fastmul) +ARM_CORE("arm720t", arm720t, arm720t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL= _FOR_ARCH4T), fastmul) +ARM_CORE("arm740t", arm740t, arm740t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL= _FOR_ARCH4T), fastmul) +ARM_CORE("arm9", arm9, arm9, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_= ARCH4T), fastmul) +ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHE= D | FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm920", arm920, arm920, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | F= L_FOR_ARCH4T), fastmul) +ARM_CORE("arm920t", arm920t, arm920t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED |= FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm922t", arm922t, arm922t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED |= FL_FOR_ARCH4T), fastmul) +ARM_CORE("arm940t", arm940t, arm940t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED |= FL_FOR_ARCH4T), fastmul) +ARM_CORE("ep9312", ep9312, ep9312, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | F= L_FOR_ARCH4T), fastmul) =20 /* V5T Architecture Processors */ -ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, 5T, FL_LDSCHED | FL_FOR_ARCH5T= , fastmul) -ARM_CORE("arm1020t", arm1020t, arm1020t, 5T, FL_LDSCHED | FL_FOR_ARCH5T, f= astmul) +ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH5T), fastmul) +ARM_CORE("arm1020t", arm1020t, arm1020t, 5T, ARM_FSET_MAKE_CPU1 (FL_LDSCHE= D | FL_FOR_ARCH5T), fastmul) =20 /* V5TE Architecture Processors */ -ARM_CORE("arm9e", arm9e, arm9e, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e) -ARM_CORE("arm946e-s", arm946es, arm946es, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE= , 9e) -ARM_CORE("arm966e-s", arm966es, arm966es, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE= , 9e) -ARM_CORE("arm968e-s", arm968es, arm968es, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE= , 9e) -ARM_CORE("arm10e", arm10e, arm10e, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fast= mul) -ARM_CORE("arm1020e", arm1020e, arm1020e, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE,= fastmul) -ARM_CORE("arm1022e", arm1022e, arm1022e, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE,= fastmul) -ARM_CORE("xscale", xscale, xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCAL= E | FL_FOR_ARCH5TE, xscale) -ARM_CORE("iwmmxt", iwmmxt, iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCAL= E | FL_IWMMXT | FL_FOR_ARCH5TE, xscale) -ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSC= ALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE, xscale) -ARM_CORE("fa606te", fa606te, fa606te, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e) -ARM_CORE("fa626te", fa626te, fa626te, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e) -ARM_CORE("fmp626", fmp626, fmp626, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e) -ARM_CORE("fa726te", fa726te, fa726te, 5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fa= 726te) +ARM_CORE("arm9e", arm9e, arm9e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_= FOR_ARCH5TE), 9e) +ARM_CORE("arm946e-s", arm946es, arm946es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSC= HED | FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm966e-s", arm966es, arm966es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSC= HED | FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm968e-s", arm968es, arm968es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSC= HED | FL_FOR_ARCH5TE), 9e) +ARM_CORE("arm10e", arm10e, arm10e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | = FL_FOR_ARCH5TE), fastmul) +ARM_CORE("arm1020e", arm1020e, arm1020e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCH= ED | FL_FOR_ARCH5TE), fastmul) +ARM_CORE("arm1022e", arm1022e, arm1022e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCH= ED | FL_FOR_ARCH5TE), fastmul) +ARM_CORE("xscale", xscale, xscale, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | = FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE), xscale) +ARM_CORE("iwmmxt", iwmmxt, iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | = FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale) +ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED = | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale) +ARM_CORE("fa606te", fa606te, fa606te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED = | FL_FOR_ARCH5TE), 9e) +ARM_CORE("fa626te", fa626te, fa626te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED = | FL_FOR_ARCH5TE), 9e) +ARM_CORE("fmp626", fmp626, fmp626, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | = FL_FOR_ARCH5TE), 9e) +ARM_CORE("fa726te", fa726te, fa726te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED = | FL_FOR_ARCH5TE), fa726te) =20 /* V5TEJ Architecture Processors */ -ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, 5TEJ, FL_LDSCHED | FL_FOR_ARC= H5TEJ, 9e) -ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, 5TEJ, FL_LDSCHED | FL_FOR_= ARCH5TEJ, 9e) +ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_= LDSCHED | FL_FOR_ARCH5TEJ), 9e) +ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, 5TEJ, ARM_FSET_MAKE_CPU1 (= FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e) =20 /* V6 Architecture Processors */ -ARM_CORE("arm1136j-s", arm1136js, arm1136js, 6J, FL_LDSCHED | FL_FOR_AR= CH6J, 9e) -ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, 6J, FL_LDSCHED | FL_VFP= V2 | FL_FOR_ARCH6J, 9e) -ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, 6ZK, FL_LDSCHED | FL_FOR= _ARCH6ZK, 9e) -ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, 6ZK, FL_LDSCHED | FL_VF= PV2 | FL_FOR_ARCH6ZK, 9e) -ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, 6K, FL_LDSCHED | FL_FO= R_ARCH6K, 9e) -ARM_CORE("mpcore", mpcore, mpcore, 6K, FL_LDSCHED | FL_VFPV2 | FL_FOR_= ARCH6K, 9e) -ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, 6T2, FL_LDSCHED | FL_FOR= _ARCH6T2, v6t2) -ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, 6T2, FL_LDSCHED | FL_VF= PV2 | FL_FOR_ARCH6T2, v6t2) +ARM_CORE("arm1136j-s", arm1136js, arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_= LDSCHED | FL_FOR_ARCH6J), 9e) +ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, 6J, ARM_FSET_MAKE_CPU1 (= FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J), 9e) +ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, 6ZK, ARM_FSET_MAKE_CPU1 = (FL_LDSCHED | FL_FOR_ARCH6ZK), 9e) +ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, 6ZK, ARM_FSET_MAKE_CPU1= (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK), 9e) +ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, 6K, ARM_FSET_MAKE_CPU1 = (FL_LDSCHED | FL_FOR_ARCH6K), 9e) +ARM_CORE("mpcore", mpcore, mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_LDSCHED |= FL_VFPV2 | FL_FOR_ARCH6K), 9e) +ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 = (FL_LDSCHED | FL_FOR_ARCH6T2), v6t2) +ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, 6T2, ARM_FSET_MAKE_CPU1= (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2), v6t2) =20 /* V6M Architecture Processors */ -ARM_CORE("cortex-m1", cortexm1, cortexm1, 6M, FL_LDSCHED | FL_FOR_ARCH6M= , v6m) -ARM_CORE("cortex-m0", cortexm0, cortexm0, 6M, FL_LDSCHED | FL_FOR_ARCH6M= , v6m) -ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, FL_LDSCHED | FL_= FOR_ARCH6M, v6m) +ARM_CORE("cortex-m1", cortexm1, cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0", cortexm0, cortexm0, 6M, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, ARM_FSET_MAKE_CP= U1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m) =20 /* V6M Architecture Processors for small-multiply implementations. */ -ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, 6M, = FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m) -ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, 6M, = FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m) -ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm= 0plus,6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m) +ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, 6M, = ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, 6M, = ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m) +ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm= 0plus,6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6= m) =20 /* V7 Architecture Processors */ -ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, FL_LDSCHED | FL_= FOR_ARCH7A, cortex) -ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, FL_LDSCHED | FL_FOR_ARCH7= A, cortex_a5) -ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV= | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a7) -ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, FL_LDSCHED | FL_FOR_ARCH7= A, cortex_a8) -ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, FL_LDSCHED | FL_FOR_ARCH7= A, cortex_a9) -ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, FL_LDSCHED | FL_THUMB_= DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12) -ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, FL_LDSCHED | FL_THUMB_= DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15) -ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, FL_LDSCHED | FL_THUMB_= DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12) -ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, FL_LDSCHED | FL_FOR_ARCH7= R, cortex) -ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, FL_LDSCHED | FL_FOR_AR= CH7R, cortex) -ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV |= FL_FOR_ARCH7R, cortex) -ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV |= FL_FOR_ARCH7R, cortex) -ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED | FL_NO_VOLATI= LE_CE | FL_FOR_ARCH7EM, cortex_m7) -ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED | FL_FOR_ARCH7= EM, v7m) -ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED | FL_FOR_ARCH7= M, v7m) -ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED | FL_FO= R_ARCH7A, marvell_pj4) +ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, ARM_FSET_MAKE_CPU= 1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex) +ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH7A), cortex_a5) +ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7) +ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH7A), cortex_a8) +ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH7A), cortex_a9) +ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_= LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_= LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15) +ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_= LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) +ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, ARM_FSET_MAKE_CPU1 (FL_= LDSCHED | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex) +ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, ARM_FSET_MAKE_CPU1 (FL_LD= SCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7) +ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_LD= SCHED | FL_FOR_ARCH7EM), v7m) +ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_FOR_ARCH7M), v7m) +ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, ARM_FSET_MAKE_CPU1 = (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4) =20 /* V7 big.LITTLE implementations */ -ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSC= HED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15) -ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSC= HED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12) +ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET= _MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex= _a15) +ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET= _MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex= _a12) =20 /* V8 Architecture Processors */ -ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32 | F= L_FOR_ARCH8A, cortex_a53) -ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32 | F= L_FOR_ARCH8A, cortex_a57) -ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32 | F= L_FOR_ARCH8A, cortex_a57) -ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, FL_LDSCHED | FL_CRC32 | FL= _FOR_ARCH8A, cortex_a57) -ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED | FL_FOR_AR= CH8A, xgene1) +ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LD= SCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) +ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LD= SCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LD= SCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDS= CHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL= _LDSCHED | FL_FOR_ARCH8A), xgene1) =20 /* V8 big.LITTLE implementations */ -ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, FL_L= DSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57) -ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, FL_L= DSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57) +ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, ARM_F= SET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, ARM_F= SET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dd892a7..30bd0c9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2198,7 +2198,7 @@ static const struct processors all_cores[] =3D /* ARM Cores */ #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \ {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH, \ - ARM_FSET_MAKE_CPU1 (FLAGS), &arm_##COSTS##_tune}, + FLAGS, &arm_##COSTS##_tune}, #include "arm-cores.def" #undef ARM_CORE {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL} @@ -2211,7 +2211,7 @@ static const struct processors all_architectures[] =3D from the core. */ =20 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \ - {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, ARM_FSET_MAKE_CPU1 (FLAGS), NULL}, + {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL}, #include "arm-arches.def" #undef ARM_ARCH {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL} --=20 1.9.1 --------------090806010008020501000103--