[PATCH 1/4][ARM] Make room for more CPU feature flags.

public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed

* [PATCH 1/4][ARM] Make room for more CPU feature flags.
@ 2015-06-22 15:44 Matthew Wahab
  2015-06-22 15:51 ` [PATCH 2/4][ARM] Add feature set definitions Matthew Wahab
                   ` (3 more replies)
  0 siblings, 4 replies; 8+ messages in thread
From: Matthew Wahab @ 2015-06-22 15:44 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1474 bytes --]

Hello,

The ARM backend uses an unsigned long to record CPU feature flags and there are
currently 30 bits in use. To be able to support new architecture features, the
current representation will need to be replaced so that more flags can be
recorded.

This series of patches replaces the single unsigned long with a representation
based on an array of unsigned longs. Constructors and operations are explicitly
defined for the new representation and the backend is updated to use the new
operations.

The individual patches:
- Make architecture flags explicit in arm-cores.def, to prepare for the changes.
- Add definitions for the new representation as type arm_feature_set and macros
   with prefix ARM_FSET.
- Replace uses of the old representation with the arm_feature_set type and
   operations.
- Rework arm-cores.def and arm-arches.def to make the feature set constructions
   explicit.

The series tested for arm-none-linux-gnueabihf with check-gcc.

This patch moves the derived FL_FOR_ARCH##ARCH flags from the expansion of macro
arm.c/ARM_CORE and makes them explicit in the entries in arm-cores.def.

This patch tested for arm-none-linux-gnueabihf with check-gcc.

Ok for trunk?
Matthew

2015-06-22  Matthew Wahab  <matthew.wahab@arm.com>

	* gcc/config/arm/arm-cores.def: Add FL_FOR_ARCH flag for each
	ARM_CORE entry.  Fix some white-space.
	* gcc/config/arm/arm.c: Remove FL_FOR_ARCH derivation from
	ARM_CORE definition.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-ARM-Make-ARCH-flags-explicit-in-arm-cores.def.patch --]
[-- Type: text/x-patch;  name=0001-ARM-Make-ARCH-flags-explicit-in-arm-cores.def.patch, Size: 19491 bytes --]

From b8d4b4ef938d64996d0d20aaa9974757057aaad2 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 5 Jun 2015 12:33:34 +0100
Subject: [PATCH 1/4] [ARM] Make ARCH flags explicit in arm-cores.def

Change-Id: I13a79c89bebaf82aa921f0502b721ff5d9b92dbe
---
 gcc/config/arm/arm-cores.def | 200 +++++++++++++++++++++----------------------
 gcc/config/arm/arm.c         |   2 +-
 2 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 103c314..f362c27 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -43,134 +43,134 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2", 	arm2, arm2,	2, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm250", 	arm250, arm250,	2, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm2",	arm2, arm2,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
+ARM_CORE("arm250",	arm250, arm250,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
+ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
 /* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26, fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26, fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26, fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED, fastmul)
-ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED, fastmul)
-ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED, fastmul)
-ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED, fastmul)
+ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC, fastmul)
-ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC, fastmul)
-ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF,    fastmul)
-ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF,    fastmul)
-ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF,    fastmul)
-ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
+ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
+ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
+ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED, fastmul)
-ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED, fastmul)
+ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
+ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED, fastmul)
-ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED, fastmul)
-ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED, fastmul)
-ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale)
-ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
-ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale)
-ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED, 9e)
-ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED, fa726te)
+ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
+ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
+ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
+ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE, xscale)
+ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE, xscale)
+ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE, xscale)
+ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED, 9e)
-ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED, 9e)
+ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
+ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED, 9e)
-ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED, 9e)
-ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED, 9e)
-ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED, v6t2)
-ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2, v6t2)
+ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED | FL_FOR_ARCH6J, 9e)
+ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J, 9e)
+ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED | FL_FOR_ARCH6ZK, 9e)
+ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK, 9e)
+ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED | FL_FOR_ARCH6K, 9e)
+ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K, 9e)
+ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED | FL_FOR_ARCH6T2, v6t2)
+ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2, v6t2)
 
 /* V6M Architecture Processors */
-ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED, v6m)
-ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED, v6m)
-ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED, v6m)
+ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
 
 /* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M, FL_LDSCHED | FL_SMALLMUL, v6m)
-ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M, FL_LDSCHED | FL_SMALLMUL, v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, FL_LDSCHED | FL_SMALLMUL, v6m)
+ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
 
 /* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED, cortex)
-ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED, cortex_a5)
-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
-ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED, cortex_a8)
-ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED, cortex_a9)
-ARM_CORE("cortex-a12",	  	cortexa12, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
-ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED, cortex)
-ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED, cortex)
-ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED | FL_NO_VOLATILE_CE, cortex_m7)
-ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED, v7m)
-ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED, v7m)
-ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED, marvell_pj4)
+ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex)
+ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a5)
+ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a7)
+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a8)
+ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a9)
+ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
+ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
+ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
+ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM, cortex_m7)
+ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED | FL_FOR_ARCH7EM, v7m)
+ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED | FL_FOR_ARCH7M, v7m)
+ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED | FL_FOR_ARCH7A, marvell_pj4)
 
 /* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
 
 /* V8 Architecture Processors */
-ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32, cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED,            xgene1)
+ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a53)
+ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED | FL_FOR_ARCH8A,            xgene1)
 
 /* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e79a369..b21f433 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2197,7 +2197,7 @@ static const struct processors all_cores[] =
   /* ARM Cores */
 #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
-    FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
+    FLAGS, &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
   {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH 2/4][ARM] Add feature set definitions.
  2015-06-22 15:44 [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
@ 2015-06-22 15:51 ` Matthew Wahab
  2015-07-24 11:39   ` Matthew Wahab
  2015-06-22 15:54 ` [PATCH 3/4][ARM] Use new feature set representation Matthew Wahab
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 8+ messages in thread
From: Matthew Wahab @ 2015-06-22 15:51 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1162 bytes --]

Hello,

The ARM backend uses an unsigned long to record CPU feature flags and there are
currently 30 bits in use. This series of patches replaces the single unsigned
long with a representation based on an array of values.

This patch adds, but doesn't use, type arm_feature_set and macros prefixed
with ARM_FSET to represent and operate on feature sets.

Tested by building with no errors. Also tested as part of the series, for
arm-none-linux-gnueabihf with check-gcc.

Ok for trunk?
Matthew

gcc/
2015-06-22  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm-protos.h (FL_NONE): New.
	(FL_ANY): New.
	(arm_feature_set): New.
	(ARM_FSET_MAKE): New.
	(ARM_FSET_MAKE_CPU1): New.
	(ARM_FSET_MAKE_CPU2): New.
	(ARM_FSET_CPU1): New.
	(ARM_FSET_CPU2): New.
	(ARM_FSET_EMPTY): New.
	(ARM_FSET_ANY): New.
	(ARM_FSET_HAS_CPU1): New.
	(ARM_FSET_HAS_CPU2): New.
	(ARM_FSET_ADD_CPU1): New.
	(ARM_FSET_ADD_CPU2): New.
	(ARM_FSET_DEL_CPU1): New.
	(ARM_FSET_DEL_CPU2): New.
	(ARM_FSET_UNION): New.
	(ARM_FSET_INTER): New.
	(ARM_FSET_XOR): New.
	(ARM_FSET_EXCLUDE): New.
	(AFM_FSET_IS_EMPTY): New.
	(ARM_FSET_CPU_SUBSET): New.


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0002-Add-feature-set-definitions.patch --]
[-- Type: text/x-patch; name=0002-Add-feature-set-definitions.patch, Size: 4065 bytes --]

From 1a98a80b64427f7bb97212ae9ecff515e980ddb7 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 4 Jun 2015 15:35:25 +0100
Subject: [PATCH 2/4] Add feature set definitions.

Change-Id: I5f89b46ea57e35f477ec4751fea3cb6ee8fce251
---
 gcc/config/arm/arm-protos.h | 101 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 62f91ef..a19d54d 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -346,6 +346,8 @@ extern bool arm_is_constant_pool_ref (rtx);
 /* Flags used to identify the presence of processor capabilities.  */
 
 /* Bit values used to identify processor capabilities.  */
+#define FL_NONE	      (0)	      /* No flags.  */
+#define FL_ANY	      (0xffffffff)    /* All flags.  */
 #define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
 #define FL_ARCH3M     (1 << 1)        /* Extended multiply */
 #define FL_MODE26     (1 << 2)        /* 26-bit mode support */
@@ -412,6 +414,105 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
 #define FL_FOR_ARCH8A	(FL_FOR_ARCH7VE | FL_ARCH8)
 
+/* There are too many feature bits to fit in a single word so the set of cpu and
+   fpu capabilities is a structure.  A feature set is created and manipulated
+   with the ARM_FSET macros.  */
+
+typedef struct
+{
+  unsigned long cpu[2];
+} arm_feature_set;
+
+
+/* Initialize a feature set.  */
+
+#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
+
+#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
+#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
+
+/* Accessors.  */
+
+#define ARM_FSET_CPU1(S) ((S).cpu[0])
+#define ARM_FSET_CPU2(S) ((S).cpu[1])
+
+/* Useful combinations.  */
+
+#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
+#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
+
+/* Tests for a specific CPU feature.  */
+
+#define ARM_FSET_HAS_CPU1(A, F)  (((A).cpu[0] & (F)) == F)
+#define ARM_FSET_HAS_CPU2(A, F)  (((A).cpu[1] & (F)) == F)
+
+/* Add a feature to a feature set.  */
+
+#define ARM_FSET_ADD_CPU1(DST, F)		\
+  do {						\
+    (DST).cpu[0] |= (F);			\
+  } while (0)
+
+#define ARM_FSET_ADD_CPU2(DST, F)		\
+  do {						\
+    (DST).cpu[1] |= (F);			\
+  } while (0)
+
+/* Remove a feature from a feature set.  */
+
+#define ARM_FSET_DEL_CPU1(DST, F)		\
+  do {						\
+    (DST).cpu[0] &= ~(F);			\
+  } while (0)
+
+#define ARM_FSET_DEL_CPU2(DST, F)		\
+  do {						\
+    (DST).cpu[1] &= ~(F);			\
+  } while (0)
+
+/* Union of feature sets.  */
+
+#define ARM_FSET_UNION(DST,F1,F2)		\
+  do {						\
+    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];	\
+    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];	\
+  } while (0)
+
+/* Intersection of feature sets.  */
+
+#define ARM_FSET_INTER(DST,F1,F2)		\
+  do {						\
+    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];	\
+    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];	\
+  } while (0)
+
+/* Exclusive disjunction.  */
+
+#define ARM_FSET_XOR(DST,F1,F2)				\
+  do {							\
+    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];		\
+    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];		\
+  } while (0)
+
+/* Difference of feature sets: F1 excluding the elements of F2.  */
+
+#define ARM_FSET_EXCLUDE(DST,F1,F2)		\
+  do {						\
+    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];	\
+    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];	\
+  } while (0)
+
+/* Test for an empty feature set.  */
+
+#define ARM_FSET_IS_EMPTY(A)		\
+  (!((A).cpu[0]) && !((A).cpu[1]))
+
+/* Tests whether the cpu features of A are a subset of B.  */
+
+#define ARM_FSET_CPU_SUBSET(A,B)					\
+  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])				\
+   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
+
 /* The bits in this mask specify which
    instructions we are allowed to generate.  */
 extern unsigned long insn_flags;
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 2/4][ARM] Add feature set definitions.
  2015-06-22 15:51 ` [PATCH 2/4][ARM] Add feature set definitions Matthew Wahab
@ 2015-07-24 11:39   ` Matthew Wahab
  0 siblings, 0 replies; 8+ messages in thread
From: Matthew Wahab @ 2015-07-24 11:39 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1412 bytes --]

Ping. Updated patch attached.

Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and
make check and arm-none-eabi with cross-compiled make check.


On 22/06/15 16:45, Matthew Wahab wrote:
> Hello,
>
> The ARM backend uses an unsigned long to record CPU feature flags and there are
> currently 30 bits in use. This series of patches replaces the single unsigned
> long with a representation based on an array of values.
>
> This patch adds, but doesn't use, type arm_feature_set and macros prefixed
> with ARM_FSET to represent and operate on feature sets.
>
> Tested by building with no errors. Also tested as part of the series, for
> arm-none-linux-gnueabihf with check-gcc.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-06-22  Matthew Wahab  <matthew.wahab@arm.com>
>
> 	* config/arm/arm-protos.h (FL_NONE): New.
> 	(FL_ANY): New.
> 	(arm_feature_set): New.
> 	(ARM_FSET_MAKE): New.
> 	(ARM_FSET_MAKE_CPU1): New.
> 	(ARM_FSET_MAKE_CPU2): New.
> 	(ARM_FSET_CPU1): New.
> 	(ARM_FSET_CPU2): New.
> 	(ARM_FSET_EMPTY): New.
> 	(ARM_FSET_ANY): New.
> 	(ARM_FSET_HAS_CPU1): New.
> 	(ARM_FSET_HAS_CPU2): New.
> 	(ARM_FSET_ADD_CPU1): New.
> 	(ARM_FSET_ADD_CPU2): New.
> 	(ARM_FSET_DEL_CPU1): New.
> 	(ARM_FSET_DEL_CPU2): New.
> 	(ARM_FSET_UNION): New.
> 	(ARM_FSET_INTER): New.
> 	(ARM_FSET_XOR): New.
> 	(ARM_FSET_EXCLUDE): New.
> 	(AFM_FSET_IS_EMPTY): New.
> 	(ARM_FSET_CPU_SUBSET): New.
>


[-- Attachment #2: 0002-Add-feature-set-definitions.patch --]
[-- Type: text/x-patch, Size: 3933 bytes --]

From f977c65b06b0a55a6d371004d0cc64ba216ee954 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 4 Jun 2015 15:35:25 +0100
Subject: [PATCH 2/4] Add feature set definitions.

Change-Id: I5f89b46ea57e35f477ec4751fea3cb6ee8fce251
---
 gcc/config/arm/arm-protos.h | 101 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 62f91ef..a19d54d 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -346,6 +346,8 @@ extern bool arm_is_constant_pool_ref (rtx);
 /* Flags used to identify the presence of processor capabilities.  */
 
 /* Bit values used to identify processor capabilities.  */
+#define FL_NONE	      (0)	      /* No flags.  */
+#define FL_ANY	      (0xffffffff)    /* All flags.  */
 #define FL_CO_PROC    (1 << 0)        /* Has external co-processor bus */
 #define FL_ARCH3M     (1 << 1)        /* Extended multiply */
 #define FL_MODE26     (1 << 2)        /* 26-bit mode support */
@@ -412,6 +414,105 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_FOR_ARCH7EM  (FL_FOR_ARCH7M | FL_ARCH7EM)
 #define FL_FOR_ARCH8A	(FL_FOR_ARCH7VE | FL_ARCH8)
 
+/* There are too many feature bits to fit in a single word so the set of cpu and
+   fpu capabilities is a structure.  A feature set is created and manipulated
+   with the ARM_FSET macros.  */
+
+typedef struct
+{
+  unsigned long cpu[2];
+} arm_feature_set;
+
+
+/* Initialize a feature set.  */
+
+#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
+
+#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
+#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
+
+/* Accessors.  */
+
+#define ARM_FSET_CPU1(S) ((S).cpu[0])
+#define ARM_FSET_CPU2(S) ((S).cpu[1])
+
+/* Useful combinations.  */
+
+#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
+#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
+
+/* Tests for a specific CPU feature.  */
+
+#define ARM_FSET_HAS_CPU1(A, F)  (((A).cpu[0] & (F)) == F)
+#define ARM_FSET_HAS_CPU2(A, F)  (((A).cpu[1] & (F)) == F)
+
+/* Add a feature to a feature set.  */
+
+#define ARM_FSET_ADD_CPU1(DST, F)		\
+  do {						\
+    (DST).cpu[0] |= (F);			\
+  } while (0)
+
+#define ARM_FSET_ADD_CPU2(DST, F)		\
+  do {						\
+    (DST).cpu[1] |= (F);			\
+  } while (0)
+
+/* Remove a feature from a feature set.  */
+
+#define ARM_FSET_DEL_CPU1(DST, F)		\
+  do {						\
+    (DST).cpu[0] &= ~(F);			\
+  } while (0)
+
+#define ARM_FSET_DEL_CPU2(DST, F)		\
+  do {						\
+    (DST).cpu[1] &= ~(F);			\
+  } while (0)
+
+/* Union of feature sets.  */
+
+#define ARM_FSET_UNION(DST,F1,F2)		\
+  do {						\
+    (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0];	\
+    (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1];	\
+  } while (0)
+
+/* Intersection of feature sets.  */
+
+#define ARM_FSET_INTER(DST,F1,F2)		\
+  do {						\
+    (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0];	\
+    (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1];	\
+  } while (0)
+
+/* Exclusive disjunction.  */
+
+#define ARM_FSET_XOR(DST,F1,F2)				\
+  do {							\
+    (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0];		\
+    (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1];		\
+  } while (0)
+
+/* Difference of feature sets: F1 excluding the elements of F2.  */
+
+#define ARM_FSET_EXCLUDE(DST,F1,F2)		\
+  do {						\
+    (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0];	\
+    (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1];	\
+  } while (0)
+
+/* Test for an empty feature set.  */
+
+#define ARM_FSET_IS_EMPTY(A)		\
+  (!((A).cpu[0]) && !((A).cpu[1]))
+
+/* Tests whether the cpu features of A are a subset of B.  */
+
+#define ARM_FSET_CPU_SUBSET(A,B)					\
+  ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0])				\
+   && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
+
 /* The bits in this mask specify which
    instructions we are allowed to generate.  */
 extern unsigned long insn_flags;
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH 3/4][ARM] Use new feature set representation.
  2015-06-22 15:44 [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
  2015-06-22 15:51 ` [PATCH 2/4][ARM] Add feature set definitions Matthew Wahab
@ 2015-06-22 15:54 ` Matthew Wahab
  2015-07-24 11:41   ` Matthew Wahab
  2015-06-22 16:07 ` [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def Matthew Wahab
  2015-07-24 11:36 ` [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
  3 siblings, 1 reply; 8+ messages in thread
From: Matthew Wahab @ 2015-06-22 15:54 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1205 bytes --]

Hello,

The ARM backend uses an unsigned long to record CPU feature flags and there are
currently 30 bits in use. This series of patches replaces the single unsigned
long with a representation based on an array of values.

This patch replaces the existing representation of CPU feature sets with the
type arm_feature_set and ARM_FSET macros added in an earlier patch in this
series.

Tested arm-none-linux-gnueabihf with check-gcc. Also tested as part of the
series for arm-none-linux-gnueabihf with check-gcc.

Ok for trunk?
Matthew

gcc/
2015-06-22  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm-builtins.c (def_mbuiltin): Use ARM_FSET macro.
	* config/arm/arm-protos.h (insn_flags): Declare as type
	arm_feature_set.
	(tune_flags): Likewise.
	* config/arm/arm.c (feature_count): New.
	(insn_flags): Define as type arm_feature_set.
	(tune_flags): Likewise.
	(struct processors): Define field flags as type arm_feature_set.
	(all_cores): Update for change to struct processors.
	(all_architectures): Likewise.
	(arm_option_check_internal): Use arm_feature_set and ARM_FSET macros.
	(arm_option_override_internal): Likewise.
	(arm_option_override): Likewise.


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0003-Use-feature-sets.patch --]
[-- Type: text/x-patch; name=0003-Use-feature-sets.patch, Size: 12649 bytes --]

From 8b5e132868da066eb8a8673286b796656b9ed127 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 8 Jun 2015 14:11:13 +0100
Subject: [PATCH 3/4] Use feature sets.

Change-Id: I5a1b162102dd19b6376637218dc548502112cf4b
---
 gcc/config/arm/arm-builtins.c |   4 +-
 gcc/config/arm/arm-protos.h   |   4 +-
 gcc/config/arm/arm.c          | 131 ++++++++++++++++++++++++------------------
 3 files changed, 80 insertions(+), 59 deletions(-)

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index f960e0a..31203d4 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -1074,10 +1074,10 @@ arm_init_neon_builtins (void)
 #undef NUM_DREG_TYPES
 #undef NUM_QREG_TYPES
 
-#define def_mbuiltin(MASK, NAME, TYPE, CODE)				\
+#define def_mbuiltin(FLAG, NAME, TYPE, CODE)				\
   do									\
     {									\
-      if ((MASK) & insn_flags)						\
+      if (ARM_FSET_HAS_CPU1 (insn_flags, (FLAG)))			\
 	{								\
 	  tree bdecl;							\
 	  bdecl = add_builtin_function ((NAME), (TYPE), (CODE),		\
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index a19d54d..859b5d2 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -515,11 +515,11 @@ typedef struct
 
 /* The bits in this mask specify which
    instructions we are allowed to generate.  */
-extern unsigned long insn_flags;
+extern arm_feature_set insn_flags;
 
 /* The bits in this mask specify which instruction scheduling options should
    be used.  */
-extern unsigned long tune_flags;
+extern arm_feature_set tune_flags;
 
 /* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
 extern int arm_arch3m;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index b21f433..dd892a7 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -105,6 +105,7 @@ static void arm_add_gc_roots (void);
 static int arm_gen_constant (enum rtx_code, machine_mode, rtx,
 			     HOST_WIDE_INT, rtx, rtx, int, int);
 static unsigned bit_count (unsigned long);
+static unsigned feature_count (const arm_feature_set*);
 static int arm_address_register_rtx_p (rtx, int);
 static int arm_legitimate_index_p (machine_mode, rtx, RTX_CODE, int);
 static bool is_called_in_ARM_mode (tree);
@@ -771,11 +772,11 @@ static int thumb_call_reg_needed;
 
 /* The bits in this mask specify which
    instructions we are allowed to generate.  */
-unsigned long insn_flags = 0;
+arm_feature_set insn_flags = ARM_FSET_EMPTY;
 
 /* The bits in this mask specify which instruction scheduling options should
    be used.  */
-unsigned long tune_flags = 0;
+arm_feature_set tune_flags = ARM_FSET_EMPTY;
 
 /* The highest ARM architecture version supported by the
    target.  */
@@ -928,7 +929,7 @@ struct processors
   enum processor_type core;
   const char *arch;
   enum base_architecture base_arch;
-  const unsigned long flags;
+  const arm_feature_set flags;
   const struct tune_params *const tune;
 };
 
@@ -2197,10 +2198,10 @@ static const struct processors all_cores[] =
   /* ARM Cores */
 #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
-    FLAGS, &arm_##COSTS##_tune},
+   ARM_FSET_MAKE_CPU1 (FLAGS), &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
-  {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
+  {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
 };
 
 static const struct processors all_architectures[] =
@@ -2210,10 +2211,10 @@ static const struct processors all_architectures[] =
      from the core.  */
 
 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
-  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
+  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, ARM_FSET_MAKE_CPU1 (FLAGS), NULL},
 #include "arm-arches.def"
 #undef ARM_ARCH
-  {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
+  {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
 };
 
 
@@ -2279,6 +2280,14 @@ bit_count (unsigned long value)
   return count;
 }
 
+/* Return the number of features in feature-set SET.  */
+static unsigned
+feature_count (const arm_feature_set * set)
+{
+  return (bit_count (ARM_FSET_CPU1 (*set))
+	  + bit_count (ARM_FSET_CPU2 (*set)));
+}
+
 typedef struct
 {
   machine_mode mode;
@@ -2704,7 +2713,7 @@ arm_option_check_internal (struct gcc_options *opts)
 
   /* Make sure that the processor choice does not conflict with any of the
      other command line choices.  */
-  if (TARGET_ARM_P (flags) && !(insn_flags & FL_NOTM))
+  if (TARGET_ARM_P (flags) && !ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM))
     error ("target CPU does not support ARM mode");
 
   /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
@@ -2800,7 +2809,8 @@ static void
 arm_option_override_internal (struct gcc_options *opts,
 			      struct gcc_options *opts_set)
 {
-  if (TARGET_THUMB_P (opts->x_target_flags) && !(insn_flags & FL_THUMB))
+  if (TARGET_THUMB_P (opts->x_target_flags)
+      && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB)))
     {
       warning (0, "target CPU does not support THUMB instructions");
       opts->x_target_flags &= ~MASK_THUMB;
@@ -2887,8 +2897,13 @@ arm_option_override (void)
     {
       if (arm_selected_cpu)
 	{
+	  const arm_feature_set tuning_flags = ARM_FSET_MAKE_CPU1 (FL_TUNE);
+	  arm_feature_set selected_flags;
+	  ARM_FSET_XOR (selected_flags, arm_selected_cpu->flags,
+			arm_selected_arch->flags);
+	  ARM_FSET_EXCLUDE (selected_flags, selected_flags, tuning_flags);
 	  /* Check for conflict between mcpu and march.  */
-	  if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE)
+	  if (!ARM_FSET_IS_EMPTY (selected_flags))
 	    {
 	      warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
 		       arm_selected_cpu->name, arm_selected_arch->name);
@@ -2912,7 +2927,7 @@ arm_option_override (void)
   if (!arm_selected_cpu)
     {
       const struct processors * sel;
-      unsigned int        sought;
+      arm_feature_set sought = ARM_FSET_EMPTY;;
 
       arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
       if (!arm_selected_cpu->name)
@@ -2932,26 +2947,27 @@ arm_option_override (void)
 
       /* Now check to see if the user has specified some command line
 	 switch that require certain abilities from the cpu.  */
-      sought = 0;
 
       if (TARGET_INTERWORK || TARGET_THUMB)
 	{
-	  sought |= (FL_THUMB | FL_MODE32);
+	  ARM_FSET_ADD_CPU1 (sought, FL_THUMB);
+	  ARM_FSET_ADD_CPU1 (sought, FL_MODE32);
 
 	  /* There are no ARM processors that support both APCS-26 and
 	     interworking.  Therefore we force FL_MODE26 to be removed
 	     from insn_flags here (if it was set), so that the search
 	     below will always be able to find a compatible processor.  */
-	  insn_flags &= ~FL_MODE26;
+	  ARM_FSET_DEL_CPU1 (insn_flags, FL_MODE26);
 	}
 
-      if (sought != 0 && ((sought & insn_flags) != sought))
+      if (!ARM_FSET_IS_EMPTY (sought)
+	  && !(ARM_FSET_CPU_SUBSET (sought, insn_flags)))
 	{
 	  /* Try to locate a CPU type that supports all of the abilities
 	     of the default CPU, plus the extra abilities requested by
 	     the user.  */
 	  for (sel = all_cores; sel->name != NULL; sel++)
-	    if ((sel->flags & sought) == (sought | insn_flags))
+	    if (ARM_FSET_CPU_SUBSET (sought, sel->flags))
 	      break;
 
 	  if (sel->name == NULL)
@@ -2971,19 +2987,23 @@ arm_option_override (void)
 		 command line options we scan the array again looking
 		 for a best match.  */
 	      for (sel = all_cores; sel->name != NULL; sel++)
-		if ((sel->flags & sought) == sought)
-		  {
-		    unsigned count;
-
-		    count = bit_count (sel->flags & insn_flags);
-
-		    if (count >= current_bit_count)
-		      {
-			best_fit = sel;
-			current_bit_count = count;
-		      }
-		  }
+		{
+		  arm_feature_set required = ARM_FSET_EMPTY;
+		  ARM_FSET_UNION (required, sought, insn_flags);
+		  if (ARM_FSET_CPU_SUBSET (required, sel->flags))
+		    {
+		      unsigned count;
+		      arm_feature_set flags;
+		      ARM_FSET_INTER (flags, sel->flags, insn_flags);
+		      count = feature_count (&flags);
 
+		      if (count >= current_bit_count)
+			{
+			  best_fit = sel;
+			  current_bit_count = count;
+			}
+		    }
+		}
 	      gcc_assert (best_fit);
 	      sel = best_fit;
 	    }
@@ -3011,7 +3031,8 @@ arm_option_override (void)
 
   /* BPABI targets use linker tricks to allow interworking on cores
      without thumb support.  */
-  if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI))
+  if (TARGET_INTERWORK
+      && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB) || TARGET_BPABI))
     {
       warning (0, "target CPU does not support interworking" );
       target_flags &= ~MASK_INTERWORK;
@@ -3036,33 +3057,33 @@ arm_option_override (void)
     warning (0, "passing floating point arguments in fp regs not yet supported");
 
   /* Initialize boolean versions of the flags, for use in the arm.md file.  */
-  arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
-  arm_arch4 = (insn_flags & FL_ARCH4) != 0;
-  arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
-  arm_arch5 = (insn_flags & FL_ARCH5) != 0;
-  arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
-  arm_arch6 = (insn_flags & FL_ARCH6) != 0;
-  arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
-  arm_arch_notm = (insn_flags & FL_NOTM) != 0;
+  arm_arch3m = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH3M);
+  arm_arch4 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH4);
+  arm_arch4t = arm_arch4 && (ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB));
+  arm_arch5 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5);
+  arm_arch5e = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5E);
+  arm_arch6 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6);
+  arm_arch6k = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6K);
+  arm_arch_notm = ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM);
   arm_arch6m = arm_arch6 && !arm_arch_notm;
-  arm_arch7 = (insn_flags & FL_ARCH7) != 0;
-  arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
-  arm_arch8 = (insn_flags & FL_ARCH8) != 0;
-  arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
-  arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
-
-  arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
-  arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
-  arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
-  arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
-  arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
-  arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0;
-  arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
-  arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
-  arm_arch_no_volatile_ce = (insn_flags & FL_NO_VOLATILE_CE) != 0;
+  arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7);
+  arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
+  arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+  arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
+  arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
+
+  arm_ld_sched = ARM_FSET_HAS_CPU1 (tune_flags, FL_LDSCHED);
+  arm_tune_strongarm = ARM_FSET_HAS_CPU1 (tune_flags, FL_STRONG);
+  arm_tune_wbuf = ARM_FSET_HAS_CPU1 (tune_flags, FL_WBUF);
+  arm_tune_xscale = ARM_FSET_HAS_CPU1 (tune_flags, FL_XSCALE);
+  arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT);
+  arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2);
+  arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV);
+  arm_arch_arm_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARM_DIV);
+  arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
-  arm_arch_crc = (insn_flags & FL_CRC32) != 0;
-  arm_m_profile_small_mul = (insn_flags & FL_SMALLMUL) != 0;
+  arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
+  arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL);
 
   /* V5 code we generate is completely interworking capable, so we turn off
      TARGET_INTERWORK here to avoid many tests later on.  */
@@ -3154,7 +3175,7 @@ arm_option_override (void)
 
   /* For arm2/3 there is no need to do any scheduling if we are doing
      software floating-point.  */
-  if (TARGET_SOFT_FLOAT && (tune_flags & FL_MODE32) == 0)
+  if (TARGET_SOFT_FLOAT && !ARM_FSET_HAS_CPU1 (tune_flags, FL_MODE32))
     flag_schedule_insns = flag_schedule_insns_after_reload = 0;
 
   /* Use the cp15 method if it is available.  */
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 3/4][ARM] Use new feature set representation.
  2015-06-22 15:54 ` [PATCH 3/4][ARM] Use new feature set representation Matthew Wahab
@ 2015-07-24 11:41   ` Matthew Wahab
  0 siblings, 0 replies; 8+ messages in thread
From: Matthew Wahab @ 2015-07-24 11:41 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1447 bytes --]

Ping. Updated patch attached.

Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and
make check and arm-none-eabi with cross-compiled make check.


On 22/06/15 16:52, Matthew Wahab wrote:
> Hello,
>
> The ARM backend uses an unsigned long to record CPU feature flags and there are
> currently 30 bits in use. This series of patches replaces the single unsigned
> long with a representation based on an array of values.
>
> This patch replaces the existing representation of CPU feature sets with the
> type arm_feature_set and ARM_FSET macros added in an earlier patch in this
> series.
>
> Tested arm-none-linux-gnueabihf with check-gcc. Also tested as part of the
> series for arm-none-linux-gnueabihf with check-gcc.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-06-22  Matthew Wahab  <matthew.wahab@arm.com>
>
> 	* config/arm/arm-builtins.c (def_mbuiltin): Use ARM_FSET macro.
> 	* config/arm/arm-protos.h (insn_flags): Declare as type
> 	arm_feature_set.
> 	(tune_flags): Likewise.
> 	* config/arm/arm.c (feature_count): New.
> 	(insn_flags): Define as type arm_feature_set.
> 	(tune_flags): Likewise.
> 	(struct processors): Define field flags as type arm_feature_set.
> 	(all_cores): Update for change to struct processors.
> 	(all_architectures): Likewise.
> 	(arm_option_check_internal): Use arm_feature_set and ARM_FSET macros.
> 	(arm_option_override_internal): Likewise.
> 	(arm_option_override): Likewise.
>


[-- Attachment #2: 0003-Use-feature-sets.patch --]
[-- Type: text/x-patch, Size: 12331 bytes --]

From 2a4ecb02633d41f965e8e05a374700125211a440 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 8 Jun 2015 14:11:13 +0100
Subject: [PATCH 3/4] Use feature sets.

Change-Id: I5a1b162102dd19b6376637218dc548502112cf4b
---
 gcc/config/arm/arm-builtins.c |   4 +-
 gcc/config/arm/arm-protos.h   |   4 +-
 gcc/config/arm/arm.c          | 131 ++++++++++++++++++++++++------------------
 3 files changed, 80 insertions(+), 59 deletions(-)

diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 65e72a4..5c03315 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -1072,10 +1072,10 @@ arm_init_neon_builtins (void)
 #undef NUM_DREG_TYPES
 #undef NUM_QREG_TYPES
 
-#define def_mbuiltin(MASK, NAME, TYPE, CODE)				\
+#define def_mbuiltin(FLAG, NAME, TYPE, CODE)				\
   do									\
     {									\
-      if ((MASK) & insn_flags)						\
+      if (ARM_FSET_HAS_CPU1 (insn_flags, (FLAG)))			\
 	{								\
 	  tree bdecl;							\
 	  bdecl = add_builtin_function ((NAME), (TYPE), (CODE),		\
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index a19d54d..859b5d2 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -515,11 +515,11 @@ typedef struct
 
 /* The bits in this mask specify which
    instructions we are allowed to generate.  */
-extern unsigned long insn_flags;
+extern arm_feature_set insn_flags;
 
 /* The bits in this mask specify which instruction scheduling options should
    be used.  */
-extern unsigned long tune_flags;
+extern arm_feature_set tune_flags;
 
 /* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
 extern int arm_arch3m;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4f90203..4190b3f 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -97,6 +97,7 @@ static void arm_add_gc_roots (void);
 static int arm_gen_constant (enum rtx_code, machine_mode, rtx,
 			     HOST_WIDE_INT, rtx, rtx, int, int);
 static unsigned bit_count (unsigned long);
+static unsigned feature_count (const arm_feature_set*);
 static int arm_address_register_rtx_p (rtx, int);
 static int arm_legitimate_index_p (machine_mode, rtx, RTX_CODE, int);
 static bool is_called_in_ARM_mode (tree);
@@ -767,11 +768,11 @@ static int thumb_call_reg_needed;
 
 /* The bits in this mask specify which
    instructions we are allowed to generate.  */
-unsigned long insn_flags = 0;
+arm_feature_set insn_flags = ARM_FSET_EMPTY;
 
 /* The bits in this mask specify which instruction scheduling options should
    be used.  */
-unsigned long tune_flags = 0;
+arm_feature_set tune_flags = ARM_FSET_EMPTY;
 
 /* The highest ARM architecture version supported by the
    target.  */
@@ -924,7 +925,7 @@ struct processors
   enum processor_type core;
   const char *arch;
   enum base_architecture base_arch;
-  const unsigned long flags;
+  const arm_feature_set flags;
   const struct tune_params *const tune;
 };
 
@@ -2193,10 +2194,10 @@ static const struct processors all_cores[] =
   /* ARM Cores */
 #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
-    FLAGS, &arm_##COSTS##_tune},
+   ARM_FSET_MAKE_CPU1 (FLAGS), &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
-  {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
+  {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
 };
 
 static const struct processors all_architectures[] =
@@ -2206,10 +2207,10 @@ static const struct processors all_architectures[] =
      from the core.  */
 
 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
-  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
+  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, ARM_FSET_MAKE_CPU1 (FLAGS), NULL},
 #include "arm-arches.def"
 #undef ARM_ARCH
-  {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
+  {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
 };
 
 
@@ -2275,6 +2276,14 @@ bit_count (unsigned long value)
   return count;
 }
 
+/* Return the number of features in feature-set SET.  */
+static unsigned
+feature_count (const arm_feature_set * set)
+{
+  return (bit_count (ARM_FSET_CPU1 (*set))
+	  + bit_count (ARM_FSET_CPU2 (*set)));
+}
+
 typedef struct
 {
   machine_mode mode;
@@ -2700,7 +2709,7 @@ arm_option_check_internal (struct gcc_options *opts)
 
   /* Make sure that the processor choice does not conflict with any of the
      other command line choices.  */
-  if (TARGET_ARM_P (flags) && !(insn_flags & FL_NOTM))
+  if (TARGET_ARM_P (flags) && !ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM))
     error ("target CPU does not support ARM mode");
 
   /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
@@ -2800,7 +2809,8 @@ static void
 arm_option_override_internal (struct gcc_options *opts,
 			      struct gcc_options *opts_set)
 {
-  if (TARGET_THUMB_P (opts->x_target_flags) && !(insn_flags & FL_THUMB))
+  if (TARGET_THUMB_P (opts->x_target_flags)
+      && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB)))
     {
       warning (0, "target CPU does not support THUMB instructions");
       opts->x_target_flags &= ~MASK_THUMB;
@@ -2887,8 +2897,13 @@ arm_option_override (void)
     {
       if (arm_selected_cpu)
 	{
+	  const arm_feature_set tuning_flags = ARM_FSET_MAKE_CPU1 (FL_TUNE);
+	  arm_feature_set selected_flags;
+	  ARM_FSET_XOR (selected_flags, arm_selected_cpu->flags,
+			arm_selected_arch->flags);
+	  ARM_FSET_EXCLUDE (selected_flags, selected_flags, tuning_flags);
 	  /* Check for conflict between mcpu and march.  */
-	  if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE)
+	  if (!ARM_FSET_IS_EMPTY (selected_flags))
 	    {
 	      warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
 		       arm_selected_cpu->name, arm_selected_arch->name);
@@ -2912,7 +2927,7 @@ arm_option_override (void)
   if (!arm_selected_cpu)
     {
       const struct processors * sel;
-      unsigned int        sought;
+      arm_feature_set sought = ARM_FSET_EMPTY;;
 
       arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
       if (!arm_selected_cpu->name)
@@ -2932,26 +2947,27 @@ arm_option_override (void)
 
       /* Now check to see if the user has specified some command line
 	 switch that require certain abilities from the cpu.  */
-      sought = 0;
 
       if (TARGET_INTERWORK || TARGET_THUMB)
 	{
-	  sought |= (FL_THUMB | FL_MODE32);
+	  ARM_FSET_ADD_CPU1 (sought, FL_THUMB);
+	  ARM_FSET_ADD_CPU1 (sought, FL_MODE32);
 
 	  /* There are no ARM processors that support both APCS-26 and
 	     interworking.  Therefore we force FL_MODE26 to be removed
 	     from insn_flags here (if it was set), so that the search
 	     below will always be able to find a compatible processor.  */
-	  insn_flags &= ~FL_MODE26;
+	  ARM_FSET_DEL_CPU1 (insn_flags, FL_MODE26);
 	}
 
-      if (sought != 0 && ((sought & insn_flags) != sought))
+      if (!ARM_FSET_IS_EMPTY (sought)
+	  && !(ARM_FSET_CPU_SUBSET (sought, insn_flags)))
 	{
 	  /* Try to locate a CPU type that supports all of the abilities
 	     of the default CPU, plus the extra abilities requested by
 	     the user.  */
 	  for (sel = all_cores; sel->name != NULL; sel++)
-	    if ((sel->flags & sought) == (sought | insn_flags))
+	    if (ARM_FSET_CPU_SUBSET (sought, sel->flags))
 	      break;
 
 	  if (sel->name == NULL)
@@ -2971,19 +2987,23 @@ arm_option_override (void)
 		 command line options we scan the array again looking
 		 for a best match.  */
 	      for (sel = all_cores; sel->name != NULL; sel++)
-		if ((sel->flags & sought) == sought)
-		  {
-		    unsigned count;
-
-		    count = bit_count (sel->flags & insn_flags);
-
-		    if (count >= current_bit_count)
-		      {
-			best_fit = sel;
-			current_bit_count = count;
-		      }
-		  }
+		{
+		  arm_feature_set required = ARM_FSET_EMPTY;
+		  ARM_FSET_UNION (required, sought, insn_flags);
+		  if (ARM_FSET_CPU_SUBSET (required, sel->flags))
+		    {
+		      unsigned count;
+		      arm_feature_set flags;
+		      ARM_FSET_INTER (flags, sel->flags, insn_flags);
+		      count = feature_count (&flags);
 
+		      if (count >= current_bit_count)
+			{
+			  best_fit = sel;
+			  current_bit_count = count;
+			}
+		    }
+		}
 	      gcc_assert (best_fit);
 	      sel = best_fit;
 	    }
@@ -3011,7 +3031,8 @@ arm_option_override (void)
 
   /* BPABI targets use linker tricks to allow interworking on cores
      without thumb support.  */
-  if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI))
+  if (TARGET_INTERWORK
+      && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB) || TARGET_BPABI))
     {
       warning (0, "target CPU does not support interworking" );
       target_flags &= ~MASK_INTERWORK;
@@ -3036,33 +3057,33 @@ arm_option_override (void)
     warning (0, "passing floating point arguments in fp regs not yet supported");
 
   /* Initialize boolean versions of the flags, for use in the arm.md file.  */
-  arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
-  arm_arch4 = (insn_flags & FL_ARCH4) != 0;
-  arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
-  arm_arch5 = (insn_flags & FL_ARCH5) != 0;
-  arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
-  arm_arch6 = (insn_flags & FL_ARCH6) != 0;
-  arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
-  arm_arch_notm = (insn_flags & FL_NOTM) != 0;
+  arm_arch3m = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH3M);
+  arm_arch4 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH4);
+  arm_arch4t = arm_arch4 && (ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB));
+  arm_arch5 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5);
+  arm_arch5e = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5E);
+  arm_arch6 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6);
+  arm_arch6k = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6K);
+  arm_arch_notm = ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM);
   arm_arch6m = arm_arch6 && !arm_arch_notm;
-  arm_arch7 = (insn_flags & FL_ARCH7) != 0;
-  arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
-  arm_arch8 = (insn_flags & FL_ARCH8) != 0;
-  arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
-  arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
-
-  arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
-  arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
-  arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
-  arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
-  arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
-  arm_arch_iwmmxt2 = (insn_flags & FL_IWMMXT2) != 0;
-  arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
-  arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
-  arm_arch_no_volatile_ce = (insn_flags & FL_NO_VOLATILE_CE) != 0;
+  arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7);
+  arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
+  arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
+  arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
+  arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
+
+  arm_ld_sched = ARM_FSET_HAS_CPU1 (tune_flags, FL_LDSCHED);
+  arm_tune_strongarm = ARM_FSET_HAS_CPU1 (tune_flags, FL_STRONG);
+  arm_tune_wbuf = ARM_FSET_HAS_CPU1 (tune_flags, FL_WBUF);
+  arm_tune_xscale = ARM_FSET_HAS_CPU1 (tune_flags, FL_XSCALE);
+  arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT);
+  arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2);
+  arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV);
+  arm_arch_arm_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARM_DIV);
+  arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
   arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
-  arm_arch_crc = (insn_flags & FL_CRC32) != 0;
-  arm_m_profile_small_mul = (insn_flags & FL_SMALLMUL) != 0;
+  arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
+  arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL);
 
   /* V5 code we generate is completely interworking capable, so we turn off
      TARGET_INTERWORK here to avoid many tests later on.  */
@@ -3154,7 +3175,7 @@ arm_option_override (void)
 
   /* For arm2/3 there is no need to do any scheduling if we are doing
      software floating-point.  */
-  if (TARGET_SOFT_FLOAT && (tune_flags & FL_MODE32) == 0)
+  if (TARGET_SOFT_FLOAT && !ARM_FSET_HAS_CPU1 (tune_flags, FL_MODE32))
     flag_schedule_insns = flag_schedule_insns_after_reload = 0;
 
   /* Use the cp15 method if it is available.  */
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def
  2015-06-22 15:44 [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
  2015-06-22 15:51 ` [PATCH 2/4][ARM] Add feature set definitions Matthew Wahab
  2015-06-22 15:54 ` [PATCH 3/4][ARM] Use new feature set representation Matthew Wahab
@ 2015-06-22 16:07 ` Matthew Wahab
  2015-07-24 11:48   ` Matthew Wahab
  2015-07-24 11:36 ` [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
  3 siblings, 1 reply; 8+ messages in thread
From: Matthew Wahab @ 2015-06-22 16:07 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1006 bytes --]

Hello,

The ARM backend uses an unsigned long to record CPU feature flags and there are
currently 30 bits in use. This series of patches replaces the single unsigned
long with a representation based on an array of values.

This patch updates the entries in the arm-core.def and arm-arches.def files
for the new arm_feature_set representation, moving the initializers from a macro
expansion and making them explicit in the file entries.

Tested for arm-none-linux-gnueabihf with check-gcc.

Ok for trunk?
Matthew

gcc/
2015-08-22  Matthew Wahab  <matthew.wahab@arm.com>

	* config/arm/arm-arches.def: Replace single value flags with
	initializer built from ARM_FSET_MAKE_CPU1.
	* config/arm/arm-cores.def: Likewise.
	* config/arm/arm.c: (all_cores): Remove ARM_FSET_MAKE_CPU1
	derivation from the ARM_CORE macro definition, use the given value
	instead.
	(all_architectures): Remove ARM_FSET_MAKE_CPU1 derivation from the
	ARM_ARCH macro definition, use the given value instead.


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0004-Move-feature-sets-into-core-and-arch-def-files.patch --]
[-- Type: text/x-patch;  name=0004-Move-feature-sets-into-core-and-arch-def-files.patch, Size: 28966 bytes --]

From 389cfb0e1046b1d84dd3d8920aa5bed50dc19164 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 8 Jun 2015 16:15:52 +0100
Subject: [PATCH 4/4] Move feature sets into core and arch def files.

Change-Id: Ica484c7d9f46413c196b26a630ff49413b10289b
---
 gcc/config/arm/arm-arches.def |  56 ++++++------
 gcc/config/arm/arm-cores.def  | 200 +++++++++++++++++++++---------------------
 gcc/config/arm/arm.c          |   4 +-
 3 files changed, 130 insertions(+), 130 deletions(-)

diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 840c1ff..6d0374a 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -28,33 +28,33 @@
 
    genopt.sh assumes no whitespace up to the first "," in each entry.  */
 
-ARM_ARCH("armv2",   arm2,       2,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2)
-ARM_ARCH("armv2a",  arm2,       2,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2)
-ARM_ARCH("armv3",   arm6,       3,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3)
-ARM_ARCH("armv3m",  arm7m,      3M,  FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M)
-ARM_ARCH("armv4",   arm7tdmi,   4,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4)
+ARM_ARCH("armv2",   arm2,       2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv2a",  arm2,       2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv3",   arm6,       3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3))
+ARM_ARCH("armv3m",  arm7m,      3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M))
+ARM_ARCH("armv4",   arm7tdmi,   4,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4))
 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
    implementations that support it, so we will leave it out for now.  */
-ARM_ARCH("armv4t",  arm7tdmi,   4T,  FL_CO_PROC |             FL_FOR_ARCH4T)
-ARM_ARCH("armv5",   arm10tdmi,  5,   FL_CO_PROC |             FL_FOR_ARCH5)
-ARM_ARCH("armv5t",  arm10tdmi,  5T,  FL_CO_PROC |             FL_FOR_ARCH5T)
-ARM_ARCH("armv5e",  arm1026ejs, 5E,  FL_CO_PROC |             FL_FOR_ARCH5E)
-ARM_ARCH("armv5te", arm1026ejs, 5TE, FL_CO_PROC |             FL_FOR_ARCH5TE)
-ARM_ARCH("armv6",   arm1136js,  6,   FL_CO_PROC |             FL_FOR_ARCH6)
-ARM_ARCH("armv6j",  arm1136js,  6J,  FL_CO_PROC |             FL_FOR_ARCH6J)
-ARM_ARCH("armv6k",  mpcore,	6K,  FL_CO_PROC |             FL_FOR_ARCH6K)
-ARM_ARCH("armv6z",  arm1176jzs, 6Z,  FL_CO_PROC |             FL_FOR_ARCH6Z)
-ARM_ARCH("armv6zk", arm1176jzs, 6ZK, FL_CO_PROC |             FL_FOR_ARCH6ZK)
-ARM_ARCH("armv6t2", arm1156t2s, 6T2, FL_CO_PROC |             FL_FOR_ARCH6T2)
-ARM_ARCH("armv6-m", cortexm1,	6M,			      FL_FOR_ARCH6M)
-ARM_ARCH("armv6s-m", cortexm1,	6M,			      FL_FOR_ARCH6M)
-ARM_ARCH("armv7",   cortexa8,	7,   FL_CO_PROC |	      FL_FOR_ARCH7)
-ARM_ARCH("armv7-a", cortexa8,	7A,  FL_CO_PROC |	      FL_FOR_ARCH7A)
-ARM_ARCH("armv7ve", cortexa8,	7A,  FL_CO_PROC |	      FL_FOR_ARCH7VE)
-ARM_ARCH("armv7-r", cortexr4,	7R,  FL_CO_PROC |	      FL_FOR_ARCH7R)
-ARM_ARCH("armv7-m", cortexm3,	7M,  FL_CO_PROC |	      FL_FOR_ARCH7M)
-ARM_ARCH("armv7e-m", cortexm4,  7EM, FL_CO_PROC |	      FL_FOR_ARCH7EM)
-ARM_ARCH("armv8-a", cortexa53,  8A,  FL_CO_PROC |             FL_FOR_ARCH8A)
-ARM_ARCH("armv8-a+crc",cortexa53, 8A,FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A)
-ARM_ARCH("iwmmxt",  iwmmxt,     5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)
-ARM_ARCH("iwmmxt2", iwmmxt2,    5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
+ARM_ARCH("armv4t",  arm7tdmi,   4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH4T))
+ARM_ARCH("armv5",   arm10tdmi,  5,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5))
+ARM_ARCH("armv5t",  arm10tdmi,  5T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5T))
+ARM_ARCH("armv5e",  arm1026ejs, 5E,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5E))
+ARM_ARCH("armv5te", arm1026ejs, 5TE,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5TE))
+ARM_ARCH("armv6",   arm1136js,  6,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6))
+ARM_ARCH("armv6j",  arm1136js,  6J,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6J))
+ARM_ARCH("armv6k",  mpcore,	6K,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6K))
+ARM_ARCH("armv6z",  arm1176jzs, 6Z,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6Z))
+ARM_ARCH("armv6zk", arm1176jzs, 6ZK,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6ZK))
+ARM_ARCH("armv6t2", arm1156t2s, 6T2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6T2))
+ARM_ARCH("armv6-m", cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv6s-m", cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv7",   cortexa8,	7,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7))
+ARM_ARCH("armv7-a", cortexa8,	7A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7A))
+ARM_ARCH("armv7ve", cortexa8,	7A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7VE))
+ARM_ARCH("armv7-r", cortexr4,	7R,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7R))
+ARM_ARCH("armv7-m", cortexm3,	7M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7M))
+ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7EM))
+ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
+ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
+ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index f362c27..a68404e 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -43,134 +43,134 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2",	arm2, arm2,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
-ARM_CORE("arm250",	arm250, arm250,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
-ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
+ARM_CORE("arm2",	arm2, arm2,	2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm250",	arm250, arm250,	2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm3",	arm3, arm3,	2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm6",	arm6, arm6,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm60",	arm60, arm60,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm600",	arm600, arm600,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm610",	arm610, arm610,		3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm620",	arm620, arm620,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7",	arm7, arm7,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7d",	arm7d, arm7d,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7di",	arm7di, arm7di,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm70",	arm70, arm70,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700",	arm700, arm700,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700i",	arm700i, arm700i,	3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710",	arm710, arm710,		3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm720",	arm720, arm720,		3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710c",	arm710c, arm710c,	3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7100",	arm7100, arm7100,	3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500",	arm7500, arm7500,	3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
 /* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,	3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
-ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
-ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
-ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("arm8",          arm8, arm8,			4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm810",        arm810, arm810,		4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("strongarm",     strongarm, strongarm,		4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,	4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("fa526",         fa526, fa526,			4,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("fa626",         fa626, fa626,			4,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
-ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
-ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
-ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm710t",	arm710t, arm710t,	4T,	ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T),    fastmul)
+ARM_CORE("arm720t",	arm720t, arm720t,	4T,	ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T),    fastmul)
+ARM_CORE("arm740t",	arm740t, arm740t,	4T,	ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T),    fastmul)
+ARM_CORE("arm9",	arm9, arm9,		4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920",	arm920, arm920,		4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920t",	arm920t, arm920t,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm922t",	arm922t, arm922t,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm940t",	arm940t, arm940t,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("ep9312",	ep9312, ep9312,		4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
-ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
+ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
-ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
-ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
-ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE, xscale)
-ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE, xscale)
-ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE, xscale)
-ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fa726te)
+ARM_CORE("arm9e",	arm9e, arm9e,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm10e",	arm10e, arm10e,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("xscale",	xscale, xscale,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("fa606te",	fa606te, fa606te,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa626te",	fa626te, fa626te,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fmp626",	fmp626, fmp626,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa726te",	fa726te, fa726te,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
-ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
+ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED | FL_FOR_ARCH6J, 9e)
-ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J, 9e)
-ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED | FL_FOR_ARCH6ZK, 9e)
-ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK, 9e)
-ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED | FL_FOR_ARCH6K, 9e)
-ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K, 9e)
-ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED | FL_FOR_ARCH6T2, v6t2)
-ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2, v6t2)
+ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6ZK), 9e)
+ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK), 9e)
+ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6K), 9e)
+ARM_CORE("mpcore",		mpcore, mpcore,			6K,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K), 9e)
+ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
 
 /* V6M Architecture Processors */
-ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
 
 /* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
 
 /* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex)
-ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a5)
-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a7)
-ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a8)
-ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a9)
-ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
-ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM, cortex_m7)
-ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED | FL_FOR_ARCH7EM, v7m)
-ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED | FL_FOR_ARCH7M, v7m)
-ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED | FL_FOR_ARCH7A, marvell_pj4)
+ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex)
+ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5)
+ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8)
+ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9)
+ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
+ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7EM), v7m)
+ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7M), v7m)
+ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4)
 
 /* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
 
 /* V8 Architecture Processors */
-ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED | FL_FOR_ARCH8A,            xgene1)
+ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("xgene1",      xgene1,    xgene1,      8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A),            xgene1)
 
 /* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index dd892a7..30bd0c9 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2198,7 +2198,7 @@ static const struct processors all_cores[] =
   /* ARM Cores */
 #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
-   ARM_FSET_MAKE_CPU1 (FLAGS), &arm_##COSTS##_tune},
+   FLAGS, &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
   {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
@@ -2211,7 +2211,7 @@ static const struct processors all_architectures[] =
      from the core.  */
 
 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
-  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, ARM_FSET_MAKE_CPU1 (FLAGS), NULL},
+  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
 #include "arm-arches.def"
 #undef ARM_ARCH
   {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def
  2015-06-22 16:07 ` [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def Matthew Wahab
@ 2015-07-24 11:48   ` Matthew Wahab
  0 siblings, 0 replies; 8+ messages in thread
From: Matthew Wahab @ 2015-07-24 11:48 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1242 bytes --]

Ping. Updated patch attached.

Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and
make check and arm-none-eabi with cross-compiled make check.


On 22/06/15 16:54, Matthew Wahab wrote:
> Hello,
>
> The ARM backend uses an unsigned long to record CPU feature flags and there are
> currently 30 bits in use. This series of patches replaces the single unsigned
> long with a representation based on an array of values.
>
> This patch updates the entries in the arm-core.def and arm-arches.def files
> for the new arm_feature_set representation, moving the initializers from a macro
> expansion and making them explicit in the file entries.
>
> Tested for arm-none-linux-gnueabihf with check-gcc.
>
> Ok for trunk?
> Matthew
>
> gcc/
> 2015-08-22  Matthew Wahab  <matthew.wahab@arm.com>
>
> 	* config/arm/arm-arches.def: Replace single value flags with
> 	initializer built from ARM_FSET_MAKE_CPU1.
> 	* config/arm/arm-cores.def: Likewise.
> 	* config/arm/arm.c: (all_cores): Remove ARM_FSET_MAKE_CPU1
> 	derivation from the ARM_CORE macro definition, use the given value
> 	instead.
> 	(all_architectures): Remove ARM_FSET_MAKE_CPU1 derivation from the
> 	ARM_ARCH macro definition, use the given value instead.
>


[-- Attachment #2: 0004-Move-feature-sets-into-core-and-arch-def-files.patch --]
[-- Type: text/x-patch, Size: 28624 bytes --]

From 699d2d4c5b1683bddd2645690fd590ee8a812491 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 8 Jun 2015 16:15:52 +0100
Subject: [PATCH 4/4] Move feature sets into core and arch def files.

Change-Id: Ica484c7d9f46413c196b26a630ff49413b10289b
---
 gcc/config/arm/arm-arches.def |  56 ++++++------
 gcc/config/arm/arm-cores.def  | 200 +++++++++++++++++++++---------------------
 gcc/config/arm/arm.c          |   4 +-
 3 files changed, 130 insertions(+), 130 deletions(-)

diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 840c1ff..6d0374a 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -28,33 +28,33 @@
 
    genopt.sh assumes no whitespace up to the first "," in each entry.  */
 
-ARM_ARCH("armv2",   arm2,       2,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2)
-ARM_ARCH("armv2a",  arm2,       2,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2)
-ARM_ARCH("armv3",   arm6,       3,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3)
-ARM_ARCH("armv3m",  arm7m,      3M,  FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M)
-ARM_ARCH("armv4",   arm7tdmi,   4,   FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4)
+ARM_ARCH("armv2",   arm2,       2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv2a",  arm2,       2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv3",   arm6,       3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3))
+ARM_ARCH("armv3m",  arm7m,      3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M))
+ARM_ARCH("armv4",   arm7tdmi,   4,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4))
 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
    implementations that support it, so we will leave it out for now.  */
-ARM_ARCH("armv4t",  arm7tdmi,   4T,  FL_CO_PROC |             FL_FOR_ARCH4T)
-ARM_ARCH("armv5",   arm10tdmi,  5,   FL_CO_PROC |             FL_FOR_ARCH5)
-ARM_ARCH("armv5t",  arm10tdmi,  5T,  FL_CO_PROC |             FL_FOR_ARCH5T)
-ARM_ARCH("armv5e",  arm1026ejs, 5E,  FL_CO_PROC |             FL_FOR_ARCH5E)
-ARM_ARCH("armv5te", arm1026ejs, 5TE, FL_CO_PROC |             FL_FOR_ARCH5TE)
-ARM_ARCH("armv6",   arm1136js,  6,   FL_CO_PROC |             FL_FOR_ARCH6)
-ARM_ARCH("armv6j",  arm1136js,  6J,  FL_CO_PROC |             FL_FOR_ARCH6J)
-ARM_ARCH("armv6k",  mpcore,	6K,  FL_CO_PROC |             FL_FOR_ARCH6K)
-ARM_ARCH("armv6z",  arm1176jzs, 6Z,  FL_CO_PROC |             FL_FOR_ARCH6Z)
-ARM_ARCH("armv6zk", arm1176jzs, 6ZK, FL_CO_PROC |             FL_FOR_ARCH6ZK)
-ARM_ARCH("armv6t2", arm1156t2s, 6T2, FL_CO_PROC |             FL_FOR_ARCH6T2)
-ARM_ARCH("armv6-m", cortexm1,	6M,			      FL_FOR_ARCH6M)
-ARM_ARCH("armv6s-m", cortexm1,	6M,			      FL_FOR_ARCH6M)
-ARM_ARCH("armv7",   cortexa8,	7,   FL_CO_PROC |	      FL_FOR_ARCH7)
-ARM_ARCH("armv7-a", cortexa8,	7A,  FL_CO_PROC |	      FL_FOR_ARCH7A)
-ARM_ARCH("armv7ve", cortexa8,	7A,  FL_CO_PROC |	      FL_FOR_ARCH7VE)
-ARM_ARCH("armv7-r", cortexr4,	7R,  FL_CO_PROC |	      FL_FOR_ARCH7R)
-ARM_ARCH("armv7-m", cortexm3,	7M,  FL_CO_PROC |	      FL_FOR_ARCH7M)
-ARM_ARCH("armv7e-m", cortexm4,  7EM, FL_CO_PROC |	      FL_FOR_ARCH7EM)
-ARM_ARCH("armv8-a", cortexa53,  8A,  FL_CO_PROC |             FL_FOR_ARCH8A)
-ARM_ARCH("armv8-a+crc",cortexa53, 8A,FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A)
-ARM_ARCH("iwmmxt",  iwmmxt,     5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)
-ARM_ARCH("iwmmxt2", iwmmxt2,    5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
+ARM_ARCH("armv4t",  arm7tdmi,   4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH4T))
+ARM_ARCH("armv5",   arm10tdmi,  5,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5))
+ARM_ARCH("armv5t",  arm10tdmi,  5T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5T))
+ARM_ARCH("armv5e",  arm1026ejs, 5E,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5E))
+ARM_ARCH("armv5te", arm1026ejs, 5TE,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5TE))
+ARM_ARCH("armv6",   arm1136js,  6,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6))
+ARM_ARCH("armv6j",  arm1136js,  6J,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6J))
+ARM_ARCH("armv6k",  mpcore,	6K,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6K))
+ARM_ARCH("armv6z",  arm1176jzs, 6Z,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6Z))
+ARM_ARCH("armv6zk", arm1176jzs, 6ZK,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6ZK))
+ARM_ARCH("armv6t2", arm1156t2s, 6T2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6T2))
+ARM_ARCH("armv6-m", cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv6s-m", cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv7",   cortexa8,	7,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7))
+ARM_ARCH("armv7-a", cortexa8,	7A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7A))
+ARM_ARCH("armv7ve", cortexa8,	7A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7VE))
+ARM_ARCH("armv7-r", cortexr4,	7R,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7R))
+ARM_ARCH("armv7-m", cortexm3,	7M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7M))
+ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7EM))
+ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
+ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
+ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index f362c27..a68404e 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -43,134 +43,134 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2",	arm2, arm2,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
-ARM_CORE("arm250",	arm250, arm250,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
-ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
+ARM_CORE("arm2",	arm2, arm2,	2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm250",	arm250, arm250,	2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm3",	arm3, arm3,	2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
-ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm6",	arm6, arm6,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm60",	arm60, arm60,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm600",	arm600, arm600,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm610",	arm610, arm610,		3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm620",	arm620, arm620,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7",	arm7, arm7,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7d",	arm7d, arm7d,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7di",	arm7di, arm7di,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm70",	arm70, arm70,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700",	arm700, arm700,		3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700i",	arm700i, arm700i,	3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710",	arm710, arm710,		3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm720",	arm720, arm720,		3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710c",	arm710c, arm710c,	3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7100",	arm7100, arm7100,	3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500",	arm7500, arm7500,	3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
 /* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,	3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
-ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
-ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
-ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
-ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("arm8",          arm8, arm8,			4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm810",        arm810, arm810,		4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("strongarm",     strongarm, strongarm,		4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,	4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
+ARM_CORE("fa526",         fa526, fa526,			4,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("fa626",         fa626, fa626,			4,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
-ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
-ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
-ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
-ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm710t",	arm710t, arm710t,	4T,	ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T),    fastmul)
+ARM_CORE("arm720t",	arm720t, arm720t,	4T,	ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T),    fastmul)
+ARM_CORE("arm740t",	arm740t, arm740t,	4T,	ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T),    fastmul)
+ARM_CORE("arm9",	arm9, arm9,		4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920",	arm920, arm920,		4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920t",	arm920t, arm920t,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm922t",	arm922t, arm922t,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm940t",	arm940t, arm940t,	4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("ep9312",	ep9312, ep9312,		4T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
-ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
+ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
-ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
-ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
-ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE, xscale)
-ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE, xscale)
-ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE, xscale)
-ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
-ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fa726te)
+ARM_CORE("arm9e",	arm9e, arm9e,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm10e",	arm10e, arm10e,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("xscale",	xscale, xscale,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("fa606te",	fa606te, fa606te,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa626te",	fa626te, fa626te,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fmp626",	fmp626, fmp626,		5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa726te",	fa726te, fa726te,	5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
-ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
+ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED | FL_FOR_ARCH6J, 9e)
-ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J, 9e)
-ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED | FL_FOR_ARCH6ZK, 9e)
-ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK, 9e)
-ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED | FL_FOR_ARCH6K, 9e)
-ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K, 9e)
-ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED | FL_FOR_ARCH6T2, v6t2)
-ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2, v6t2)
+ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6ZK), 9e)
+ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK), 9e)
+ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6K), 9e)
+ARM_CORE("mpcore",		mpcore, mpcore,			6K,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K), 9e)
+ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
 
 /* V6M Architecture Processors */
-ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
 
 /* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
 
 /* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex)
-ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a5)
-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a7)
-ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a8)
-ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a9)
-ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
-ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
-ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM, cortex_m7)
-ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED | FL_FOR_ARCH7EM, v7m)
-ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED | FL_FOR_ARCH7M, v7m)
-ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED | FL_FOR_ARCH7A, marvell_pj4)
+ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex)
+ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5)
+ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8)
+ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9)
+ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
+ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7EM), v7m)
+ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7M), v7m)
+ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4)
 
 /* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
 
 /* V8 Architecture Processors */
-ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED | FL_FOR_ARCH8A,            xgene1)
+ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("xgene1",      xgene1,    xgene1,      8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A),            xgene1)
 
 /* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4190b3f..321d744 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2194,7 +2194,7 @@ static const struct processors all_cores[] =
   /* ARM Cores */
 #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
-   ARM_FSET_MAKE_CPU1 (FLAGS), &arm_##COSTS##_tune},
+   FLAGS, &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
   {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
@@ -2207,7 +2207,7 @@ static const struct processors all_architectures[] =
      from the core.  */
 
 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
-  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, ARM_FSET_MAKE_CPU1 (FLAGS), NULL},
+  {NAME, CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
 #include "arm-arches.def"
 #undef ARM_ARCH
   {NULL, arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 1/4][ARM] Make room for more CPU feature flags.
  2015-06-22 15:44 [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
                   ` (2 preceding siblings ...)
  2015-06-22 16:07 ` [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def Matthew Wahab
@ 2015-07-24 11:36 ` Matthew Wahab
  3 siblings, 0 replies; 8+ messages in thread
From: Matthew Wahab @ 2015-07-24 11:36 UTC (permalink / raw)
  To: gcc-patches

[-- Attachment #1: Type: text/plain, Size: 1721 bytes --]

Ping. Updated patch attached.

Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and
make check and arm-none-abi with cross-compiled make check.

On 22/06/15 16:41, Matthew Wahab wrote:
> Hello,
>
> The ARM backend uses an unsigned long to record CPU feature flags and there are
> currently 30 bits in use. To be able to support new architecture features, the
> current representation will need to be replaced so that more flags can be
> recorded.
>
> This series of patches replaces the single unsigned long with a representation
> based on an array of unsigned longs. Constructors and operations are explicitly
> defined for the new representation and the backend is updated to use the new
> operations.
>
> The individual patches:
> - Make architecture flags explicit in arm-cores.def, to prepare for the changes.
> - Add definitions for the new representation as type arm_feature_set and macros
>     with prefix ARM_FSET.
> - Replace uses of the old representation with the arm_feature_set type and
>     operations.
> - Rework arm-cores.def and arm-arches.def to make the feature set constructions
>     explicit.
>
> The series tested for arm-none-linux-gnueabihf with check-gcc.
>
> This patch moves the derived FL_FOR_ARCH##ARCH flags from the expansion of macro
> arm.c/ARM_CORE and makes them explicit in the entries in arm-cores.def.
>
> This patch tested for arm-none-linux-gnueabihf with check-gcc.
>
> Ok for trunk?
> Matthew
>
> 2015-06-22  Matthew Wahab  <matthew.wahab@arm.com>
>
> 	* gcc/config/arm/arm-cores.def: Add FL_FOR_ARCH flag for each
> 	ARM_CORE entry.  Fix some white-space.
> 	* gcc/config/arm/arm.c: Remove FL_FOR_ARCH derivation from
> 	ARM_CORE definition.
>


[-- Attachment #2: 0001-ARM-Make-ARCH-flags-explicit-in-arm-cores.def.patch --]
[-- Type: text/x-patch, Size: 19225 bytes --]

From 898ac2cb977df8739a5bee7a16c78410f04c6dab Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 5 Jun 2015 12:33:34 +0100
Subject: [PATCH 1/4] [ARM] Make ARCH flags explicit in arm-cores.def

Change-Id: I13a79c89bebaf82aa921f0502b721ff5d9b92dbe
---
 gcc/config/arm/arm-cores.def | 200 +++++++++++++++++++++----------------------
 gcc/config/arm/arm.c         |   2 +-
 2 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 103c314..f362c27 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -43,134 +43,134 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2", 	arm2, arm2,	2, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm250", 	arm250, arm250,	2, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm2",	arm2, arm2,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
+ARM_CORE("arm250",	arm250, arm250,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
+ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
+ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
 /* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3, slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26, fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26, fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26, fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED, fastmul)
-ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED, fastmul)
-ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED, fastmul)
-ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED, fastmul)
+ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4, strongarm)
+ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
+ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED | FL_FOR_ARCH4, fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC, fastmul)
-ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC, fastmul)
-ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF,    fastmul)
-ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF,    fastmul)
-ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF,    fastmul)
-ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED, fastmul)
-ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
+ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
+ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF | FL_FOR_ARCH4T,    fastmul)
+ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
+ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED | FL_FOR_ARCH4T, fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED, fastmul)
-ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED, fastmul)
+ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
+ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED | FL_FOR_ARCH5T, fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED, fastmul)
-ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED, fastmul)
-ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED, fastmul)
-ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale)
-ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
-ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale)
-ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED, 9e)
-ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED, 9e)
-ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED, fa726te)
+ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
+ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
+ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fastmul)
+ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE, xscale)
+ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE, xscale)
+ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE, xscale)
+ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED | FL_FOR_ARCH5TE, 9e)
+ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED | FL_FOR_ARCH5TE, fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED, 9e)
-ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED, 9e)
+ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
+ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED | FL_FOR_ARCH5TEJ, 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED, 9e)
-ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED, 9e)
-ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED, 9e)
-ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED, v6t2)
-ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2, v6t2)
+ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED | FL_FOR_ARCH6J, 9e)
+ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J, 9e)
+ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED | FL_FOR_ARCH6ZK, 9e)
+ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6ZK, 9e)
+ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED | FL_FOR_ARCH6K, 9e)
+ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K, 9e)
+ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED | FL_FOR_ARCH6T2, v6t2)
+ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2, v6t2)
 
 /* V6M Architecture Processors */
-ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED, v6m)
-ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED, v6m)
-ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED, v6m)
+ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED | FL_FOR_ARCH6M, v6m)
 
 /* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M, FL_LDSCHED | FL_SMALLMUL, v6m)
-ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M, FL_LDSCHED | FL_SMALLMUL, v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, FL_LDSCHED | FL_SMALLMUL, v6m)
+ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M, v6m)
 
 /* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED, cortex)
-ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED, cortex_a5)
-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
-ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED, cortex_a8)
-ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED, cortex_a9)
-ARM_CORE("cortex-a12",	  	cortexa12, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
-ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED, cortex)
-ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED, cortex)
-ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED | FL_NO_VOLATILE_CE, cortex_m7)
-ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED, v7m)
-ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED, v7m)
-ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED, marvell_pj4)
+ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex)
+ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a5)
+ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a7)
+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a8)
+ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED | FL_FOR_ARCH7A, cortex_a9)
+ARM_CORE("cortex-a12",		cortexa12, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
+ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
+ARM_CORE("cortex-a17",		cortexa17, cortexa17,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
+ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R, cortex)
+ARM_CORE("cortex-m7",		cortexm7, cortexm7,		7EM, FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM, cortex_m7)
+ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED | FL_FOR_ARCH7EM, v7m)
+ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED | FL_FOR_ARCH7M, v7m)
+ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED | FL_FOR_ARCH7A, marvell_pj4)
 
 /* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A, cortex_a12)
 
 /* V8 Architecture Processors */
-ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32, cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A, FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED,            xgene1)
+ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a53)
+ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("cortex-a72",	cortexa72, cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("exynos-m1",	exynosm1,  cortexa57,	8A, FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED | FL_FOR_ARCH8A,            xgene1)
 
 /* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A, cortex_a57)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e1bc727..4f90203 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2193,7 +2193,7 @@ static const struct processors all_cores[] =
   /* ARM Cores */
 #define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
-    FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
+    FLAGS, &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
   {NULL, arm_none, NULL, BASE_ARCH_0, 0, NULL}
-- 
1.9.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2015-07-24 11:39 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-22 15:44 [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab
2015-06-22 15:51 ` [PATCH 2/4][ARM] Add feature set definitions Matthew Wahab
2015-07-24 11:39   ` Matthew Wahab
2015-06-22 15:54 ` [PATCH 3/4][ARM] Use new feature set representation Matthew Wahab
2015-07-24 11:41   ` Matthew Wahab
2015-06-22 16:07 ` [PATCH 4/4][ARM] Move initializer into arm-cores.def and arm-arches.def Matthew Wahab
2015-07-24 11:48   ` Matthew Wahab
2015-07-24 11:36 ` [PATCH 1/4][ARM] Make room for more CPU feature flags Matthew Wahab

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).